KR970030358A - Contact formation method of semiconductor device - Google Patents

Contact formation method of semiconductor device Download PDF

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Publication number
KR970030358A
KR970030358A KR1019950043628A KR19950043628A KR970030358A KR 970030358 A KR970030358 A KR 970030358A KR 1019950043628 A KR1019950043628 A KR 1019950043628A KR 19950043628 A KR19950043628 A KR 19950043628A KR 970030358 A KR970030358 A KR 970030358A
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KR
South Korea
Prior art keywords
forming
film
layer
conductive layer
photoresist pattern
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KR1019950043628A
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Korean (ko)
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KR0172505B1 (en
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황준
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김주용
현대전자산업 주식회사
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Priority to KR1019950043628A priority Critical patent/KR0172505B1/en
Publication of KR970030358A publication Critical patent/KR970030358A/en
Application granted granted Critical
Publication of KR0172505B1 publication Critical patent/KR0172505B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 다층 구조의 콘택 형성시 콘택 저항을 크게 감소시키고, 평탄도를 증대시킬 수 있는 반도체 소자의 콘택 형성방법에 관한 것으로, 반도체 소자 제조공정 중 소자의 소자간의 전기적 연결을 위한 콘택 형성방법에 있어서, 제1도전층, 제2도전층을 차례로 형성하는 제1 단계; 상기 제2도전층 상부에 감광막패턴을 형성한 다음, 이를 마스크로 사용한 식각공정을 통해 상기 제2금속층을 식각하는 제2 단계; 상기 제1 단계 및 제2 단계에 의한 구조의 전체 상부에 감광막이 없는 지역에만 선택적으로 증착되는 LPD(Liquid Phase Dielectrics)막을 형성하는 제3 단계; 상기 감광막패턴을 제거한 다음, 평탄화 특성이 우수한 평탄화절연막을 형성하는 제4단계; 및 상기 평탄화절연막을 에치-백(etch-back)하여 평탄화한 다음, 전체 상부에 제3 금속층을 형성하는 제5단계를 포함하여 이루어지는 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact of a semiconductor device which can greatly reduce contact resistance and increase flatness when forming a multi-layer contact. A first step of sequentially forming a first conductive layer, the second conductive layer; A second step of forming a photoresist pattern on the second conductive layer and then etching the second metal layer through an etching process using the photoresist pattern; A third step of forming a Liquid Phase Dielectrics (LPD) film selectively deposited only in a region where no photoresist film is formed over the entire structure of the first and second structures; Removing the photoresist pattern, and then forming a planarization insulating film having excellent planarization characteristics; And a fifth step of etching and flattening the planarization insulating layer, and then forming a third metal layer over the entire surface.

Description

반도체 소자의 콘택 형성방법Contact formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1D도는 본 발명의 실시예에 따른 콘택 형성 과정을 나타내는 단면도.1D is a cross-sectional view illustrating a process for forming a contact according to an embodiment of the present invention.

Claims (5)

반도체 소자 제조공정 중 소자의 소자간의 전기적 연결을 위한 콘택 형성방법에 있어서, 제1도전층, 제2도전층을 차례로 형성하는 제1 단계; 상기 제2도전층 상부에 감광막패턴을 형성한 다음, 이를 마스크로 사용한 식각공정을 통해 상기 제2금속층을 식각하는 제2단계; 상기 제1 단계 및 제2 단계에 의한 구조의 전체 상부에 감광막이 없는 지역에만 선택적으로 증착되는 LPD(Liquid Phase Dielectrics)막을 형성하는 제3 단계; 상기 감광막패턴을 제거한 다음, 평탄화 특성이 우수한 평탄화절연막을 형성하는 제4 단계; 및 상기 평탄화절연막을 에치-백(etch-back)하여 평탄화한 다음, 전체 상부에 제3 금속층을 형성하는 제5단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 콘택 형성방법.A method for forming a contact for electrical connection between devices in a semiconductor device manufacturing process, the method comprising: a first step of sequentially forming a first conductive layer and a second conductive layer; Forming a photoresist pattern on the second conductive layer and then etching the second metal layer through an etching process using the photoresist pattern as a mask; A third step of forming a Liquid Phase Dielectrics (LPD) film selectively deposited only in a region where no photoresist film is formed over the entire structure of the first and second structures; Removing the photoresist pattern, and then forming a planarization insulating film having excellent planarization characteristics; And a fifth step of etching and planarizing the planarization insulating layer, and then forming a third metal layer on the entire upper surface of the planarization insulating layer. 제1항에 있어서, 상기 제4 단계의 평탄화절연막은 LPD막 또는 SOG(Spin On Glass)막 중 어느 하나로 이루어지는 것을 특징으로 하는 반도체 소자의 콘택 형성방법.The method of claim 1, wherein the planarization insulating film of the fourth step comprises one of an LPD film and a spin on glass (SOG) film. 제1항 또는 제2항에 있어서, 상기 도전층은 금속막으로 이루어지는 것을 특징으로 하는 반도체 소자의 콘택 형성방법.The method for forming a contact of a semiconductor device according to claim 1 or 2, wherein the conductive layer is made of a metal film. 제3항에 있어서, 상기 제2 도전층은 상기 제1 금속막과 제3 금속막간의 접착력을 증대시키기 위한 접착력증가층을 더 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 콘택 형성방법.The method of claim 3, wherein the second conductive layer further comprises an adhesion increasing layer for increasing adhesion between the first metal film and the third metal film. 제4항에 있어서, 상기 접착력 증가층은 TiN 막 또는 TiW막 중 어느 하나로 이루어지는 것을 특징으로 하는 반도체 소자의 콘택 형성방법.The method of claim 4, wherein the adhesion increasing layer is formed of any one of a TiN film and a TiW film.
KR1019950043628A 1995-11-24 1995-11-24 Method of forming contact on semiconductor device KR0172505B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950043628A KR0172505B1 (en) 1995-11-24 1995-11-24 Method of forming contact on semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950043628A KR0172505B1 (en) 1995-11-24 1995-11-24 Method of forming contact on semiconductor device

Publications (2)

Publication Number Publication Date
KR970030358A true KR970030358A (en) 1997-06-26
KR0172505B1 KR0172505B1 (en) 1999-03-30

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