KR100290466B1 - Method of manufacturing a semiconductor device - Google Patents

Method of manufacturing a semiconductor device Download PDF

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KR100290466B1
KR100290466B1 KR1019970081141A KR19970081141A KR100290466B1 KR 100290466 B1 KR100290466 B1 KR 100290466B1 KR 1019970081141 A KR1019970081141 A KR 1019970081141A KR 19970081141 A KR19970081141 A KR 19970081141A KR 100290466 B1 KR100290466 B1 KR 100290466B1
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South Korea
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contact hole
via contact
photoresist pattern
spin
forming
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KR1019970081141A
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Korean (ko)
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KR19990060895A (en
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양기홍
홍택기
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박종섭
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A fabrication method of semiconductor devices is provided to improve a step coverage and to prevent a bowing of an SOG(Spin On Glass) by forming a via contact hole having a positive slope without using a wet etching. CONSTITUTION: After forming a lower metal film(12) on a semiconductor substrate(11), a first insulating layer(13) and an SOG film(14) are sequentially formed. A first via contact hole(17A) is formed by dry etching the SOG film(14) and the first insulating layer(13) using a first photoresist pattern(21) as a mask. The first photoresist pattern(21) is removed by oxygen plasma and the SOG film(14) is partially etched by increasing an exposure time of the oxygen plasma, thereby forming a second via contact hole(17B) having wider diameter compared to the first via contact hole. A second insulating layer(15) is formed on the resultant structure. A via contact hole(17) is formed by etching the second insulating layer(15) using a second photoresist pattern(22) as a mask. After removing the second photoresist pattern(22), an upper metal film(18) is formed on the resultant structure.

Description

반도체 소자의 제조 방법{Method of manufacturing a semiconductor device}Method of manufacturing a semiconductor device

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 제 1 절연막, 스핀 온 글라스(Spin On Glass; SOG)막 및 제 2 절연막으로 이루어진 금속 층간 절연막에 형성되는 비아 콘택홀(via contact hole)이 습식 식각 없이 포지티브 경사 (positive slope)를 갖게 하여 스텝 커버리지(step coverage)를 개선시키고, 비아 콘택홀 측벽면에 스핀 온 글라스막이 노출되지 않도록 하여 스핀 온 글라스막의 굴곡(bowing) 현상을 배제시킬 수 있는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, a via contact hole formed in a metal interlayer insulating film including a first insulating film, a spin on glass (SOG) film, and a second insulating film is wet. A semiconductor that has a positive slope without etching to improve step coverage and prevents the spin on glass film from being exposed on the sidewalls of the via contact hole, thereby eliminating the bowing of the spin on glass film. A method for manufacturing a device.

일반적으로, 다층간 금속 배선을 사용하는 초고집적 반도체 소자 제조에 있어서, 금속 층간 절연막으로 스핀 온 글라스막이 널리 사용되고 있다. 스핀 온 글라스막이 널리 사용되는 이유는 회전 도포 후 열 경화 방법으로 형성하기 때문에 금속 패턴간의 간극 매립 특성이 다른 방법보다 탁월하고 평탄화 특성이 우수할 뿐만 아니라 공정이 단순하고 공정 단가가 저렴하기 때문이다.In general, in the manufacture of ultra-high density semiconductor devices using multi-layer metal wiring, spin-on glass films are widely used as metal interlayer insulating films. The reason why the spin-on glass film is widely used is that the gap-filling property between the metal patterns is superior to other methods, the planarization property is excellent, and the process is simple and the process cost is low because it is formed by the thermal curing method after the spin coating.

다층간 금속 배선 형성시, 하부 금속 배선과 상부 금속 배선을 연결하기 위해 하부 금속 배선 상에 형성된 금속 층간 절연막을 습식 식각 및 건식 식각 공정으로 포지티브 경사를 갖는 비아 콘택홀을 형성하고, 후속으로 상부 금속 배선 형성용 금속층을 증착 한다.In the formation of the multi-layered metal interconnection, a metal interlayer insulating layer formed on the lower metal interconnection to form a via contact hole having a positive slope by wet etching and dry etching processes to connect the lower metal interconnection and the upper metal interconnection, and subsequently the upper metal The metal layer for wiring formation is deposited.

도 1은 종래 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도이다.1 is a cross-sectional view of a device for explaining a method of manufacturing a conventional semiconductor device.

반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 기판(1)상에 하부 금속 배선(2)이 형성된다. 하부 금속 배선(2)을 포함한 전체 구조상에 제 1 절연막 (3), 스핀 온 글라스막(4) 및 제 2 절연막(5)를 순차적으로 형성하여 금속 층간 절연막(6)이 완성된다. 금속 층간 절연막(6)의 선택된 부분을 습식 식각 및 건식 식각 공정으로 식각하여 하부 금속 배선(2)이 노출되는 포지티브 경사를 갖는 비아 콘택홀(7)이 형성된다. 비아 콘택홀(7) 형성시 식각 마스크로 사용되는 감광막은 주로 산소 플라즈마를 이용하여 제거하게 되는데, 스핀 온 글라스막(4)이 산소 플라즈마와의 반응으로 수축하여 비아 콘택홀(7)의 측벽면에 굴곡(bowing) 현상을 유발시키게 된다. 이러한 비아 콘택홀(7)을 포함한 전체 구조 상에 금속층 증착 및 패터닝 공정으로 상부 금속 배선(8)이 형성된다.The lower metal wiring 2 is formed on a substrate 1 having a structure in which various elements for forming a semiconductor element are formed. The metal interlayer insulating film 6 is completed by sequentially forming the first insulating film 3, the spin-on glass film 4, and the second insulating film 5 on the entire structure including the lower metal wiring 2. Selected portions of the metal interlayer insulating film 6 are etched by wet etching and dry etching processes to form via contact holes 7 having positive inclinations through which the lower metal wirings 2 are exposed. When the via contact hole 7 is formed, the photoresist film, which is used as an etch mask, is mainly removed by using an oxygen plasma. The spin-on glass film 4 contracts in response to the oxygen plasma to form a sidewall of the via contact hole 7. This causes bowing. The upper metal wiring 8 is formed by the metal layer deposition and patterning process on the entire structure including the via contact hole 7.

상기한 종래 방법에 의해 형성된 비아 콘택홀(7)은 측벽면에 굴곡 현상이 발생되기 때문에 상부 금속 배선(8)을 형성하기 위한 금속층 증착시 금속 스텝 커버리지가 불량하게 되어 비아 콘택홀(7) 부분에서 상부 금속 배선(8)의 단선 또는 가늘어지는 현상이 발생할 수 있고(저온에서 금속층을 증착할 경우), 또한 비아 콘택홀(7) 부분에서 상부 금속 배선(8)에 보이드(void)가 발생할 수 있다(고온에서 금속층을 증착할 경우). 이와 같은 상부 금속 배선(8)의 비아 콘택홀(7) 내에서의 단선, 세선 및 보이드 등의 문제점으로 인하여 배선 불량, 저항 증가, 소자 사용중 전류열에 의한 단선 등이 발생하여 소자의 수율 저하나 수명의 단축 등이 초래된다.Since the via contact hole 7 formed by the above-described conventional method has a bending phenomenon on the sidewall surface, the metal step coverage is poor when the metal layer for forming the upper metal wiring 8 is deposited. Disconnection or thinning of the upper metal wiring 8 may occur (when the metal layer is deposited at low temperature), and voids may occur in the upper metal wiring 8 in the via contact hole 7. (If depositing a metal layer at high temperature). Due to such problems as disconnection, thin wire, and voids in the via contact hole 7 of the upper metal wiring 8, poor wiring, increased resistance, and disconnection due to current heat while the device is in use may cause a decrease in yield or lifespan of the device. Shortening and so on.

따라서, 본 발명은 제 1 절연막, 스핀 온 글라스막 및 제 2 절연막으로 이루어진 금속 층간 절연막에 형성되는 비아 콘택홀을 습식 식각 없이 포지티브 경사를 갖게 하고, 비아 콘택홀 측벽면에 스핀 온 글라스막이 노출되지 않도록 하여 스핀온 글라스막의 굴곡 현상을 배제시키므로써, 금속 스텝 커버리지가 개선되어 소자의 수율 및 신뢰성을 향상시킬 수 있는 반도체 소자의 제조 방법을 제공함에 그 목적이 있다.Accordingly, the present invention allows the via contact hole formed in the metal interlayer insulating film including the first insulating film, the spin on glass film, and the second insulating film to have a positive slope without wet etching, and does not expose the spin on glass film on the sidewalls of the via contact hole. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can improve the yield and reliability of the device by improving the metal step coverage by preventing the bending phenomenon of the spin-on glass film.

이러한 목적을 달성하기 위한 본 발명의 반도체 소자의 제조 방법은 반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 기판 상에 하부 금속 배선을 형성하고, 상기 하부 금속 배선을 포함한 전체 구조 상에 제 1 절연막 및 스핀 온 글라스막을 순차적으로 형성하는 단계; 제 1 감광막 패턴을 식각 마스크로 한 건식 식각 공정으로 상기 스핀 온 글라스막 및 상기 제 1 절연막을 순차적으로 식각하여 제 1 비아 콘택홀을 형성하는 단계; 상기 제 1 감광막 패턴을 산소 플라즈마로 제거하되, 산소 플라즈마의 노출시간을 증가시켜 상기 스핀 온 글라스막이 일부 식각되도록 하여 상기 제 1 비아 콘택홀의 크기보다 큰 제 2 비아 콘택홀을 형성하는 단계; 상기 제 2 비아 콘택홀을 포함한 전체 구조상에 제 2 절연막을 형성하는 단계; 및 제 2 감광막 패턴을 식각 마스크로 한 건식 식각 공정으로 상기 제 2 절연막을 식각한 후, 상기 제 2 감광막 패턴을 제거하여 비아 콘택홀을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The semiconductor device manufacturing method of the present invention for achieving the above object is to form a lower metal wiring on a substrate having a structure formed with a number of elements for forming a semiconductor device, a first insulating film on the entire structure including the lower metal wiring And sequentially forming a spin on glass film. Forming a first via contact hole by sequentially etching the spin-on glass film and the first insulating film by a dry etching process using the first photoresist pattern as an etching mask; Removing the first photoresist pattern with oxygen plasma, and increasing the exposure time of the oxygen plasma to partially etch the spin-on glass layer to form a second via contact hole larger than the size of the first via contact hole; Forming a second insulating film on the entire structure including the second via contact hole; And etching the second insulating film by a dry etching process using the second photoresist pattern as an etch mask, and then removing the second photoresist pattern to form a via contact hole.

도 1은 종래 반도체 소자의 제조 방법을 설명하기 위해 도시된 소자의 단면도.1 is a cross-sectional view of a device shown for explaining a method of manufacturing a conventional semiconductor device.

도 2(a) 내지 도 2(d)는 본 발명의 실시 예에 따른 반도체 소자의 제조 방법을 설명하기 위해 도시된 소자의 단면도.2 (a) to 2 (d) are cross-sectional views of a device shown for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

<도면의 주요부분에 대한 기호설명><Description of Symbols on Main Parts of Drawing>

1 및 11: 기판 2 및 12: 하부 금속 배선1 and 11: Substrate 2 and 12: lower metal wiring

3 및 13: 제 1 절연막 4 및 14: 스핀 온 글라스막3 and 13: first insulating film 4 and 14: spin on glass film

5 및 15: 제 2 절연막 6 및 16: 금속 층간 절연막5 and 15: second insulating film 6 and 16: metal interlayer insulating film

7 및 17: 비아 콘택홀 8 및 18: 상부 금속 배선7 and 17: Via contact holes 8 and 18: Upper metal wiring

17A 및 17B: 제 1 및 2 비아 콘택홀 21: 제 1 감광막 패턴17A and 17B: first and second via contact holes 21: first photoresist pattern

22: 제 2 감광막 패턴22: second photosensitive film pattern

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2(a) 내지 도 2(d)는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위해 도시된 소자의 단면도이다.2 (a) to 2 (d) are cross-sectional views of the device shown for explaining a method of manufacturing a semiconductor device according to the present invention.

도 2(a)를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 기판(11)상에 하부 금속 배선(12)이 형성된다. 하부 금속 배선(12)을 포함한 전체 구조 상에 실리콘 나이트라이드(silicon nitride)로된 제 1 절연막(13) 및 스핀 온 글라스막(14)이 순차적으로 형성된다. 비아 콘택 마스크를 사용한 포토리소그라피(photolithography) 공정으로 스핀 온 글라스막(14)상에 제 1 감광막 패턴(21)을 형성하고, 제 1 감광막 패턴(21)을 식각 마스크로 한 건식 식각 공정으로 스핀 온 글라스막(14) 및 제 1 절연막(13)의 선택된 부분을 식각하여 하부 금속 배선(12)이 노출된 제 1 비아 콘택홀(17A)을 형성한다. 제 1 비아 콘택홀(17A)의 형상은 수직 모양을 갖는다.Referring to FIG. 2A, a lower metal wiring 12 is formed on a substrate 11 having a structure in which various elements for forming a semiconductor device are formed. The first insulating film 13 and the spin on glass film 14 made of silicon nitride are sequentially formed on the entire structure including the lower metal wiring 12. The first photoresist pattern 21 is formed on the spin-on glass film 14 by a photolithography process using a via contact mask, and the spin-on process is performed by a dry etching process using the first photoresist pattern 21 as an etch mask. Selected portions of the glass film 14 and the first insulating film 13 are etched to form a first via contact hole 17A through which the lower metal wire 12 is exposed. The shape of the first via contact hole 17A has a vertical shape.

도 2(b)를 참조하면, 제 1 감광막 패턴(21)을 산소 플라즈마를 이용하여 제거한다. 이때 스핀 온 글라스막(14) 내의 유기 성분량(5 내지 20 wt%)에 따라 산소 플라즈마를 기존 노출 시간보다 50 내지 200초간 더 노출시켜 유기 성분의 스핀 온 글라스막(14)이 산소 플라즈마와 반응되어 일부 식각된다. 산소 플라즈마에 의해 제 1 비아 콘택홀(17A)을 이루는 스핀 온 글라스막(14)은 상단이 하단보다 많이 식각되어져 포지티브 경사를 갖으며, 제 1 비아 콘택홀(17A)의 크기보다 1.5 내지 2.5배 정도 큰 제 2 비아 콘택홀(17B)이 형성된다.Referring to FIG. 2B, the first photoresist pattern 21 is removed using an oxygen plasma. At this time, the oxygen plasma is further exposed for 50 to 200 seconds according to the amount of organic components (5 to 20 wt%) in the spin on glass film 14, thereby causing the spin on glass film 14 of the organic component to react with the oxygen plasma. Some are etched. The spin-on glass film 14 forming the first via contact hole 17A by the oxygen plasma has a positive slope because the upper end thereof is more etched than the lower end thereof, and has 1.5 to 2.5 times the size of the first via contact hole 17A. A large second via contact hole 17B is formed.

도 2(c)를 참조하면, 제 2 비아 콘택홀(17B)을 포함한 스핀 온 글라스막(14)상에 실리콘 리치 옥사이드(silicon rich oxide) 또는 O3-TEOS로 된 제 2 절연막 (15)을 형성하여 금속 층간 절연막(16)을 완성하고, 비아 콘택 마스크를 다시 사용한 포토리소그라피 공정으로 금속 층간 절연막(16)상에 제 2 감광막 패턴(22)을 형성한 후, 제 2 감광막 패턴(22)을 식각 마스크로 한 건식 식각 공정으로 제 2 절연막(15)의 선택된 부분을 식각하여 하부 금속 배선(12)이 노출된 비아 콘택홀(17)을 형성한다.Referring to FIG. 2C, a second insulating film 15 made of silicon rich oxide or O 3 -TEOS is formed on the spin-on glass film 14 including the second via contact hole 17B. After forming the second interlayer insulating film 16 to form a second photosensitive film pattern 22 on the metal interlayer insulating film 16 by a photolithography process using a via contact mask again, the second photosensitive film pattern 22 is formed. In the dry etching process using the etching mask, the selected portion of the second insulating layer 15 is etched to form the via contact hole 17 in which the lower metal wiring 12 is exposed.

상기에서, 비아 콘택홀(17)의 형상은 습식 식각 및 건식 식각 공정으로 형성된 모양과 비슷한 포지티브 경사를 이루며, 비아 콘택홀(17)의 측벽면은 제 2 절연막(15)만이 존재하게 되어 스핀 온 글라스막(14)이 노출되지 않는다.In the above, the shape of the via contact hole 17 has a positive slope similar to the shape formed by the wet etching and the dry etching process, and the sidewall surface of the via contact hole 17 has only the second insulating film 15 to spin on. The glass film 14 is not exposed.

도 2(d)를 참조하면, 제 2 감광막 패턴(22)을 산소 플라즈마를 이용하여 제거한 후, 비아 콘택홀(17)을 포함한 금속 층간 절연막(16)상에 금속층 증착 및 패터닝 공정으로 상부 금속 배선(18)이 형성된다.Referring to FIG. 2 (d), after the second photoresist layer pattern 22 is removed using an oxygen plasma, the upper metal interconnection is formed by depositing and patterning a metal layer on the metal interlayer insulating layer 16 including the via contact hole 17. 18 is formed.

상기에서, 상부 금속 배선(18)을 형성하기 위한 금속층 증착 공정은 저온 증착 방식 및/또는 고온 증착 방식을 적용한다.In the above, the metal layer deposition process for forming the upper metal wiring 18 applies a low temperature deposition method and / or a high temperature deposition method.

상기한 본 발명에 의해 형성된 비아 콘택홀(17)은 측벽면에 스핀 온 글라스막(14)이 노출되지 않기 때문에 산소 플라즈마에 의한 굴곡 현상이 발생되지 않고, 또한 포지티브 경사를 갖기 때문에 상부 금속 배선(18)을 형성하기 위한 금속층 증착시 금속 스텝 커버리지가 우수하여 비아 콘택홀(17) 부분에서 상부 금속 배선 (18)의 단선 또는 가늘어지는 현상이 방지된다.The via contact hole 17 formed according to the present invention does not expose the spin-on glass film 14 on the sidewall surface, and therefore, no bending occurs due to the oxygen plasma, and also has a positive inclination. The metal step coverage during the deposition of the metal layer for forming 18) is excellent to prevent disconnection or tapering of the upper metal wiring 18 in the via contact hole 17.

상술한 바와 같이, 본 발명은 비아 콘택홀의 형상을 포지티브 경사를 갖게하므로 스텝 커버리지가 개선되어 후속 금속층 증착 공정을 용이하게 실시할 수 있게 하며, 비아 콘택홀의 측벽면에 스핀 온 글라스막이 노출되지 않아 스핀 온 글라스막에 함유된 수분 등의 오염원이 금속 배선으로 침투되는 것이 방지되고, 소자의 수율 및 신뢰성을 향상시킬 수 있다.As described above, the present invention has a positive inclination in the shape of the via contact hole, so that the step coverage is improved to facilitate the subsequent metal layer deposition process, and the spin-on glass film is not exposed on the sidewall surface of the via contact hole so that the spin The contamination source such as moisture contained in the on glass film can be prevented from penetrating into the metal wiring, and the yield and reliability of the device can be improved.

Claims (4)

반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 기판 상에 하부 금속 배선을 형성하고, 상기 하부 금속 배선을 포함한 전체 구조 상에 제 1 절연막 및 스핀 온 글라스막을 순차적으로 형성하는 단계;Forming a lower metal wiring on a substrate having a structure in which various elements for forming a semiconductor device are formed, and sequentially forming a first insulating film and a spin on glass film on the entire structure including the lower metal wiring; 제 1 감광막 패턴을 식각 마스크로 한 건식 식각 공정으로 상기 스핀 온 글라스막 및 상기 제 1 절연막을 순차적으로 식각하여 제 1 비아 콘택홀을 형성하는 단계;Forming a first via contact hole by sequentially etching the spin-on glass film and the first insulating film by a dry etching process using the first photoresist pattern as an etching mask; 상기 제 1 감광막 패턴을 산소 플라즈마로 제거하되, 산소 플라즈마의 노출시간을 증가시켜 상기 스핀 온 글라스막이 일부 식각되도록 하여 상기 제 1 비아 콘택홀의 크기보다 큰 제 2 비아 콘택홀을 형성하는 단계;Removing the first photoresist pattern with oxygen plasma, and increasing the exposure time of the oxygen plasma to partially etch the spin-on glass layer to form a second via contact hole larger than the size of the first via contact hole; 상기 제 2 비아 콘택홀을 포함한 전체 구조 상에 제 2 절연막을 형성하는 단계; 및Forming a second insulating film on the entire structure including the second via contact hole; And 제 2 감광막 패턴을 식각 마스크로 한 건식 식각 공정으로 상기 제 2 절연막을 식각한 후, 상기 제 2 감광막 패턴을 제거하여 비아 콘택홀을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 제조 방법.And etching the second insulating film by a dry etching process using the second photoresist pattern as an etch mask, and then removing the second photoresist pattern to form a via contact hole. . 제 1 항에 있어서,The method of claim 1, 상기 제 1 감광막 패턴 및 상기 제 2 감광막 패턴은 동일한 비아 콘택홀 마스크를 사용한 포토리소그라피 공정으로 형성되는 것을 특징으로 하는 반도체 소자의 제조 방법.The first photoresist pattern and the second photoresist pattern are formed by a photolithography process using the same via contact hole mask. 제 1 항에 있어서,The method of claim 1, 상기 제 1 감광막 패턴 제거시 산소 플라즈마의 노출 시간은 상기 스핀 온 글라스막 내의 유기 성분량에 따라 일반적인 노출 시간보다 50 내지 200초간 더 증가시키는 것을 특징으로 하는 반도체 소자의 제조 방법.The method of manufacturing a semiconductor device according to claim 1, wherein the exposure time of the oxygen plasma during the removal of the first photoresist layer pattern is increased for 50 to 200 seconds more than the normal exposure time according to the amount of organic components in the spin on glass layer. 제 1 항에 있어서,The method of claim 1, 상기 비아 콘택홀은 포지티브 경사를 갖는 것을 특징으로 하는 반도체 소자의 제조 방법.And the via contact hole has a positive inclination.
KR1019970081141A 1997-12-31 1997-12-31 Method of manufacturing a semiconductor device KR100290466B1 (en)

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JPH03276721A (en) * 1990-03-27 1991-12-06 Sanyo Electric Co Ltd Manufacture of semiconductor device
KR950021127A (en) * 1993-12-31 1995-07-26 김주용 Method for manufacturing contact hole of semiconductor device

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Publication number Priority date Publication date Assignee Title
JPH03276721A (en) * 1990-03-27 1991-12-06 Sanyo Electric Co Ltd Manufacture of semiconductor device
KR950021127A (en) * 1993-12-31 1995-07-26 김주용 Method for manufacturing contact hole of semiconductor device

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