KR100197538B1 - Forming method for metal wiring in semiconductor device - Google Patents
Forming method for metal wiring in semiconductor device Download PDFInfo
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- KR100197538B1 KR100197538B1 KR1019960024519A KR19960024519A KR100197538B1 KR 100197538 B1 KR100197538 B1 KR 100197538B1 KR 1019960024519 A KR1019960024519 A KR 1019960024519A KR 19960024519 A KR19960024519 A KR 19960024519A KR 100197538 B1 KR100197538 B1 KR 100197538B1
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- film
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- interlayer insulating
- insulating film
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 82
- 239000002184 metal Substances 0.000 title claims abstract description 82
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000011229 interlayer Substances 0.000 claims abstract description 34
- 239000010410 layer Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 5
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 1
- 230000007797 corrosion Effects 0.000 abstract description 5
- 238000005260 corrosion Methods 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 230000007547 defect Effects 0.000 abstract description 2
- 238000000206 photolithography Methods 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32138—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only pre- or post-treatments, e.g. anti-corrosion processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 평탄화막에 의한 결함 및 접촉 특성이 개선된 반도체 소자의 금속 배선 방법이 개시된다. 본 발명은 반도체 기판의 비아홀 예정 영역에 더미 패턴이 형성되고, 구조물 상부에 제1 금속막이 증착된다. 그런 다음 제1 금속막의 소정 부분인 식각되어 더미 패턴 상부 및 반도체 기판상의 소정 부분에 제1 금속 패턴이 형성된 다음, 전체 구조 상부에 제1층간절연막과, 평탄화막 및 제2층간절연막이 증착되고, 더미 패턴 상부의 제1금속 패턴 표면이 노출되고, 그외의 구조물 상부에는 미세한 두께의 제2층간 절연막이 존재하도록 제1층간절연막과, 평탄화막 및 제2층간 절연막이 식각된 후 제2금속 배선이 형성되어, 소자의 콘택 특성을 증대시키고, 금속 배선 공정시 평탄화막이 노츨되지 아니하여, 평탄화막에 의한 제2금속 배선의 부식이 방지된다, 또한, 비아홀을 형성하기 위한 마스크 형성 공정이 배제되어 공정의 단순화를 이룩할 수 있다.Disclosed is a metal wiring method of a semiconductor device in which defects and contact characteristics caused by a planarization film are improved. In the present invention, a dummy pattern is formed in a predetermined region of a via hole of a semiconductor substrate, and a first metal layer is deposited on the structure. Then, a predetermined portion of the first metal film is etched to form a first metal pattern on the dummy pattern and a predetermined portion on the semiconductor substrate, and then a first interlayer insulating film, a planarization film, and a second interlayer insulating film are deposited on the entire structure. The first interlayer insulating film, the planarization film, and the second interlayer insulating film are etched to expose the surface of the first metal pattern on the dummy pattern, and the second interlayer insulating film having a fine thickness is formed on the other structure. Formed to increase the contact characteristics of the device, and the planarization film is not exposed during the metal wiring process, thereby preventing corrosion of the second metal wiring by the planarization film, and eliminating the mask formation process for forming the via hole. Can be simplified.
Description
제1도는 종래의 반도체 소자의 금속 배선 형성방법에 따라 형성된 반도체 소자의 단면도.1 is a cross-sectional view of a semiconductor device formed in accordance with a metal wiring formation method of a conventional semiconductor device.
제2a도 내지 제2i도는 본 발명의 반도체 소자의 금속 배선 형성 방법을 공정 순서적으로 설명하기 위한 단면도.2A to 2I are cross-sectional views for explaining the process steps of a metal wiring forming method of a semiconductor device of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 반도체 기판 11 : 더미 패션10: semiconductor substrate 11: dummy fashion
12 : 제1금속막 12a : 제1금속 패턴12: first metal film 12a: first metal pattern
13 : 포토레지스트막 13a : 제2의 포토레지스트 패턴13 photoresist film 13a second photoresist pattern
14 : 난반사 방지막 또는 불투명층 15 : 포토레지스트 패턴14 anti-reflective coating or opaque layer 15 photoresist pattern
16 : 제1층간 절연막 17 : 평탄화막16: first interlayer insulating film 17: planarization film
18 : 제2층간 절연막 19 : 제2금속 배선막18: second interlayer insulating film 19: second metal wiring film
[발명의 기술분야]Technical Field of the Invention
본 발명은 반도체 소자의 금속 배선 형성방법에 관한 것으로, 특히, 상, 하층 금속 배선간의 접속 특성을 개선할 수 있는 반도체 소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming metal wirings in semiconductor devices capable of improving connection characteristics between upper and lower metal wirings.
[발명이 속하는 기술분야 및 그 분야의 종래 기술]TECHNICAL FIELD OF THE INVENTION
반도체 기술의 진보와 더불어 더 나아가서는 반도체 소자의 고속화, 고집적화가 진행되고 있어, 이에 수반해서 패턴에 대한 미세화의 필요성이 점점 높아지고 있으며, 또한 패턴의 칫수도 고정밀화가 요구되고 있다.In addition to the advances in semiconductor technology, the speed and integration of semiconductor devices have been increased, and the necessity of miniaturization of patterns is increasing, and the size of patterns is also required to be highly accurate.
일반적으로 반도체 소자의 금속 배선 방법은, 반도체 기판 및 또는 제1금속 배선상부에 절연막이 형성되고, 이 절연막의 소정 부분이 식각되어, 콘택홀이 형성된다. 그리고, 이 콘택홀 내부에 반도체 기판 또는 제1금속 배선과 접촉되도록 또 다른 금속 배선이 증착되어, 소정의 부분 패터닝되어, 금속 배선이 형성된다.Generally, in the metal wiring method of a semiconductor element, an insulating film is formed on a semiconductor substrate and or a 1st metal wiring, and predetermined part of this insulating film is etched and a contact hole is formed. Further, another metal wiring is deposited inside the contact hole so as to be in contact with the semiconductor substrate or the first metal wiring, and predetermined patterning is performed to form a metal wiring.
이에 대하여 보다 구체적으로 설명하면, 제1도에 도시된 바와 같이, 예를들어, 제1금속 배선막(2)이 형성된 반도체 기판(1) 상부에, 제1층간 절연막(3)과, 하부의 굴곡을 평탄하게 하기 위한 평탄화 절연막(4) 예를들면, SOG(spin on glass) 및 평탄화 절연막(4)과 이후에 형성되어질 금속 배선과의 접촉 불량을 방지하기 위한 제2층간 절연막(5)가 순차적으로 형성된다. 그런 다음, 제1금속 배선(2)의 조성 부분이 노출되도록 제2층간 절연막(5), 평탄화 절연막(4) 및 제층간 절연막(3)이 식각되어, 비아홀이 형성된다. 이어서, 반도체 기판의 전체적구조물 표면에, 수퍼터링 방식에 의하여, 제2금속 배선막(6)이 형성되어, 다층금속 배선이 형성된 반도체 소자가 형성된다.More specifically, as shown in FIG. 1, for example, the first interlayer insulating film 3 and the lower portion of the semiconductor substrate 1 on which the first metal wiring film 2 is formed are formed. For example, the planarization insulating film 4 for flattening the curvature, for example, a second interlayer insulating film 5 for preventing contact failure between the spin on glass (SOG) and the planarization insulating film 4 and the metal wiring to be formed later Are formed sequentially. Then, the second interlayer insulating film 5, the planarization insulating film 4, and the interlayer insulating film 3 are etched so that the compositional portion of the first metal wiring 2 is exposed to form a via hole. Subsequently, the second metal wiring film 6 is formed on the surface of the entire structure of the semiconductor substrate by a superuttering method to form a semiconductor element having a multi-layer metal wiring formed thereon.
[발명이 이루고자 하는 기술적 과제][Technical problem to be achieved]
그러나, 상기와 같은 종래의 방법에 따르면, 제2금속 배선 공정시, 제2금속 배선과, 비아홀내의 평판화 절연막인 SOG막이 접촉되어, SOG막으로부터, 수분들이 외방 확산되어, 금속 부식이 발생되는 문제점이 존재하였다.However, according to the conventional method as described above, during the second metal wiring process, the second metal wiring contacts the SOG film, which is a flattening insulating film in the via hole, and moisture is diffused outward from the SOG film, causing metal corrosion. There was a problem.
더구나 종래의 방법은 미세한 비아홀내에 스퍼터링 방식에 의하여 고르게 증착된다고 하더라도, 비아홀 내부에는 제2금속 배선이 제대로 증착되지 않음으로 인하여, 하부의 제1금속 배선과 접촉 불량 및 전기적 단선을 유발시키게 되는 문제점 또한 상존하고 있었다.In addition, even if the conventional method is evenly deposited by the sputtering method in the fine via hole, since the second metal wiring is not properly deposited inside the via hole, the problem of causing contact failure and electrical disconnection with the lower first metal wiring is also caused. It was always there.
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로, 다층 금속 배선시, 평탄화 절연막과의 접촉을 배제하여, 금속 배선의 부식을 방지할 수 있는 반도체 소자의 금속 배선 형성방법을 제공하는 것을 목적으로 한다.Accordingly, the present invention has been made to solve the above-described problems, and to provide a method for forming a metal wiring of a semiconductor device capable of preventing corrosion of the metal wiring by excluding contact with the planarization insulating film during multilayer metal wiring. The purpose.
또한, 본 발명의 다른 목적은, 제2금속 배선막과 하부의 제1금속 배선막의 접촉을 용이하게 하여 소자의 접촉 특성 및 전기적 단선을 방지할 수 있는 반도체 소자의 금속 배선 형성방법을 제공하는 것이다.Further, another object of the present invention is to provide a method for forming a metal wiring of a semiconductor device which can facilitate contact between the second metal wiring film and the lower first metal wiring film to prevent contact characteristics and electrical disconnection of the device. .
더불어, 반도체 소자의 금속 배선 공정시, 포토리소 그라피 공정을 줄여, 단순화된 반도체 조사의 금속 배선 형성방법을 제공하는 것을 목적으로 한다.In addition, an object of the present invention is to reduce the photolithography process in the metal wiring process of a semiconductor device, and to provide a method of forming a metal wiring of a simplified semiconductor irradiation.
[발명의 구성 및 작용][Configuration and Function of Invention]
상기한 본 발명의 목적으로 달성하기 위하여, 본 발명은, 트랜지스터 및 절연막이 형성된 반도체 기판을 제공하는 단계; 반도체 기판의 비아홀 예정 영역에 더미 패턴을 형성하는 단계; 반도체 기판의 결과물 상부에 제1금속막을 증착하는 단계; 제1금속막의 소정 부분을 식각하여 더미 패턴 상부 및 반도체 기판상의 소성 부분에 제1금속 패턴을 형성하는 단계; 전체 구조 상부에 제1층간 절연막과, 평탄화막 및 제2층간 절연막을 증착하는 단계; 더미 패턴 상부의 제1금속 패턴 표면은 노출되고, 그외의 구조물 상부에는 미세한 두께의 제2층간 절연막이 존재하도록 제1층간 절연막과, 평탄화막 및 제2층간 절연막을 식각하는 단계; 및 반도체 기판의 결과물 상부에 제2금속 배선을 형성하는 단계를 포함한다.In order to achieve the above object of the present invention, the present invention provides a semiconductor substrate comprising a transistor and an insulating film formed; Forming a dummy pattern on a predetermined region of the via hole of the semiconductor substrate; Depositing a first metal film on the resultant of the semiconductor substrate; Etching a predetermined portion of the first metal film to form a first metal pattern on the dummy pattern and on the baked portion on the semiconductor substrate; Depositing a first interlayer insulating film, a planarization film, and a second interlayer insulating film over the entire structure; Etching the first interlayer insulating film, the planarization film, and the second interlayer insulating film so that the surface of the first metal pattern on the dummy pattern is exposed, and the second interlayer insulating film having a fine thickness exists on the other structure; And forming a second metal wire on the resultant of the semiconductor substrate.
따라서, 본 발명에 따르면, 제2금속 배선과 평탄화막과의 접속을 배제하여, 금속막의 부식이 감소되고, 제1금속 배선과 제2금속 배선간의 접촉 특성이 개성되어 반도체 소자의 금속 배선 신뢰성이 형성된다.Therefore, according to the present invention, by eliminating the connection between the second metal wiring and the flattening film, the corrosion of the metal film is reduced, the contact characteristics between the first metal wiring and the second metal wiring are improved, and the metal wiring reliability of the semiconductor element is improved. Is formed.
[실시예]EXAMPLE
이하, 첨부된 도면에 의거하여, 본 발명의 바람직한 실시예를 자세히 설명하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도면 제2a도 내지 제21도는 본 발명의 반도체 소자의 금속 배선 형성방법을 공정 순서적으로 설명하기 위한 단면도이다.2A to 21 are cross-sectional views for explaining a method of forming metal wirings of a semiconductor device according to the present invention in order of process.
먼저, 제2a도에 도시된 바와 같이, 트랜지스터(도시되지 않음) 및 트랜지스터와 이후의 금속 배선을 절연시키기 위한 절연막(도시되지 않음)이 형성된 반도체 기판에 더미패턴(11)이 형성되는데, 이 더미 패턴(11)은 이후에 제1금속 배선과 제2금속 배선과 접촉이 될 비아홀 예정 영역에 형성됨이 바람직하다. 이어서, 전체 구조믈 상부에 알루미늄을 주성분으로 하는 제1금속막(12)이 예정된 두께로 형성되고, 포토레지스트막(13)이 코팅된 후, 포토레지스트막을 고형화하기 위하여 하드 베이킹 공정이 진행된다. 이때, 포토레지스트(12)은, 공지된 바와 같이 액상의 형태로, 이후의 제1금속막을 페터닝하기 위한 포토리소그라피 공정시 하부단차로 인한 오정렬을 최소화하기 위하여 도포된다.First, as shown in FIG. 2A, a dummy pattern 11 is formed on a semiconductor substrate on which a transistor (not shown) and an insulating film (not shown) for insulating the transistor and subsequent metal wirings are formed. The pattern 11 is preferably formed in the via hole predetermined region to be in contact with the first metal wiring and the second metal wiring. Subsequently, the first metal film 12 containing aluminum as a main component is formed on the entire structure to a predetermined thickness, and after the photoresist film 13 is coated, a hard baking process is performed to solidify the photoresist film. At this time, the photoresist 12 is applied in the form of a liquid, so as to minimize misalignment due to the lower step in the subsequent photolithography process for patterning the first metal film.
그런다음, 제2b도에 도시된 바와 같이 포토레지스트막(13) 상부에 난 반사 방지막으로 불투명층(14)이 증착된 다음, 제2c도에 도시된 바와 같이, 불투명층(14) 상부의 소정 영역에 제1금속막(12)을 패터닝하기 위한 포토레지스트 패턴(15)이 공지의 포토리고그라피 공정에 의하여 형성된다. 이때, 불투명한 층(14)은 포토리소그라피 공정시, DOF(depth of focus) 문제점들을 최소화하기 위하여 형성된다.Then, as shown in FIG. 2B, an opaque layer 14 is deposited on the photoresist film 13 with an anti-reflective film, and then, as shown in FIG. 2C, a predetermined upper portion of the opaque layer 14 is shown. A photoresist pattern 15 for patterning the first metal film 12 in the region is formed by a known photolithography process. At this time, the opaque layer 14 is formed in order to minimize depth of focus (DOF) problems in the photolithography process.
그 후에, 포토레지스트 패턴(15)에 의하여, 불투명층(14)이 제2d도에서와 같이 패터닝되고, 포토레지스트 패턴(15)은 공지된 방법에 의하여 제거된다.Thereafter, with the photoresist pattern 15, the opaque layer 14 is patterned as in FIG. 2d, and the photoresist pattern 15 is removed by a known method.
그 다음에, 패터닝 불투명층(14)을 마스크로 하여, 노출된 포토레지스트막(13)은 노광 및 현성되어, 제2의 포토레지스트 패턴(13a)이 형성된다.Then, using the patterned opaque layer 14 as a mask, the exposed photoresist film 13 is exposed and developed to form a second photoresist pattern 13a.
제2f도는 제1금속막(12)이 패터닝되어, 제1금속 패턴(12a)이 형성된 도면으로, 제2의 포토레지스트 패턴(13a)에 의하여 하부의 제1금속막이 이방성 식각되므로써, 제1금속 패턴(12a)이 형성된다.FIG. 2F is a view in which the first metal film 12 is patterned and the first metal pattern 12a is formed. The first metal film below is anisotropically etched by the second photoresist pattern 13a to form the first metal. The pattern 12a is formed.
제2g도에 도시된 바와 같이, 제1층간 절연막(16)과 평탄화 절연막(17) 바람직하게 SOG막 및 제2층간 절연막(18)이 순차적으로 반도체 기판의 구조물 표면에 형성된다. 이때, 제2층간 절연막(17)으로는 평탄화 절연막인 SOG 막과 선택비가 큰 오존 PSG막으로 형성되고, SOG막은 도포된 다음 소정 온도에서 큐오링(curing) 공정이 실시된다.As shown in FIG. 2G, the first interlayer insulating film 16 and the planarization insulating film 17, preferably the SOG film and the second interlayer insulating film 18, are sequentially formed on the surface of the structure of the semiconductor substrate. At this time, the second interlayer insulating film 17 is formed of an SOG film which is a planarization insulating film and an ozone PSG film having a high selectivity, and the SOG film is coated and then cured at a predetermined temperature.
그리고 나서, 습식 시각 방식에 의한 블랭킷 식각으로, 더미 패턴 상부에 있는 제1금속 패턴(12a)의 최상단이 노출되고, 나머지 구조물 상부에는 미세한 두께의 제2층간 절연막(17)이 존재하도록 제2층간 절연막(17), 평탄화 절연막(16) 및 제1층간 절연막(15)이 식각된다. 그러면, 제2h도에 도시된 바와 같이, 더미 패턴 상부에 존재하는 제1금속 패턴(12a)의 상부 및 양측부의 일부분이 노출되고, 평탄화막(15) 및 제1층간 절연막(15)의 상부에는 미세한 두께의 제2층간 절연막이 존재하게 된다. 이때, 구조물 전면에 미세한 두께의 제2층간 절연막이 존해하게 되는 것은, 더미 패턴으로 인한 단차에 의하여 제2층간 절연막의 부위별 식각 속도가 달아지고, 또한 평탄화 절연막에 비하여 식각 선택비가 크기 때문이다.Then, by wet etching, the second layer may be exposed such that the top end of the first metal pattern 12a on the dummy pattern is exposed and the second interlayer insulating layer 17 having a fine thickness is present on the remaining structure. The insulating film 17, the planarization insulating film 16, and the first interlayer insulating film 15 are etched. Then, as shown in FIG. 2h, portions of the upper portion and both sides of the first metal pattern 12a existing on the dummy pattern are exposed, and the upper portion of the planarization layer 15 and the first interlayer insulating layer 15 is exposed. A second interlayer insulating film of minute thickness is present. In this case, the second interlayer insulating film having a small thickness exists on the entire surface of the structure because the etching rate for each part of the second interlayer insulating film is increased by the step due to the dummy pattern, and the etching selectivity is larger than that of the planarizing insulating film.
그후에, 제2f도에 도시된 바와 같이, 알루미늄 금속을 주성분으로 하는 제2금속막(18)이 형성된다. 이에 따라, 평탄화막과 금속 배선막은 직접 접촉하지 않게 되고, 제2금속막과 제1금속 패턴과도 콘택 결함없이 접촉하게 된다.Thereafter, as shown in FIG. 2F, a second metal film 18 mainly composed of aluminum metal is formed. Accordingly, the planarization film and the metal wiring film do not directly contact each other, and the second metal film and the first metal pattern also come into contact without contact defects.
[발명의 효과][Effects of the Invention]
이상에서 자세히 설명한 바와 같이, 본 발명은, 비아홀 형성공정 없이, 제1금속 배선 상부에 제2금속 배선을 효과적으로 형성함으로써, 소자의 콘택 특성을 증대시키고, 금속 배선 공정시 평탄화막이 노출되지 아니하여, 평탄화막에 의한 제2금속 배선의 부식이 방지된다. 또한, 비아홀을 형성하기 위한 마스크 형성 공정이 배제되어, 공정의 단순화를 이룩할 수 있다. 이로써, 반도체 소자의 금속 배선의 신뢰성이 증대된다.As described in detail above, in the present invention, by effectively forming the second metal wiring on the first metal wiring without the via hole forming process, the contact characteristics of the device are increased, and the planarization film is not exposed during the metal wiring process. Corrosion of the second metal wiring by the planarization film is prevented. In addition, the mask forming process for forming the via hole is excluded, thereby simplifying the process. Thereby, the reliability of the metal wiring of a semiconductor element increases.
Claims (6)
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| KR1019960024519A KR100197538B1 (en) | 1996-06-27 | 1996-06-27 | Forming method for metal wiring in semiconductor device |
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| KR1019960024519A KR100197538B1 (en) | 1996-06-27 | 1996-06-27 | Forming method for metal wiring in semiconductor device |
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| KR100499396B1 (en) * | 2002-10-31 | 2005-07-05 | 매그나칩 반도체 유한회사 | Method for manufacturing semiconductor device |
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