KR100499399B1 - Manufacturing Method of Stacked Via Contact - Google Patents

Manufacturing Method of Stacked Via Contact Download PDF

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Publication number
KR100499399B1
KR100499399B1 KR10-1998-0041596A KR19980041596A KR100499399B1 KR 100499399 B1 KR100499399 B1 KR 100499399B1 KR 19980041596 A KR19980041596 A KR 19980041596A KR 100499399 B1 KR100499399 B1 KR 100499399B1
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South Korea
Prior art keywords
metal layer
layer
forming
insulating film
photoresist pattern
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KR10-1998-0041596A
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Korean (ko)
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KR20000024844A (en
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김진형
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주식회사 하이닉스반도체
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Priority to KR10-1998-0041596A priority Critical patent/KR100499399B1/en
Publication of KR20000024844A publication Critical patent/KR20000024844A/en
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Publication of KR100499399B1 publication Critical patent/KR100499399B1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/7685Barrier, adhesion or liner layers the layer covering a conductive structure

Abstract

본 발명은 스택형 비아콘택의 제조방법에 관한 것으로, 종래에는 제1,제2콘택홀의 형성을 위해 2회의 사진식각공정이 요구됨에 따라 제1,제2콘택홀의 정렬정밀도를 고려한 세부공정이 복잡한 문제점이 있었다. 따라서, 본 발명은 하부배선의 상부에 제1층간절연막을 형성한 후, 사진식각공정을 통해 일부를 식각하여 제1콘택홀을 형성하는 공정과; 상기 제1콘택홀이 형성된 제1층간절연막의 상부에 제1금속층을 형성하는 공정과; 상기 제1금속층의 상부에 감광막을 도포한 후, 노광 및 현상을 실시하여 감광막 패턴을 형성하고, 그 감광막 패턴을 적용하여 제1금속층을 패터닝하는 공정과; 상기 감광막 패턴이 형성된 구조물의 상부 전면에 에스오지 절연막을 도포하는 공정과; 상기 에스오지 절연막이 도포된 구조물을 고압 스크러빙 처리하여 상기 감광막 패턴 상부의 에스오지 절연막 및 감광막 패턴을 제거함으로써, 상기 제1금속층을 노출시키는 공정과; 상기 노출된 제1금속층 및 잔류하는 에스오지 절연막의 상부에 제2금속층을 형성하여 패터닝하는 공정으로 이루어지는 스택형 비아콘택의 제조방법을 제공하여 제1콘택홀의 형성을 위한 1회의 사진식각공정만을 사용하고, 그에 따라 제1금속층과 제2금속층의 정렬마진을 확보하여 공정이 단순화됨과 아울러 신뢰성이 향상되는 효과가 있다. The present invention relates to a method for manufacturing a stacked via contact. In the related art, since two photolithography processes are required to form the first and second contact holes, detailed processes considering the alignment accuracy of the first and second contact holes are complicated. There was a problem. Accordingly, the present invention comprises the steps of forming a first contact hole by forming a first interlayer insulating film on the lower wiring, and then etching a portion through a photolithography process; Forming a first metal layer on top of the first interlayer insulating film on which the first contact hole is formed; Applying a photoresist film on top of the first metal layer, performing exposure and development to form a photoresist pattern, and applying the photoresist pattern to pattern the first metal layer; Applying an sedge insulating film to the entire upper surface of the structure on which the photoresist pattern is formed; Exposing the first metal layer by high pressure scrubbing of the structure coated with the Suji insulating layer to remove the Suji insulating layer and the photosensitive layer pattern on the photoresist pattern; Provided is a method of manufacturing a stacked via contact which comprises a step of forming and patterning a second metal layer on top of the exposed first metal layer and the remaining SOH insulating film to use only one photolithography process for forming the first contact hole. As a result, the alignment margin between the first metal layer and the second metal layer is secured, thereby simplifying the process and improving reliability.

Description

스택형 비아콘택의 제조방법Manufacturing Method of Stacked Via Contact

본 발명은 스택형 비아콘택(stacked via contact)의 제조방법에 관한 것으로, 특히 접착력이 약한 감광막이 고압 스크러빙(high pressure scrubbing) 처리를 통해 선택적으로 제거되는 것을 이용하여 제조공정을 단순화 한 스택형 비아콘택의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a stacked via contact. In particular, the stacked via simplifies the manufacturing process by selectively removing the photosensitive film having a weak adhesive strength through high pressure scrubbing. It relates to a method for manufacturing a contact.

일반적으로, 적층형 비아콘택이란 다층배선의 반도체 제조시에 절연층에 형성되어 상부 및 하부배선들을 접속시키는 비아콘택의 상부에 다시 비아콘택을 형성하는 기술을 말하는 것으로, 이와같은 종래 스택형 비아콘택의 제조방법을 도1a 내지 도1e의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.In general, the stacked via contact refers to a technology of forming a via contact again on top of a via contact that is formed in an insulating layer during semiconductor manufacturing of a multilayer wiring and connects upper and lower wirings. The manufacturing method is described in detail with reference to the procedure cross-sectional view of FIGS. 1A to 1E as follows.

먼저, 도1a에 도시한 바와같이 하부배선(미도시)의 상부에 제1층간절연막(inter metal dielectric : IMD, 1)을 형성한 후, 사진식각공정을 통해 일부를 식각하여 제1콘택홀을 형성한다.First, as shown in FIG. 1A, a first interlayer dielectric (IMD) 1 is formed on a lower wiring (not shown), and then a portion of the first contact hole is etched through a photolithography process. Form.

그리고, 도1b에 도시한 바와같이 상기 제1콘택홀이 형성된 제1층간절연막(1)의 상부에 제1금속층(2)을 형성하여 패터닝한다. 이때, 상기 제1콘택홀이 제1금속층(2)으로 채워져서 제1비아콘택(A)이 된다.As shown in FIG. 1B, the first metal layer 2 is formed and patterned on the first interlayer insulating film 1 having the first contact hole. In this case, the first contact hole is filled with the first metal layer 2 to become the first via contact A. FIG.

그리고, 도1c에 도시한 바와같이 상기 패터닝된 제1금속층(2) 및 제1층간절연막(1)의 상부에 제2층간절연막(3)을 형성한다. As shown in FIG. 1C, a second interlayer insulating film 3 is formed on the patterned first metal layer 2 and the first interlayer insulating film 1.

그리고, 도1d에 도시한 바와같이 사진식각공정을 통해 상기 제2층간절연막(3)의 일부를 식각하여 제2콘택홀을 형성한다.As shown in FIG. 1D, a part of the second interlayer insulating film 3 is etched through a photolithography process to form a second contact hole.

그리고, 도1e에 도시한 바와같이 상기 제2콘택홀이 형성된 제2층간절연막(3)의 상부에 제2금속층(4)을 형성하여 패터닝한다. 이때, 상기 제2콘택홀이 제2금속층(4)으로 채워져서 제2비아콘택(B)이 된다.As shown in FIG. 1E, the second metal layer 4 is formed and patterned on the second interlayer insulating film 3 on which the second contact hole is formed. At this time, the second contact hole is filled with the second metal layer 4 to become the second via contact B.

그러나, 상기한 바와같은 종래 스택형 비아콘택의 제조방법은 제1,제2콘택홀의 형성을 위해 2회의 사진식각공정이 요구됨에 따라 제1,제2콘택홀의 정렬정밀도를 고려한 세부공정이 복잡한 문제점이 있었다.However, the conventional method for manufacturing a stacked via contact as described above requires two photolithography processes to form the first and second contact holes, and thus, the detailed process considering the alignment accuracy of the first and second contact holes is complicated. There was this.

본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 접착력이 약한 감광막이 고압 스크러빙 처리를 통해 선택적으로 제거되는 것을 이용하여 사진식각공정을 1회로 단순화할 수 있는 스택형 비아콘택의 제조방법을 제공하는데 있다.The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to simplify the photolithography process by using a photosensitive film having a weak adhesive force selectively removed through a high pressure scrubbing process. The present invention provides a method for manufacturing a stacked via contact.

상기한 바와같은 본 발명의 목적을 달성하기 위한 스택형 비아콘택 제조방법의 바람직한 일 실시예는 하부배선의 상부에 제1층간절연막을 형성한 후, 사진식각공정을 통해 일부를 식각하여 제1콘택홀을 형성하는 공정과; 상기 제1콘택홀이 형성된 제1층간절연막의 상부에 제1금속층을 형성하는 공정과; 상기 제1금속층의 상부에 감광막을 도포한 후, 노광 및 현상을 실시하여 감광막 패턴을 형성하고, 그 감광막 패턴을 적용하여 제1금속층을 패터닝하는 공정과; 상기 감광막 패턴이 형성된 구조물의 상부 전면에 에스오지(spin on glass : SOG) 절연막을 도포하는 공정과; 상기 에스오지 절연막이 도포된 구조물을 고압 스크러빙 처리하여 상기 감광막 패턴 상부의 에스오지 절연막 및 감광막 패턴을 제거함으로써, 상기 제1금속층을 노출시키는 공정과; 상기 노출된 제1금속층 및 잔류하는 에스오지 절연막의 상부에 제2금속층을 형성하여 패터닝하는 공정을 구비하여 이루어짐을 특징으로 한다.One preferred embodiment of the stacked via contact manufacturing method for achieving the object of the present invention as described above is to form a first interlayer insulating film on the upper portion of the lower wiring, and then etching a portion through a photolithography process to the first contact Forming a hole; Forming a first metal layer on top of the first interlayer insulating film on which the first contact hole is formed; Applying a photoresist film on top of the first metal layer, performing exposure and development to form a photoresist pattern, and applying the photoresist pattern to pattern the first metal layer; Applying a spin on glass (SOG) insulating film to the entire upper surface of the structure on which the photoresist pattern is formed; Exposing the first metal layer by high pressure scrubbing of the structure coated with the Suji insulating layer to remove the Suji insulating layer and the photosensitive layer pattern on the photoresist pattern; And forming and patterning a second metal layer on the exposed first metal layer and the remaining SOH insulating layer.

상기한 바와같은 본 발명의 일 실시예에 따른 스택형 비아콘택의 제조방법을 도2a 내지 도2g의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A method of manufacturing a stacked via contact according to an embodiment of the present invention as described above will be described in detail with reference to the procedure cross-sectional view of FIGS. 2A to 2G.

먼저, 도2a에 도시한 바와같이 하부배선(미도시)의 상부에 제1층간절연막(11)을 형성한 후, 사진식각공정을 통해 일부를 식각하여 제1콘택홀을 형성한다.First, as shown in FIG. 2A, the first interlayer insulating layer 11 is formed on the lower wiring (not shown), and then a portion of the first interlayer insulating layer 11 is etched to form a first contact hole.

그리고, 도2b에 도시한 바와같이 상기 제1콘택홀이 형성된 제1층간절연막(11)의 상부에 제1금속층(12) 및 Ti층(13)을 형성한다. 이때, Ti층(13)은 제1금속층(12)과 이후에 형성되는 감광막 및 제2금속층(16)과의 접촉특성을 향상시키기 위하여 증착한다.As shown in FIG. 2B, the first metal layer 12 and the Ti layer 13 are formed on the first interlayer insulating film 11 having the first contact hole. At this time, the Ti layer 13 is deposited to improve contact characteristics between the first metal layer 12 and the photosensitive film and the second metal layer 16 formed thereafter.

그리고, 도2c에 도시한 바와같이 상기 Ti층(13)의 상부에 감광막을 도포한 후, 노광 및 현상을 실시하여 감광막 패턴(14)을 형성한다.Then, as shown in FIG. 2C, the photoresist film is coated on the Ti layer 13, and then exposed and developed to form the photoresist pattern 14.

그리고, 도2d에 도시한 바와같이 상기 감광막 패턴(14)을 적용하여 Ti층(13) 및 제1금속층(12)을 패터닝한다.2D, the Ti layer 13 and the first metal layer 12 are patterned by applying the photosensitive film pattern 14.

그리고, 도2e에 도시한 바와같이 상기 감광막 패턴(14)이 형성된 구조물의 상부 전면에 에스오지 절연막(15)을 도포한다.As shown in FIG. 2E, the SOH insulating layer 15 is coated on the entire upper surface of the structure on which the photoresist pattern 14 is formed.

그리고, 도2f에 도시한 바와같이 상기 에스오지 절연막(15)이 도포된 구조물을 고압 스크러빙 처리하여 감광막 패턴(14) 상부의 에스오지 절연막(15) 및 감광막 패턴(14)을 제거함으로써, 상기 Ti층(13)을 노출시킨다. 이때, 상기 고압 스크러빙 처리란 고압에서 웨이퍼의 표면에 초순수(DI water)를 분사하는 것으로, 이 고압 스크러빙 처리에 의해 접착력이 약한 감광막 패턴(14)을 제거된다.As shown in FIG. 2F, the structure on which the Suji insulating layer 15 is applied is subjected to high pressure scrubbing to remove the Suji insulating layer 15 and the photosensitive layer pattern 14 on the photoresist pattern 14, thereby removing the Ti. Expose layer 13. At this time, the high pressure scrubbing treatment is to spray ultra pure water (DI water) on the surface of the wafer at a high pressure, and the high pressure scrubbing treatment removes the photosensitive film pattern 14 having low adhesive strength.

그리고, 도2g에 도시한 바와같이 상기 노출된 Ti층(13) 및 잔류하는 에스오지 절연막(15)의 상부에 제2금속층(16)을 형성하여 패터닝한다.As shown in FIG. 2G, the second metal layer 16 is formed and patterned on the exposed Ti layer 13 and the remaining SOH insulating layer 15.

상기한 바와같은 본 발명에 의한 스택형 비아콘택의 제조방법은 제1콘택홀의 형성을 위해 1회의 사진식각공정이 요구되며, 제1금속층과 제2금속층의 정렬마진을 확보하여 공정이 단순화됨과 아울러 신뢰성이 향상되는 효과가 있다. As described above, the method for manufacturing a stacked via contact according to the present invention requires one photolithography process to form the first contact hole, and the process is simplified by securing an alignment margin of the first metal layer and the second metal layer. The reliability is improved.

도1은 종래 스택형 비아콘택의 제조방법을 보인 수순단면도.1 is a cross-sectional view showing a method of manufacturing a conventional stacked via contact.

도2는 본 발명의 일 실시예를 보인 수순단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.

***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***

11:제1층간절연막 12,16:제1,제2금속층11: first interlayer insulating film 12, 16: first and second metal layers

13:Ti층 14:감광막 패턴13: Ti layer 14: photosensitive film pattern

15:에스오지 절연막15: Sōji insulating film

Claims (2)

하부배선의 상부에 제1층간절연막을 형성한 후, 사진식각공정을 통해 일부를 식각하여 제1콘택홀을 형성하는 공정과; 상기 제1콘택홀이 형성된 제1층간절연막의 상부에 제1금속층을 형성하는 공정과; 상기 제1금속층의 상부에 감광막을 도포한 후, 노광 및 현상을 실시하여 감광막 패턴을 형성하고, 그 감광막 패턴을 적용하여 제1금속층을 패터닝하는 공정과; 상기 감광막 패턴이 형성된 구조물의 상부 전면에 에스오지 절연막을 도포하는 공정과; 상기 에스오지 절연막이 도포된 구조물을 고압 스크러빙 처리하여 상기 감광막 패턴 상부의 에스오지 절연막 및 감광막 패턴을 제거함으로써, 상기 제1금속층을 노출시키는 공정과; 상기 노출된 제1금속층 및 잔류하는 에스오지 절연막의 상부에 제2금속층을 형성하여 패터닝하는 공정을 구비하여 이루어지는 것을 특징으로 하는 스택형 비아콘택의 제조방법.Forming a first contact hole by forming a first interlayer insulating layer on the lower wiring and then etching a part through a photolithography process; Forming a first metal layer on top of the first interlayer insulating film on which the first contact hole is formed; Applying a photoresist film on top of the first metal layer, performing exposure and development to form a photoresist pattern, and applying the photoresist pattern to pattern the first metal layer; Applying an sedge insulating film to the entire upper surface of the structure on which the photoresist pattern is formed; Exposing the first metal layer by high pressure scrubbing of the structure coated with the Suji insulating layer to remove the Suji insulating layer and the photosensitive layer pattern on the photoresist pattern; And forming and patterning a second metal layer on the exposed first metal layer and the remaining SOH insulating layer. 제 1항에 있어서, 상기 제1콘택홀이 형성된 제1층간절연막의 상부에 제1금속층을 형성하는 공정은 그 제1금속층의 상부에 Ti층을 형성하는 공정을 더 포함하여 이루어지는 것을 특징으로 하는 스택형 비아콘택의 제조방법.The method of claim 1, wherein the forming of the first metal layer on the first interlayer insulating film having the first contact hole further comprises forming a Ti layer on the first metal layer. Method of manufacturing a stacked via contact.
KR10-1998-0041596A 1998-10-02 1998-10-02 Manufacturing Method of Stacked Via Contact KR100499399B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101013548B1 (en) * 2007-11-30 2011-02-14 주식회사 하이닉스반도체 Staack package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101013548B1 (en) * 2007-11-30 2011-02-14 주식회사 하이닉스반도체 Staack package

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