KR960008559B1 - Fine contact hall forming method of semiconductor device - Google Patents
Fine contact hall forming method of semiconductor device Download PDFInfo
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- KR960008559B1 KR960008559B1 KR1019930010487A KR930010487A KR960008559B1 KR 960008559 B1 KR960008559 B1 KR 960008559B1 KR 1019930010487 A KR1019930010487 A KR 1019930010487A KR 930010487 A KR930010487 A KR 930010487A KR 960008559 B1 KR960008559 B1 KR 960008559B1
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- Prior art keywords
- contact hole
- forming
- semiconductor device
- film
- photosensitive film
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims description 7
- 239000010408 film Substances 0.000 description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
제1도 및 제2도는 종래의 기술에 의해 콘택홀이 형성된 상태를 도시한 단면도.1 and 2 are cross-sectional views showing a state in which a contact hole is formed by a conventional technology.
제3a도 내지 제3d도는 본 발명에 의한 콘택홀 형성단계를 나타낸 단면도.3a to 3d are cross-sectional views showing a step of forming a contact hole according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1 : 실리콘 웨이펴 2,14 :감광막1: silicon wafer 2,14: photosensitive film
3,15 : 콘택홀 10 : 콘택기판3,15: contact hole 10: contact substrate
11 : 절연막 12: 제1금속배선11 insulating film 12 first metal wiring
13 : 제2금속배선 16,16a: 제1감광막13: second metal wiring 16, 16a: first photosensitive film
17,17a : 제1콘택홀 18 : 제2 감광막17,17a: first contact hole 18: second photosensitive film
19 : 제2콘택홀19: 2nd contact hole
본 발명은 반도체 소자의 제조공정중 미세 콘택홀을 형성하는 방법에 관한 것으로, 특히 감광막을 얇게 도포한 후 경화하는 공정을 통하여 미세 콘택홀을 형성하므로써, 해상력, 공정마진 그리고 설계마진을 향상시킬 수 있는 반도체 소자의 미세 콘택홀을 형성하는 방범에 관한 것이다.The present invention relates to a method of forming a fine contact hole during the manufacturing process of a semiconductor device, in particular by forming a fine contact hole through a process of applying a thin photosensitive film and then curing, it is possible to improve the resolution, process margin and design margin The present invention relates to a security for forming a fine contact hole of a semiconductor device.
일반적으로 반도체 소자에서 콘택홀 형성공정은 배선과 배선 사이를 연결시켜 주기 위한 공정으로 절연막을 식각하여 상하간에 전기전 특성을 갖게 한다. 이 콘택홀 형성공정은 설계시 상층과 하층을 연결시켜야 하기 때문에 하층의 구조 및 설계룰에 따라 설계의 제약을 받게 된다. 부족한 설계마진을 확보하기 위하여 자기정렬 콘택공정(Self-Aligned Contact : SAC)이 보편화 되어 있으나 공정이 복잡하다는 단점이 있다.In general, the contact hole forming process in the semiconductor device is a process for connecting the wirings and the wirings to etch the insulating film to have electrical properties between the top and bottom. Since the contact hole forming process is required to connect the upper and lower layers in the design, it is subject to design constraints according to the structure and design rules of the lower layer. In order to secure insufficient design margin, self-aligned contact process (SAC) is common, but the process is complicated.
그리고, 종래기술로서 감광막을 이용하여 콘택홀을 형성한 상태를 도시한 제1도 및 제2도를 참조하여 미세 콘택홀 형성시 문제점을 설명하면, 제1도는 실리콘 웨이펴(1)상의 평면구조에서 감광막(2)을 도표하여 콘택홀(3)을 형성한 상태를 도시한 것으로, 이러한 구조형성은 노광장치의 한계에 의하여 공정한계를 갖는다.In addition, referring to FIGS. 1 and 2 showing a state in which contact holes are formed using a photoresist film as a prior art, FIG. 1 illustrates a problem in forming a fine contact hole. The contact hole 3 is formed by plotting the photoresist film 2 in the drawing. This structure formation has a process limit due to the limitation of the exposure apparatus.
제2도는 소정의 콘택기판(10)상에 절연막(11)이 전체적으로 둘러쌓여 서로 이웃하고 있는 제1금속배선(12) 및 제2금속배선(12)이 구비된 토플러지(Topology)구조에서 감광막(14)을 도포하여 상기 제1금속배선(12)과 제2금속배선(13)사이에 미형성된 콘택홀(15)의 상태를 도시한 것으로, 상기 콘택홀(15)은 상기 제1금속배선(12)과 제2금속배선(13)사이의 설계룰이 작은 경우 또는 하층의 배선구조에 의하여 토플러지의 차가 심할 경우에 상기 콘택홀(15)의 크기와 설계마진이 작아지고, 심한 토플러지로 감광막(14)에 콘택홀 형성시 이 콘택홀이 갖는 에너지 부포 특성으로 인하여 콘택홀(15)은 미형성되어 제품의 특성이 저하된다.FIG. 2 is a photoresist film in a topology structure in which a first metal wiring 12 and a second metal wiring 12 are adjacent to each other with the insulating film 11 entirely surrounded on a predetermined contact substrate 10. (14) shows the state of the non-formed contact hole 15 between the first metal wiring 12 and the second metal wiring 13, wherein the contact hole 15 is the first metal wiring When the design rule between the 12 and the second metal wiring 13 is small or when the difference in the top plug due to the lower wiring structure is severe, the size of the contact hole 15 and the design margin are reduced, and the photoresist film is severely exposed. When the contact hole is formed at 14, the contact hole 15 is not formed due to the energy buoyancy characteristic of the contact hole, thereby degrading the characteristics of the product.
따라서, 본 발면은 상기한 문제점을 해결하기 위하여 1차적으로 감광막을 얇게 도포하여 마스크 공정 및 식각공정으로 1차 콘택홀을 형성한 후에 경화시키고, 그 상부에 2차적으로 감광막을 소정의 두께로 도포하여 상기와 같이 마스크 공정 및 식각공정을 통하여 2차 콘택홀을 형성하므로써, 해상도를 증가시키고 공정마진과 설계마진을 확보하여 제품의 신뢰성을 증가시킬 수 있는 반도체 소자의 미세 콘택홀을 형성하는 방법을 제공함에 그 목적이 있다.Therefore, in order to solve the above problems, the present invention firstly thins the photoresist film, forms a primary contact hole by a mask process and an etching process, and then hardens it. Secondly, the photoresist film is secondarily applied to a predetermined thickness. By forming the second contact hole through the mask process and the etching process as described above, a method of forming a fine contact hole of a semiconductor device that can increase the resolution, secure process margin and design margin to increase the reliability of the product The purpose is to provide.
이러한 목적을 달성하기 위한 본 발명은 소정의 콘택기판(10)상에 절연막(11)으로 둘러쌓여 서로 이웃하고 있는 제1금속배선(12) 및 제2금속배선(13)을 구비하고, 상기 절연막(11) 상부에 제1감광막(16)을 얇게 도포한 다음, 마스크 공정 및 식각공정을 통하여 상기 제1 및 제2금속배선(12 및 13) 사이에 제1콘택홀(17)을 형성하고, 상기 제1콘택홀(17)이 형성된 제1감광막(16)을 약 120∼140℃의 온도로 경화공정을 실시하여 제1콘택홀(17)의 모서리를 완만하게 하면서 제1감광막(16)을 견고히 하고, 상기 경화공정으로 경화된 제1감광막(16a) 상부와 제1콘택홀(17a)에 전반적으로 제2감광막(18)을 도포한 다음, 마스크 공정 및 식각공정으로 제2콘택홀(19)을 형성하여 이루어지는 것을 특징으로 한다.The present invention for achieving this purpose is provided with a first metal wiring 12 and a second metal wiring 13 which is surrounded by an insulating film 11 on a predetermined contact substrate 10 and adjacent to each other, the insulating film (11) After the first photosensitive film 16 is applied thinly on the upper surface, a first contact hole 17 is formed between the first and second metal wires 12 and 13 through a mask process and an etching process. The first photoresist layer 16 is formed by curing the first photoresist layer 16 having the first contact hole 17 at a temperature of about 120 ° C. to 140 ° C. while smoothing the corners of the first contact hole 17. The second photoresist film 18 is generally applied to the upper portion of the first photoresist film 16a and the first contact hole 17a that are hardened by the curing process, and then the second contact hole 19 is formed by a mask process and an etching process. It is characterized by forming a).
이하, 본 발명을 첨부된 도명을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제3a도 내지 제3d도는 본 발명에 의한 반도체 소자의 미세 콘택홀을 형성하는 단계를 도시한 것으로, 제3a도는 소정의 콘택기판(10)상에 절연막(11)으로 둘러쌓여 서로 이웃하고 있는 제1금속배선(12) 및 제 2금속배선(13)이 구비된 상태를 도시한 것이다.3A to 3D illustrate a step of forming a fine contact hole of a semiconductor device according to the present invention, and FIG. 3A is a third embodiment adjacent to each other by being surrounded by an insulating film 11 on a predetermined contact substrate 10. 1 shows the state in which the metal wiring 12 and the second metal wiring 13 are provided.
상기 콘택기판(10)은 예를들어, 실리콘 기판 또는 소정의 배선장치이고, 상기 제1 및 2금속배선(12 및 13)은 예를 들어, 반도체 소자의 게이트 전극이다.The contact substrate 10 is, for example, a silicon substrate or a predetermined wiring device, and the first and second metal wirings 12 and 13 are, for example, gate electrodes of semiconductor devices.
제3b도는 상기 제3A동의 전체구조 상부에 제1감광막(16)을 얇게 도포한 다음, 마스크 공정 및 식각공정을 통하여 상기 제1 및 2금속배선(12 및 13) 사이에 제1콘택홀(17)을 형성한 상태를 도시한 것이다.FIG. 3b shows a thin film of the first photoresist film 16 on the entire structure of the third A copper, and then the first contact hole 17 between the first and second metal wirings 12 and 13 through a mask process and an etching process. ) Is a state formed.
상기 얇게 도포된 제1감광막(16)의 두께는 약 0.4um 정도이다.The thinly coated first photosensitive film 16 has a thickness of about 0.4 μm.
제3c도는 상기 제1콘택홀(17)이 형성된 제1감광막(16)을 약 120∼140℃의 온도로 경화공정을 실시하여 제1콘택홀(17)의 모서리를 완만하게 하면서 제1감광막(16)을 견고하게한 상태를 도시한 것이다.3c illustrates that the first photoresist film 16 having the first contact hole 17 formed thereon is cured at a temperature of about 120 to 140 ° C. to smooth the corners of the first contact holes 17. 16 shows a state of solidification.
도면의 미설명부호(16a)는 제1감광막(16)을 경화한 것임을 나타낸 것이고, 부호(17a)는 경화공정으로 제1콘택홀(17)의 각진 모서리가 완만하게 되었음을 나타낸 것이다.In the drawing, reference numeral 16a indicates that the first photosensitive film 16 is cured, and reference number 17a indicates that the angular edge of the first contact hole 17 is smoothed by the curing process.
제3d도는 상기 경화된 제1감광막(16a) 상부와 제1콘택혹(17a)에 전반적으로 소정의 두께를 갖는 제2 감광막(18)을 도포한 다음, 상기 제3b도의 공정에서 제1감광막(16)의 제1콘택홀(17) 형성시 사용한 마스크의 배열과 동일한 마스크로 마스크 공정을 실시하고, 이후 식각공정으로 제2콘택홀(19)을 형성한 상태를 도시한 것이다.FIG. 3d shows a second photoresist film 18 having a predetermined thickness on the upper portion of the cured first photoresist film 16a and the first contact hatch 17a, and then, in the process of FIG. 16 shows a state in which a mask process is performed using the same mask as that of the mask used when the first contact hole 17 is formed, and then the second contact hole 19 is formed by an etching process.
한편, 상기 제2콘택홀(19)이 형성된 제2감광막(18)을 상기 제3c도 단계와 같이 경화공정으로 경화 가능하다.Meanwhile, the second photosensitive film 18 having the second contact hole 19 formed thereon may be cured in a curing process as in step 3c.
상술한 바와같이 본 발명에 의한 반도체 소자의 미세 콘택홀을 형성하는 방법으로 콘택홀을 형성하므로써, 해상도를 증가시키고 공정마진과 설계마진을 확보하여 제품의 신뢰성을 증가시킬 수 있다.As described above, by forming the contact hole in the method of forming the fine contact hole of the semiconductor device according to the present invention, it is possible to increase the resolution, secure the process margin and the design margin, and increase the reliability of the product.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930010487A KR960008559B1 (en) | 1993-06-10 | 1993-06-10 | Fine contact hall forming method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930010487A KR960008559B1 (en) | 1993-06-10 | 1993-06-10 | Fine contact hall forming method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950001892A KR950001892A (en) | 1995-01-04 |
| KR960008559B1 true KR960008559B1 (en) | 1996-06-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930010487A KR960008559B1 (en) | 1993-06-10 | 1993-06-10 | Fine contact hall forming method of semiconductor device |
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| KR (1) | KR960008559B1 (en) |
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- 1993-06-10 KR KR1019930010487A patent/KR960008559B1/en not_active IP Right Cessation
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| KR950001892A (en) | 1995-01-04 |
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