KR950001892A - Method of forming fine contact hole in semiconductor device - Google Patents

Method of forming fine contact hole in semiconductor device Download PDF

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Publication number
KR950001892A
KR950001892A KR1019930010487A KR930010487A KR950001892A KR 950001892 A KR950001892 A KR 950001892A KR 1019930010487 A KR1019930010487 A KR 1019930010487A KR 930010487 A KR930010487 A KR 930010487A KR 950001892 A KR950001892 A KR 950001892A
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KR
South Korea
Prior art keywords
contact hole
semiconductor device
film
forming
curing
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KR1019930010487A
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Korean (ko)
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KR960008559B1 (en
Inventor
함영목
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김주용
현대전자산업 주식회사
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Priority to KR1019930010487A priority Critical patent/KR960008559B1/en
Publication of KR950001892A publication Critical patent/KR950001892A/en
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Publication of KR960008559B1 publication Critical patent/KR960008559B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 미세 콘택홀 형성방법에 관한 것으로, 소정의 콘택기판(10)상에 절연막(11)으로 둘러쌓여 서로 이웃하고 있는 제 1 금속배선(12) 및 제 2 금속배선(13)을 구비하고, 상기 절연막(11) 상부에 제 1 감광막(16)을 얇게 도포한 다음, 마스크 공정 및 식각공정을 통하여 상기 제1 및 2금속배선(12 및 13)사이에 제 1 콘택홀(17)을 형성하고, 상기 제 1 콘택홀(17)이 형성된 제 1 감광막(16)을 약 120∼140℃의 온도로 경화공정을 실시하여 제 1 콘택홀(17)의 모서리를 완만하게 하면서 제 1 감광막(16)을 견고히 하고, 상기 경화공정으로 경화된 제 1 감광막(16a) 상부와 제 1 콘택홀(17a)에 전반적으로 제 2 감광막(18)을 도포한 다음, 마스크 공정 및 식각공정으로 제 2 콘택홀(19)을 형성하여, 해상도를 증가시키고 공정마진과 설계마진을 확보하여 제품의 신뢰성을 증가시킬 수 있는 반도체 소자의 미세 콘택홀을 형성하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a fine contact hole in a semiconductor device, and includes a first metal wiring 12 and a second metal wiring 13 enclosed by an insulating film 11 on a predetermined contact substrate 10 and adjacent to each other. And a thin coating of the first photoresist layer 16 on the insulating layer 11, and then a first contact hole 17 between the first and second metal wirings 12 and 13 through a mask process and an etching process. ) And curing the first photosensitive film 16 having the first contact hole 17 at a temperature of about 120 to 140 ° C. to smooth the corners of the first contact hole 17. The photoresist film 16 is hardened, and the second photoresist film 18 is generally applied to the upper portion of the first photoresist film 16a and the first contact hole 17a that are cured by the curing process, and then, the mask process and the etching process are performed. 2 Contact hole 19 is formed to increase the resolution, process margin and design margin to ensure product reliability It is for forming a fine contact hole of a semiconductor device capable of increasing technology.

Description

반도체 소자의 미세 콘택홀 형성방법Method of forming fine contact hole in semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3A도 내지 제3D도는 본 발명에 의한 콘택홀 형성단계를 나타낸 단면도이다.3A to 3D are cross-sectional views illustrating a step of forming a contact hole according to the present invention.

Claims (3)

소정의 콘택기판(10)상에 절연막(11)으로 둘러쌓여 서로 이웃하고 있는 제1금속배선(12) 및 제2금속배선(13)을 구비된 반도체 소자의 미세 콘택홀 형성방법에 있어서, 상기 절연막(11) 상부에 제1감광막(16)을 얇게 도포한 다음, 마스크 공정 및 식각공정을 통하여 상기 제 1 및 제2금속배선(12 및 13)사이에 제1콘택홀(17)을 형성하는 단계와, 상기 제1콘택홀(17)이 형성된 제1감광막(16)을 약 120∼140°C의 온도로 경화공정을 실시하여 제1콘택홀(17)의 모서리를 완만하게 하면서 제1감광막(16)을 견고히 하는 단계와, 상기 경화공정으로 경화된 제1감광막(16a)상부와 제1콘택홀(17a)에 전반적으로 제2감광막(18)을 도포한다음, 마스크 공정 및 식각공정으로 상기 제2콘택홀(18)의 소정부분을 식각하여 제2콘택홀(19)을 형성하고, 상기 패턴화된 제2감광막(18)을 경화하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 미세콘택홀 형성방법.In the method for forming a fine contact hole of a semiconductor device having a first metal wiring 12 and a second metal wiring 13 which are surrounded by an insulating film 11 on a predetermined contact substrate 10 and adjacent to each other. The first photoresist film 16 is thinly coated on the insulating film 11, and then the first contact hole 17 is formed between the first and second metal wires 12 and 13 through a mask process and an etching process. And curing the first photosensitive film 16 on which the first contact hole 17 is formed at a temperature of about 120 to 140 ° C. to smooth the corners of the first contact hole 17. (16) is solidified, and the second photosensitive film 18 is generally applied to the upper portion of the first photosensitive film 16a and the first contact hole 17a cured by the curing process, followed by a mask process and an etching process. Etching a predetermined portion of the second contact hole 18 to form a second contact hole 19 and curing the patterned second photoresist film 18. Forming fine contact hole, a semiconductor device, characterized in that where the lure. 제1항에 있어서, 상기 제1감광막(16)의 두께는 0.4um인 것을 특징으로 하는 반도체 소자의 미세 콘택홀 형성방법.The method of claim 1, wherein the thickness of the first photosensitive film (16) is 0.4 um. 제1항에 있어서, 상기 제1콘택홀(17) 및 상기 제 2콘택홀(19) 형성시 동일한 배열구조를 갖는 마스크를 사용하는 것을 특징으로 하는 반도체 소자의 미세 콘택홀 형성방법.2. The method of claim 1, wherein a mask having the same arrangement structure is used when forming the first contact hole (17) and the second contact hole (19). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930010487A 1993-06-10 1993-06-10 Fine contact hall forming method of semiconductor device KR960008559B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930010487A KR960008559B1 (en) 1993-06-10 1993-06-10 Fine contact hall forming method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930010487A KR960008559B1 (en) 1993-06-10 1993-06-10 Fine contact hall forming method of semiconductor device

Publications (2)

Publication Number Publication Date
KR950001892A true KR950001892A (en) 1995-01-04
KR960008559B1 KR960008559B1 (en) 1996-06-28

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KR1019930010487A KR960008559B1 (en) 1993-06-10 1993-06-10 Fine contact hall forming method of semiconductor device

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KR960008559B1 (en) 1996-06-28

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