KR940018930A - Planarization method of semiconductor device - Google Patents

Planarization method of semiconductor device Download PDF

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Publication number
KR940018930A
KR940018930A KR1019930000613A KR930000613A KR940018930A KR 940018930 A KR940018930 A KR 940018930A KR 1019930000613 A KR1019930000613 A KR 1019930000613A KR 930000613 A KR930000613 A KR 930000613A KR 940018930 A KR940018930 A KR 940018930A
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KR
South Korea
Prior art keywords
region
field
active region
reducing
semiconductor device
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Application number
KR1019930000613A
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Korean (ko)
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KR960006960B1 (en
Inventor
양두영
Original Assignee
문정환
금성일렉트론 주식회사
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Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019930000613A priority Critical patent/KR960006960B1/en
Publication of KR940018930A publication Critical patent/KR940018930A/en
Application granted granted Critical
Publication of KR960006960B1 publication Critical patent/KR960006960B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers

Abstract

본 발명은 반도체 소자의 필드영역과 활성영역의 단차를 줄이는 방법에 관한것으로, 필드 산화막 형성될 영역에 에피실리콘을 높게 증착시켜 초기 공정에서 활성 영역과 필드영역과의 단차를 크게하여 궁극적으로 반도체 소자 제조 공정에서 생기는 활성 영역과 필드영역의 단차를 줄여 제2워드라인 금속 패턴시 패턴불량을 줄여 마스킹 공정의 신뢰도를 높일 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of reducing the step difference between the field region and the active region of a semiconductor device, and to increase the step difference between the active region and the field region in an initial process by depositing high episilicon in a region where a field oxide film is to be formed. The reliability of the masking process can be increased by reducing the pattern defect in the second word line metal pattern by reducing the step difference between the active region and the field region generated in the manufacturing process.

Description

반도체 소자의 평판화 방법Flattening method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 반도체 소자 평탄화 공정 단면도.3 is a cross-sectional view of a semiconductor device planarization process according to the present invention.

Claims (2)

실리콘기판(1)위에 절연막을 증착하고 활성영역에만 절연막이 남도록 패터닝하는 공정과, 상기 절연막이 제거된 필드영역에 에피-실리콘(13)을 성정시켜 활성영역보다 필드 영역이 높도록 형성하는 공정과, 필드 영역에 LOCOS 공정으로 필드산화막(2)을 형성하는 공정과, 상기와 같이 형성된 기판위에 반도체 소자를 형성하는 공정을 포함하여 이루어짐을 특징으로하는 반도체 소자의 평탄화 방법.Depositing an insulating film on the silicon substrate 1 and patterning the insulating film to remain only in the active region; and forming an epi-silicon 13 in the field region from which the insulating film is removed to form a field region higher than the active region; And forming a field oxide film (2) in the field region by a LOCOS process, and forming a semiconductor element on the substrate formed as described above. 제1항에 있어서, 절연막은 산화막(11a)으로 형성함으로 특징으로 하는 반도체 소자의 평탄화 방법.2. The method of claim 1, wherein the insulating film is formed of an oxide film (11a). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930000613A 1993-01-19 1993-01-19 Plannerizing method of semiconductor device KR960006960B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930000613A KR960006960B1 (en) 1993-01-19 1993-01-19 Plannerizing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930000613A KR960006960B1 (en) 1993-01-19 1993-01-19 Plannerizing method of semiconductor device

Publications (2)

Publication Number Publication Date
KR940018930A true KR940018930A (en) 1994-08-19
KR960006960B1 KR960006960B1 (en) 1996-05-25

Family

ID=19349772

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930000613A KR960006960B1 (en) 1993-01-19 1993-01-19 Plannerizing method of semiconductor device

Country Status (1)

Country Link
KR (1) KR960006960B1 (en)

Also Published As

Publication number Publication date
KR960006960B1 (en) 1996-05-25

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