KR960005809A - Pattern formation method of semiconductor device - Google Patents

Pattern formation method of semiconductor device Download PDF

Info

Publication number
KR960005809A
KR960005809A KR1019940018403A KR19940018403A KR960005809A KR 960005809 A KR960005809 A KR 960005809A KR 1019940018403 A KR1019940018403 A KR 1019940018403A KR 19940018403 A KR19940018403 A KR 19940018403A KR 960005809 A KR960005809 A KR 960005809A
Authority
KR
South Korea
Prior art keywords
forming
semiconductor device
pattern
gas
conductive layer
Prior art date
Application number
KR1019940018403A
Other languages
Korean (ko)
Other versions
KR0144430B1 (en
Inventor
장현진
오세준
이우봉
문영화
전영호
고재완
구영모
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940018403A priority Critical patent/KR0144430B1/en
Publication of KR960005809A publication Critical patent/KR960005809A/en
Application granted granted Critical
Publication of KR0144430B1 publication Critical patent/KR0144430B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Abstract

본 발명은 반도체 소자의 패턴 형성방법에 관한 것으로, 반사율이 높은 도전층을 패터닝하기 위한 사진공정시 발생되는 광간섭 현상을 방지하기 위해 도전층 형성 후 소정의 가스분위기하에서 실리콘 타겟(Si Target)을 이용하여 스퍼터링방법에 의해 그 상부에 저반사막(Anti-Reflective Coating)을 형성시키고 패터닝(Patterning)하므로써 패턴의 직선성 및 균일도를 향상시킬 수 있도록 한 반도체 소자의 패턴 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a pattern of a semiconductor device. In order to prevent optical interference caused during a photolithography process for patterning a highly reflective conductive layer, a silicon target (Si Target) is formed under a predetermined gas atmosphere after the conductive layer is formed. The present invention relates to a method of forming a pattern of a semiconductor device in which a low reflection film (Anti-Reflective Coating) is formed and patterned on the top thereof by a sputtering method, thereby improving the linearity and uniformity of the pattern.

Description

반도체 소자의 패턴 형성방법Pattern formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1A 내지 제1C도는 본 발명에 따른 반도체 소자의 패턴 형성방법을 설명하기 위한 소자의 단면도이다.1A to 1C are cross-sectional views of devices for explaining a method of forming a pattern of a semiconductor device according to the present invention.

제2도는 제1A도의 저반사막을 형성하기 위한 스퍼터링 장비의 구조도이다.FIG. 2 is a structural diagram of sputtering equipment for forming the low reflection film of FIG. 1A.

Claims (4)

소자내부 집적층이 형성된 소정의 기판(1)상에 절연층(2)및 도전층(3)을 순차적으로 형성시킨 상태에서, 상기 도전층(3)을 패턴화하기 위한 반도체 소자의 패턴 형성방법에 있어서, 상기 도전층(3)상부에 실리콘 타겟을 이용한 스퍼터링 방법에 의해 소정의 가스 분위기 및 저온에서 저반사막(4)을 형성시키는 단계와, 상기 단계로부터 감광막(5)을 도포하고 소정의 마스크를 통해 노광시킨 후 상기 감광막(5)을 현상시켜 패터닝하는 단계와, 상기 단계로부터 상기 감광막 패턴(5)을 마스크로 이용하여 상기 저반사막(4) 및 도전층(3)을 순차적으로 식각하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 패턴 형성방법.A method of forming a pattern of a semiconductor device for patterning the conductive layer 3 in a state in which an insulating layer 2 and a conductive layer 3 are sequentially formed on a predetermined substrate 1 on which an internal device integrated layer is formed. A method of forming a low reflection film (4) in a predetermined gas atmosphere and low temperature by sputtering using a silicon target on the conductive layer (3), and applying the photosensitive film (5) from the step Exposing through the photoresist film 5 and patterning the photoresist film 5, and sequentially etching the low reflection film 4 and the conductive layer 3 using the photoresist pattern 5 as a mask. Pattern forming method of a semiconductor device, characterized in that consisting of. 제1항에 있어서, 상기 저반사막(4)은 SixOyNz, SixNy 또는 SixOy구조인 것을 특징으로 하는 반도체 소자의 패턴 형성방법.The method of forming a pattern of a semiconductor device according to claim 1, wherein the low reflection film (4) has a structure of SixOyNz, SixNy or SixOy. 제2항에 있어서, 상기 SixOyNz 구조의 저반사막(4) 형성시 소오스 가스는 Ar 및 N2O가스 또는 N2O가스이며, SixNy구조 형성시 소오스 가스는 Ar 및 N2가스, N2가스이고, SixOy구조 형성시 소오스 가스는 Ar 및 O2가스 또는 O2가스인 것을 특징으로 하는 반도체 소자의 패턴 형성방법.The method of claim 2, wherein the source gas when forming the low-reflection film 4 of the SixOyNz structure is Ar and N 2 O gas or N 2 O gas, the source gas when forming the SixNy structure is Ar and N 2 gas, N 2 gas The source gas for forming a SixOy structure is a pattern forming method of a semiconductor device, characterized in that the Ar and O 2 gas or O 2 gas. 제1항에 있어서, 상기 저반사막(4)은 상기 도전층(3) 형성 후 동일 장비 내에서 연속적으로 형성되며 400℃이하의 저온에서 1000A 이하의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 패턴 형성방법.The pattern of the semiconductor device according to claim 1, wherein the low reflection film (4) is formed continuously in the same equipment after the formation of the conductive layer (3) and formed at a thickness of 1000 A or less at a low temperature of 400 ° C or less. Formation method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940018403A 1994-07-28 1994-07-28 Method for making pattern of semiconductor KR0144430B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940018403A KR0144430B1 (en) 1994-07-28 1994-07-28 Method for making pattern of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940018403A KR0144430B1 (en) 1994-07-28 1994-07-28 Method for making pattern of semiconductor

Publications (2)

Publication Number Publication Date
KR960005809A true KR960005809A (en) 1996-02-23
KR0144430B1 KR0144430B1 (en) 1998-08-17

Family

ID=19389105

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940018403A KR0144430B1 (en) 1994-07-28 1994-07-28 Method for making pattern of semiconductor

Country Status (1)

Country Link
KR (1) KR0144430B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101698383B1 (en) 2015-07-17 2017-01-20 최연수 Finish material support apparatus and construction method of brick wall using the same

Also Published As

Publication number Publication date
KR0144430B1 (en) 1998-08-17

Similar Documents

Publication Publication Date Title
US4092442A (en) Method of depositing thin films utilizing a polyimide mask
JPS56122130A (en) Method for forming pattern of thin film transistor
KR960005809A (en) Pattern formation method of semiconductor device
KR0161917B1 (en) Method of manufacturing semiconductor device
KR100350762B1 (en) Formation method of micropattern
KR19980052471A (en) Manufacturing Method of Semiconductor Device
KR970052354A (en) Contact hole formation method of semiconductor device
KR0130386B1 (en) Patterning method of photoresist
KR970048979A (en) Mask formation method with fine pattern
KR960008095B1 (en) Method of micro patterning using organo arc layer
KR970018149A (en) Fine Pattern Formation Method of Semiconductor Device
KR970016754A (en) Method of manufacturing mask for semiconductor device
KR970018041A (en) Method of forming fine contact hole in semiconductor device
KR940015698A (en) Fine photoresist pattern formation method
KR950021761A (en) Method of manufacturing thin film transistor
KR950001918A (en) Gate pattern forming method using nitride film
KR970023705A (en) Opening Formation Method of Semiconductor Device
KR970023636A (en) Fine wiring formation method of semiconductor device
KR950009360A (en) Method of forming fine pattern of semiconductor device
KR960002597A (en) Fine pattern formation method
KR940015709A (en) Aluminum wiring etching method of semiconductor device
KR970018032A (en) Small contact formation method of semiconductor device
KR970052963A (en) Manufacturing method of semiconductor device
KR950029846A (en) Phase reversal mask manufacturing method
KR970008403A (en) Insulation Planarization Method

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090327

Year of fee payment: 12

LAPS Lapse due to unpaid annual fee