KR970052354A - Contact hole formation method of semiconductor device - Google Patents

Contact hole formation method of semiconductor device Download PDF

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Publication number
KR970052354A
KR970052354A KR1019950056956A KR19950056956A KR970052354A KR 970052354 A KR970052354 A KR 970052354A KR 1019950056956 A KR1019950056956 A KR 1019950056956A KR 19950056956 A KR19950056956 A KR 19950056956A KR 970052354 A KR970052354 A KR 970052354A
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KR
South Korea
Prior art keywords
photoresist film
contact hole
photoresist
film
forming
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Application number
KR1019950056956A
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Korean (ko)
Inventor
김인철
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019950056956A priority Critical patent/KR970052354A/en
Publication of KR970052354A publication Critical patent/KR970052354A/en

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 콘택 홀 형성 방법에 관한 것으로, 특히 건식 식각에 의한 반도체 소자의 콘택홀 형성 방법에 관한 것이다. 이와 같은 본 발명의 콘택 홀 형성 방법은 실리콘 기판상에 실리콘 산화막을 형성하는 단계; 상기 실리콘 산화막 상에 콘택 홀을 형성할 영역에 제1감광막을 도포한 후 노광하는 단계; 제1감광막을 경화시키는 단계; 제1감광막 상에 제2감광막을 도포한 다음 노광하는 단계; 제1감광막과 제2감광막을 현상하여 제1감광막 패턴과 제2감광막 패턴을 형성하는 단계; 이방성 식각을 행하여 콘택 홀을 형성하는 단계를 포함하는 것을 특징으로 한다. 특히, 본 발명은, 2층의 크기가 다른 감광막 패턴을 형성하여 식각하므로써 스텝 커버리지를 향상시키는 깔데기 모양의 콘택 홀을 건식 식각만을 통해 형성할 수 있으므로 공정을 간소화시키는 효과를 제공한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device by dry etching. Such a contact hole forming method of the present invention comprises the steps of forming a silicon oxide film on a silicon substrate; Exposing a first photoresist film to a region where a contact hole is to be formed on the silicon oxide film and then exposing the first photoresist film; Curing the first photoresist film; Coating and then exposing the second photoresist film on the first photoresist film; Developing the first photoresist film and the second photoresist film to form a first photoresist film pattern and a second photoresist film pattern; And anisotropic etching to form contact holes. In particular, the present invention provides an effect of simplifying the process, since a funnel-shaped contact hole that improves step coverage by forming and etching photoresist patterns having different sizes of two layers can be formed only by dry etching.

Description

반도체 소자의 콘택 홀 형성방법Contact hole formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도 (가) 내지 (마)는 본 발명의 일 실시예에 따른 콘택 홀 형성 공정 단계를 설명하기 위한 반도체 소자의 요부 단면도.2 (a) to (e) are cross-sectional views of principal parts of a semiconductor device for explaining a process of forming a contact hole according to an embodiment of the present invention.

Claims (5)

실리콘 기판상에 실리콘 산화막을 형성하는 단계; 상기 실리콘 산화막 상에 콘택 홀을 형성할 영역에 제1감광막을 도포한 후 노광하는 단계; 제1감광막을 경화시키는 단계; 제1감광막 상에 제2감광막을 도포한 다음 노광하는 단계; 제1감광막과 제2감광막을 현상하여 제1감광막 패턴과 제2감광막 패턴을 형성하는 단계; 이방성 식각을 행하여 콘택 홀을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 콘택 홀 형성방법.Forming a silicon oxide film on the silicon substrate; Exposing a first photoresist film to a region where a contact hole is to be formed on the silicon oxide film and then exposing the first photoresist film; Curing the first photoresist film; Coating and then exposing the second photoresist film on the first photoresist film; Developing the first photoresist film and the second photoresist film to form a first photoresist film pattern and a second photoresist film pattern; And forming a contact hole by performing anisotropic etching. 제1항에 있어서, 제1차 감광막 패턴의 폭은 형성할 콘택 홀 중 하부에 폭에 해당되고 제2차 감광막 패턴의 폭은 형성할 콘택 홀 중 상부의 폭에 해당되도록 제1차 감광막 패턴보다 넓은 폭으로 형성하는 것을 특징으로 하는 반도체 소자의 콘택 홀 형성방법.The method of claim 1, wherein the width of the first photoresist pattern corresponds to a lower portion of the contact holes to be formed, and the width of the second photoresist pattern corresponds to the width of the upper portion of the contact holes to be formed. A contact hole forming method of a semiconductor device, characterized in that formed in a wide width. 제1항에 있어서, 제1감광막의 두께는 산화막을 식각하여 콘택 홀을 형성할 때 식각되고 그 밑의 산화막까지 어느 정도 식각이 될 수 있도록 산화막과 감광막의 식각 선택비를 고려하여 결정하는 것을 특징으로 하는 반도체 소자의 콘택 홀 형성방법.The method of claim 1, wherein the thickness of the first photoresist layer is determined in consideration of the etch selectivity of the oxide and photoresist layer to be etched when the oxide film is etched to form a contact hole, and to be etched to some extent below the oxide film. A contact hole forming method of a semiconductor device. 제1항에 있어서, 제1감광막을 경화시키는 단계는, 150℃ 이상의 온도에서 하드 베이킹을 실시하는 것을 특징으로 하는 반도체 소자의 콘택 홀 형성방법.The method of claim 1, wherein the hardening of the first photosensitive film comprises hard baking at a temperature of 150 ° C. or higher. 제1항에 있어서, 이방성 건식 식각하는 단계는, CF4/CHF3/Ar의 혼합 가스를 이용하여 식각을 행하고, 통상적으로 산화막과 감광막의 선택비가 5:1 내지 8:1 정도이므로, 산화막과 동시에 제1감광막도 식각이 진행되는 것을 특징으로 하는 반도체 소자의 콘택 홀 형성방법.The method of claim 1, wherein the anisotropic dry etching is performed by using a mixed gas of CF 4 / CHF 3 / Ar, and the selectivity between the oxide film and the photosensitive film is typically about 5: 1 to 8: 1. And etching the first photoresist film at the same time. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950056956A 1995-12-26 1995-12-26 Contact hole formation method of semiconductor device KR970052354A (en)

Priority Applications (1)

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KR1019950056956A KR970052354A (en) 1995-12-26 1995-12-26 Contact hole formation method of semiconductor device

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Application Number Priority Date Filing Date Title
KR1019950056956A KR970052354A (en) 1995-12-26 1995-12-26 Contact hole formation method of semiconductor device

Publications (1)

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KR970052354A true KR970052354A (en) 1997-07-29

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