JPH11224898A - Method for forming channel hole using resist - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form channels and holes for wiring of dual damascene structure with one-time etching. SOLUTION: A lower resist 21 for deep holes is formed with a resist for KrF or an SiO2 layer 2 to be etched, and an upper resist 31 is formed with a resist for i-line on the lower resist 21 (A). When an etching process is performed in an initial stage, SiO2 layer 2 is etched in the pattern of the lower resist 21 to form a contact hole 4 and etch a portion of the lower resist 21 not covered with an upper resist 31 (C). When the etching process proceeds further, the SiO2 layer 2 is etched in the pattern of the upper resist 31 to form a channel 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a groove using a resist, and more particularly to a method for simplifying a manufacturing process.

[0002]

2. Description of the Related Art Today, a wiring method having a dual-damascene structure shown in FIG. 3 is known. By employing the dual damascene structure, a groove for the upper wiring 7 and a vertical hole for forming the plug 8 can be formed in the insulating layer 2 and the upper wiring 7 and the plug 8 can be formed in one process. .

A method of manufacturing a semiconductor having a dual damascene structure will be described with reference to FIG. First, on the lower wiring 3 and the insulating layer 2 formed on the insulating layer 1, FIG.
As shown in FIG. 7, a resist 61 having an opening 62 is formed. Etching is performed in this state. As a result, FIG.
B, a groove 6 is formed on the upper surface of the insulating layer 2.
After removing the resist 61, a resist 71 having an opening 72 is formed as shown in FIG. 4C. Etching is performed in this state. Thereby, as shown in FIG. 4D, a contact hole 4 for connecting the groove 6 and the lower wiring 3 is formed. After removing the resist 71, the upper wiring 7 and the plug 8 are formed as shown in FIG.

[0004] However, in the above manufacturing method,
Two etching steps are required. This complicates the manufacturing process. Such a problem similarly occurs when forming a deep hole and a wide groove other than the dual damascene structure.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problem and to provide a groove forming method capable of forming a shallow groove and a deep hole by a simple manufacturing process.

[0006]

In the method of forming a groove according to the present invention, a resist having an opening for forming the deep hole on the first layer is provided. Forming a first resist having a first selectivity with respect to the first layer, and a resist having an opening for forming the groove on the first resist, wherein the first resist is formed with respect to the first layer. A second resist having a higher selectivity than the first selectivity is formed, and anisotropic etching is performed. The anisotropic etching forms the deep hole and also etches the first resist that is not covered with the second resist. Further, if the etching is continued, the second
The first layer not covered with the resist is etched. By using resists having different selectivity as described above, the grooves and the deep holes can be formed by one etching.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device using a wiring method having a dual damascene structure according to the present invention will be described with reference to the drawings. First, a lower resist 21 as a first resist is applied on the SiO ₂ layer 2 as a first layer in the same manner as in the prior art. In the present embodiment, the first
As a resist, a resist for KrF having a low selectivity to the SiO ₂ layer 2 was used. Next, using an exposure apparatus (not shown), a mask pattern is baked and baked to form a lower resist 2 having an opening 22 as shown in FIG. 1A.
Form one. The opening 22 is an opening for forming a deep hole to be described later. FIG. 1C shows an arrow view from the direction of arrow A in FIG. 1B.

Next, an upper resist 31, which is a second resist, is applied on the lower resist 21.

In this embodiment, as the second resist,
For the SiO ₂ layer 2, an i-line resist having a higher selectivity than the first resist was used. Next, using an exposure device (not shown), the mask pattern is baked and baked to form an upper resist 31 having an opening 32 as shown in FIG. 2A. The opening 32 is an opening for forming a groove to be described later. FIG. 2B shows an arrow view from the direction of arrow A in FIG. 1A.

When anisotropic etching is performed in this state,
The portion of the SiO ₂ layer 2 that is not covered by the lower resist 21 is etched to form a contact hole 4.
At this time, the lower resist 21, since the selection ratio with respect to the SiO ₂ layer 2 is poor, with the etching of the SiO ₂ layer 2 is etched. Specifically, as shown in FIG. 2C, the lower resist 2 not covered with the upper resist 31 is used.
1 is etched. Therefore, if the etching is further performed, the wiring groove 6 is formed on the SiO ₂ layer 2.

Thereafter, wiring may be formed in the groove 6 and the contact hole 4 as in the conventional case.

As described above, in the present embodiment, the resist for the deep hole is formed on the etching target layer (first layer) for forming the deep hole and the shallow groove with a selectivity relative to the etching target layer. It is formed by a bad first resist, and a resist for the shallow groove is formed on the second resist having a high selectivity with respect to the etching target layer by patterning the second resist, and etching is performed. Thus, in the initial stage of etching, the etching target layer is etched with the first resist pattern, and the deep hole is formed in the etching target layer. Along with the etching of the etching target layer, a portion of the second resist not covered with the first resist is etched. In the later stage of the etching, the first resist portion that is not covered with the second resist has already been etched, and thus the etching target layer is etched with the pattern of the second resist. As a result, the resist is removed by etching after forming the resist as before, and further,
The step of removing the resist by etching after forming another resist becomes unnecessary, and a deep hole and a shallow groove can be formed by one etching.

The thickness of the first resist may be determined by the thickness of the layer to be etched and the selectivity of the first resist. That is, as shown in FIG. 2C, the thickness may be such that the first resist is also etched when the formation of the deep hole is completed.

In this embodiment, KrF is used as the first resist.
Although the i-line resist was used as the second resist, the present invention is not limited to this. Any resist can be used as long as the first resist has a lower selectivity to the etching target layer than the second resist. For example, a KrF resist may be used as the first resist, and a G-line resist may be used as the second resist.

In this embodiment, the case where the shallow groove and the deep hole for the wiring of the dual damascene structure are formed has been described. However, other than the dual damascene structure, the case where the deep hole and the wide groove are formed may be used. The same can be applied.

[Brief description of the drawings]

FIG. 1 is a diagram showing a manufacturing process for forming a shallow deep hole according to the present invention.

FIG. 2 is a diagram showing a manufacturing process for forming a shallow deep hole according to the present invention.

3A and 3B are a main-portion cross-sectional view and a plan view of a semiconductor device for describing a dual damascene structure.

FIG. 4 is a diagram showing a conventional manufacturing process.

[Explanation of symbols]

2 SiO ₂ layer 4 Contact hole 6 Groove 21 Lower resist 31 Upper resist

Claims (1)

[Claims] 1. A deep hole formed in a first layer in a depth direction of the first layer, and a depth direction of the first layer on the upper surface of the first layer, the depth being larger than the depth hole. A groove forming method for forming a groove that is shallow and wide in a direction perpendicular to the depth direction, the resist having an opening for forming the deep hole on the first layer. Forming a first resist having a first selectivity with respect to the first layer, a resist having an opening for forming the groove on the first resist, and Forming a second resist having a higher selectivity than the first selectivity, and performing anisotropic etching on the second resist.