KR950021154A

KR950021154A - Widening step flattening method of semiconductor device

Info

Publication number: KR950021154A
Application number: KR1019930028873A
Authority: KR
Inventors: 김근영
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1993-12-21
Filing date: 1993-12-21
Publication date: 1995-07-26

Abstract

반도체 기판 상부에 셀 지역과 주변회로 지역에 광역 단차가 발생된 하부층 상부에 감광막 패턴을 형성하는 방법에 있어서, 하부층 상부에 제1 감광막을 도포하는 단계와, 상기 제1 감광막을 전면 식각하여 주변회로 지역에만 제1 감광막을 남겨두는 단계와, 전체구조 상부에 제2 감광막을 도포하고, 노광 및 현상공정으로 상기 셀지역과 주변회로 지역에 제2 감광막 패턴을 형성하는 단계와, 산소 플라즈마 식각공정으로 노출된 상기 제1 감광막과 제2 감광막 패턴을 전면 식각하여 주변회로 하부의 제2 감광막 패턴을 제1 감광막으로 전사시켜 제1 감광막 패턴을 형성하는 단계를 포함하는 기술이다.A method of forming a photoresist pattern on an upper portion of a lower layer having a wide area difference in a cell region and a peripheral circuit region on an upper surface of a semiconductor substrate, the method comprising: applying a first photoresist layer on an upper portion of a lower layer; Leaving a first photoresist film only in a region, applying a second photoresist film over the entire structure, and forming a second photoresist pattern in the cell region and the peripheral circuit region by an exposure and development process, and an oxygen plasma etching process. And etching the exposed first photoresist layer and the second photoresist pattern to form a first photoresist pattern by transferring the second photoresist pattern under the peripheral circuit to the first photoresist.

Description

Widening step flattening method of semiconductor device.

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2D도는 본 발명에 의하여 광역단차를 해소하고 감광막 패턴을 형성하는 과정을 나타낸 단면도이다. 제2A도는 광역단차가 있을 경우 감광막 도포후 전면식각하는 단계를 나타낸 단면도, 제2B도는 전면 식각 이 완료된 후 고온에서 처리하여 주변회로 지역에만 감광막 수지가 채워지도록 한 상태를 나타낸 단면도, 제2C도는 상기 과정에 의하여 평탄화가 이루어진 상태에서 감광막을 도포하고 패턴을 형성한 상태의 단면도, 제2D도는 전면 식각에 의하여 상기 감광막 패턴이 하부 감광막에 전사된 상태의 단면도.2A to 2D are cross-sectional views showing a process of eliminating a wide area difference and forming a photosensitive film pattern according to the present invention. Figure 2A is a cross-sectional view showing a step of etching the entire surface after the photosensitive film is applied when there is a wide step, Figure 2B is a cross-sectional view showing a state in which the photoresist resin is filled only in the peripheral circuit area after the surface etching is completed, Figure 2C is the above A cross-sectional view of a state in which a photoresist film is applied and a pattern is formed in a planarized state by a process, and FIG. 2D is a cross-sectional view of the photoresist pattern transferred to a lower photoresist layer by full etching.

Claims

A method of forming a photoresist pattern on an upper portion of a lower layer having a wide area difference in a cell region and a peripheral circuit region on an upper surface of a semiconductor substrate, the method comprising: applying a first photoresist layer on an upper portion of a lower layer; Leaving a first photoresist film only in a region, applying a second photoresist film over the entire structure, and forming a second photoresist pattern in the cell region and the peripheral circuit region by an exposure and development process, and an oxygen plasma etching process. And etching the exposed first photoresist layer and the second photoresist pattern to form a first photoresist pattern by transferring the second photoresist pattern under the peripheral circuit to the first photoresist to form a first photoresist pattern.

2. The method of claim 1, comprising treating and curing at a high temperature after leaving the first photoresist film in the peripheral circuit area.

The method according to claim 1, wherein the thickness of the second photoresist film is thicker than the thickness of the first photoresist film remaining in the peripheral circuit region.

※ Note: The disclosure is based on the initial application.