KR950001925A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
KR950001925A
KR950001925A KR1019930011364A KR930011364A KR950001925A KR 950001925 A KR950001925 A KR 950001925A KR 1019930011364 A KR1019930011364 A KR 1019930011364A KR 930011364 A KR930011364 A KR 930011364A KR 950001925 A KR950001925 A KR 950001925A
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KR
South Korea
Prior art keywords
resist
low step
primary
globally
steps
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Application number
KR1019930011364A
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Korean (ko)
Inventor
복철규
김진웅
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019930011364A priority Critical patent/KR950001925A/en
Publication of KR950001925A publication Critical patent/KR950001925A/en

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  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

본 발명은 반도체 제조공정에서 단차가 발생된 웨이퍼 상부에 평탄화된 레지스트를 도포하기 위하여 광역적으로 낮은 실리콘기판 상부에 1차 레지스트패턴을 형성하고 다시 2차 레지스트를 도포하는 기술이다.The present invention is a technique for forming a first resist pattern on the globally low silicon substrate in order to apply the planarized resist on top of the wafer where the step is generated in the semiconductor manufacturing process, and then again apply a second resist.

Description

반도체소자 제조방법Semiconductor device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 내지 제1E도는 본 발명의 실시예에 의해 광역적으로 단차가 발생된 지역에 1차 레지스트패턴을 형성한 다음, 2차 레지스트를 전체적으로 도포하여 표면을 평탄하게 형성한 단면도.1A to 1E are cross-sectional views in which a first resist pattern is formed in a region where a step difference is generated globally according to an embodiment of the present invention, and then the second resist is applied as a whole to form a flat surface.

Claims (3)

반도체 제조공정에 있어서, 국부적으로 낮은 단차와 광역적으로 낮은 단차가 형성된 웨이퍼상부에 1차 레지스트를 도포하는 단계와, 노광 및 현상공정으로 상기 1차 레지스트의 예정된 부분을 제거하여 광역적으로 낮은 단차가 형성된 웨이퍼 상부에 1차 레지스트 패턴을 형성하는 단계와, 2차 레지스트를 도포하여 국부적으로 낮은 단차와 광역적으로 낮은 단차의 전체구조 상부에 2차 레지스트를 평탄하게 형성하는 단계를 포함하는 반도체소자 제조방법.A semiconductor manufacturing process comprising the steps of applying a primary resist on a wafer on which locally low steps and broadly low steps are formed, and removing a predetermined portion of the primary resist by an exposure and development process to obtain a globally low step. Forming a primary resist pattern on the wafer on which the semiconductor substrate is formed, and applying a secondary resist to form a secondary resist on the entire structure of a locally low step and a globally low step Manufacturing method. 제1항에 있어서, 상기 국부적으로 낮은 단차는 주회로지역이고, 광역적으로 낮은 단차는 주변회로인 것을 특징으로 하는 반도체소자 제조방법.The method of claim 1, wherein the locally low step is a main circuit region, and the globally low step is a peripheral circuit. 제1항에 있어서, 상기 1차 레지스트패턴을 형성한 다음, 고온공정의 1차 레지스트패턴의 프로파일을 완화시킨 다음, 2차 레지스트를 도포하는 것을 특징으로 하는 반도체소자 제조방법.The method of claim 1, wherein after forming the primary resist pattern, the profile of the primary resist pattern in a high temperature process is relaxed, and then a secondary resist is applied. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930011364A 1993-06-22 1993-06-22 Semiconductor device manufacturing method KR950001925A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930011364A KR950001925A (en) 1993-06-22 1993-06-22 Semiconductor device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930011364A KR950001925A (en) 1993-06-22 1993-06-22 Semiconductor device manufacturing method

Publications (1)

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KR950001925A true KR950001925A (en) 1995-01-04

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930011364A KR950001925A (en) 1993-06-22 1993-06-22 Semiconductor device manufacturing method

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KR (1) KR950001925A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970008403A (en) * 1995-07-10 1997-02-24 김주용 Insulation Planarization Method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970008403A (en) * 1995-07-10 1997-02-24 김주용 Insulation Planarization Method

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