JPS6343349A - Multilayer thin-film interconnection - Google Patents

Multilayer thin-film interconnection

Info

Publication number
JPS6343349A
JPS6343349A JP18712286A JP18712286A JPS6343349A JP S6343349 A JPS6343349 A JP S6343349A JP 18712286 A JP18712286 A JP 18712286A JP 18712286 A JP18712286 A JP 18712286A JP S6343349 A JPS6343349 A JP S6343349A
Authority
JP
Japan
Prior art keywords
layer
film
deposited
hole
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18712286A
Other languages
Japanese (ja)
Other versions
JP2511892B2 (en
Inventor
Tsutomu Fujita
Takao Kakiuchi
Shoichi Tanimura
Hiroshi Yamamoto
Kosaku Yano
Original Assignee
Matsushita Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd filed Critical Matsushita Electric Ind Co Ltd
Priority to JP61187122A priority Critical patent/JP2511892B2/en
Publication of JPS6343349A publication Critical patent/JPS6343349A/en
Application granted granted Critical
Publication of JP2511892B2 publication Critical patent/JP2511892B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE: To reduce inter-layer contact resistance, and to shorten the wiring delay time by using a multilayer film, in which Al is employed as one layer in a wiring layer and the one layer and high melting-point metallic layers are deposited alternately, and forming a wiring layer as the next layer through a layer insulating film.
CONSTITUTION: A CVD-SiO2 film is deposited on the surface of a semiconductor substrate 1, to which various structure required is manufactured completely, as a layer insulating film 2, a contact-hole is shaped, and Ti films 3a and Al.Si films 3b are each deposited continuously through a sputtering method in the same vacuum in three layers and two layers. The pattern of Ti/Al.Si/Ti/AlWSi/ Ti multilayer film is formed, thus shaping a wiring layer 3. An SiO2 film is deposited as a layer insulating film 4 through a plasma CVD method, an inter- layer contact hole 5 is shaped, and a metal is deposited selectively only in the hole 5, and used as a contact-hole burying material 6. Lastly, a wiring layer 7 and a surface protective film 12 are manufactured respectively through the same method as the wiring layer 3 and the layer insulating film 4.
COPYRIGHT: (C)1988,JPO&Japio
JP61187122A 1986-08-08 1986-08-08 Multilayer thin film wiring and method for forming the same Expired - Fee Related JP2511892B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61187122A JP2511892B2 (en) 1986-08-08 1986-08-08 Multilayer thin film wiring and method for forming the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61187122A JP2511892B2 (en) 1986-08-08 1986-08-08 Multilayer thin film wiring and method for forming the same

Publications (2)

Publication Number Publication Date
JPS6343349A true JPS6343349A (en) 1988-02-24
JP2511892B2 JP2511892B2 (en) 1996-07-03

Family

ID=16200496

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61187122A Expired - Fee Related JP2511892B2 (en) 1986-08-08 1986-08-08 Multilayer thin film wiring and method for forming the same

Country Status (1)

Country Link
JP (1) JP2511892B2 (en)

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63314851A (en) * 1987-06-17 1988-12-22 Nec Corp Semiconductor device
JPS648645A (en) * 1987-06-30 1989-01-12 Nec Corp Semiconductor integrated circuit
JPH01255250A (en) * 1988-04-05 1989-10-12 Fujitsu Ltd Forming method for multilayer interconnection
JPH0235753A (en) * 1988-07-26 1990-02-06 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPH02181920A (en) * 1989-01-09 1990-07-16 Hitachi Ltd Semiconductor integrated circuit device
JPH02278827A (en) * 1989-04-20 1990-11-15 Nec Corp Wiring structure of semiconductor integrated circuit device and its formation
JPH039522A (en) * 1989-06-07 1991-01-17 Nec Corp Manufacture of semiconductor device
JPH03116932A (en) * 1989-09-29 1991-05-17 Sharp Corp Formation of multilayer wiring
JPH03129755A (en) * 1989-07-14 1991-06-03 Hitachi Ltd Semiconductor device and manufacture thereof
US5128744A (en) * 1988-09-12 1992-07-07 Hitachi, Ltd. Semiconductor integrated circuit and method of manufacturing same
JPH0594990A (en) * 1991-10-01 1993-04-16 Nec Corp Manufacture of multilayer interconnection
JPH05251567A (en) * 1992-03-09 1993-09-28 Nec Corp Semiconductor device
JPH09298198A (en) * 1996-05-02 1997-11-18 Nec Corp Semiconductor device
US5877082A (en) * 1996-06-14 1999-03-02 Nec Corporation Method of manufacturing semiconductor device without plasma damage
JP2009044194A (en) * 1994-04-28 2009-02-26 Xerox Corp Thin film structure having multilayer metal line
JP2010141144A (en) 2008-12-11 2010-06-24 Cree Inc Metallized structure for high electric power micro electronic device
US9024327B2 (en) 2007-12-14 2015-05-05 Cree, Inc. Metallization structure for high power microelectronic devices

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5950544A (en) * 1982-09-17 1984-03-23 Hitachi Ltd Formation of multi-layer wiring
JPS59202666A (en) * 1983-05-04 1984-11-16 Hitachi Ltd Aluminum alloy wiring
JPS6186943U (en) * 1984-11-13 1986-06-07

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5950544A (en) * 1982-09-17 1984-03-23 Hitachi Ltd Formation of multi-layer wiring
JPS59202666A (en) * 1983-05-04 1984-11-16 Hitachi Ltd Aluminum alloy wiring
JPS6186943U (en) * 1984-11-13 1986-06-07

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63314851A (en) * 1987-06-17 1988-12-22 Nec Corp Semiconductor device
JPS648645A (en) * 1987-06-30 1989-01-12 Nec Corp Semiconductor integrated circuit
JPH01255250A (en) * 1988-04-05 1989-10-12 Fujitsu Ltd Forming method for multilayer interconnection
JPH0235753A (en) * 1988-07-26 1990-02-06 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
US5128744A (en) * 1988-09-12 1992-07-07 Hitachi, Ltd. Semiconductor integrated circuit and method of manufacturing same
JPH02181920A (en) * 1989-01-09 1990-07-16 Hitachi Ltd Semiconductor integrated circuit device
JPH02278827A (en) * 1989-04-20 1990-11-15 Nec Corp Wiring structure of semiconductor integrated circuit device and its formation
JPH039522A (en) * 1989-06-07 1991-01-17 Nec Corp Manufacture of semiconductor device
JPH03129755A (en) * 1989-07-14 1991-06-03 Hitachi Ltd Semiconductor device and manufacture thereof
JPH03116932A (en) * 1989-09-29 1991-05-17 Sharp Corp Formation of multilayer wiring
JPH0594990A (en) * 1991-10-01 1993-04-16 Nec Corp Manufacture of multilayer interconnection
JPH05251567A (en) * 1992-03-09 1993-09-28 Nec Corp Semiconductor device
JP2009044194A (en) * 1994-04-28 2009-02-26 Xerox Corp Thin film structure having multilayer metal line
JPH09298198A (en) * 1996-05-02 1997-11-18 Nec Corp Semiconductor device
US5877082A (en) * 1996-06-14 1999-03-02 Nec Corporation Method of manufacturing semiconductor device without plasma damage
US9024327B2 (en) 2007-12-14 2015-05-05 Cree, Inc. Metallization structure for high power microelectronic devices
JP2010141144A (en) 2008-12-11 2010-06-24 Cree Inc Metallized structure for high electric power micro electronic device

Also Published As

Publication number Publication date
JP2511892B2 (en) 1996-07-03

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees