JPS6343349A - Multilayer thin-film interconnection - Google Patents
Multilayer thin-film interconnectionInfo
- Publication number
- JPS6343349A JPS6343349A JP18712286A JP18712286A JPS6343349A JP S6343349 A JPS6343349 A JP S6343349A JP 18712286 A JP18712286 A JP 18712286A JP 18712286 A JP18712286 A JP 18712286A JP S6343349 A JPS6343349 A JP S6343349A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- wiring
- deposited
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims description 20
- 239000010410 layer Substances 0.000 claims abstract description 67
- 239000011229 interlayer Substances 0.000 claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- 239000010408 film Substances 0.000 claims description 54
- 238000002844 melting Methods 0.000 claims description 15
- 230000008018 melting Effects 0.000 claims description 14
- 229910001092 metal group alloy Inorganic materials 0.000 claims description 8
- 229910000838 Al alloy Inorganic materials 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 17
- 238000000034 method Methods 0.000 abstract description 12
- 239000004065 semiconductor Substances 0.000 abstract description 10
- 238000004544 sputter deposition Methods 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 4
- 230000001681 protective effect Effects 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 3
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 229910018125 Al-Si Inorganic materials 0.000 abstract 1
- 229910018520 Al—Si Inorganic materials 0.000 abstract 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910045601 alloy Inorganic materials 0.000 description 18
- 239000000956 alloy Substances 0.000 description 17
- 238000000151 deposition Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910000510 noble metal Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 235000013527 bean curd Nutrition 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002222 fluorine compounds Chemical class 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910001512 metal fluoride Inorganic materials 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置等において用いられる多層薄膜配
線に関するものであり、特に、層間コンタクト抵抗およ
び配線抵抗が低い多層薄膜配線に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to multilayer thin film interconnects used in semiconductor devices and the like, and particularly relates to multilayer thin film interconnects with low interlayer contact resistance and low interconnect resistance.
従来の技術
従来、半導体装置における多層薄膜配線は、（１）Ａｌ
もしくはＭ合金、（２）貴金属もしくは貴金属合金
、（■高融点金属もしくは高融点金属合金、（４）多結
晶シリコンなどの材料を単独で用いるかもしくは複数組
み合わせて形成されていた。Conventional technology Conventionally, multilayer thin film wiring in semiconductor devices is made of (1) Al
Or M alloy, (2) noble metal or noble metal alloy, (■ high melting point metal or high melting point metal alloy, (4) polycrystalline silicon, etc. materials were used alone or in combination.
発明が解決しようとする問題点
Ａｌ もしくはＡＩ 合金は大気中で容易に強固なＡ
１２ｏ３ 絶縁層をその表面に形成するため、それを最
上層以外の配線層の材料として用いる場合、次層との層
間コンタクト抵抗を低くするためには、次層の配線材料
もしくはコンタクト孔埋込み材料の堆積の直前にたとえ
ばＡｒ イオンによるスパッタを行ない表面Ａ１２ｏ
３層を除去する工程を追加する必要があった。しかも、
今後半導体装置の微細化が進むにつれて、コンタクトホ
ール側壁からスパッタされた物質の両付着などの現象に
より、この様な方法で層間コンタクト抵抗を十分に抵く
するとこが困難になることに加え、スパッタダメージに
よって半導体装置の電気特性の劣化も大きくなる。Problems to be Solved by the Invention Al or AI alloys easily become strong in the atmosphere.
12o3 When an insulating layer is formed on the surface and is used as a material for a wiring layer other than the top layer, in order to lower the interlayer contact resistance with the next layer, it is necessary to use the wiring material of the next layer or the contact hole filling material. Immediately before the deposition, sputtering using Ar ions, for example, is performed to form the surface A12o.
It was necessary to add a step to remove three layers. Moreover,
As the miniaturization of semiconductor devices progresses in the future, it will become difficult to sufficiently reduce the interlayer contact resistance using this method due to phenomena such as the adhesion of materials sputtered from the sidewalls of contact holes. The damage also increases the deterioration of the electrical characteristics of the semiconductor device.
一方、前記（勢〜（４）の材料を用いた場合には上記の
様なＡｌもしくはＡＩ 合金を用いた場合の間眺点は解
決されるが、それらの）材料はＡｌ、Ａ１合金に比較し
て高い抵抗率を持つため、配線抵抗の増加および配線遅
延時間の増大の問題が発生した。On the other hand, when using the materials listed in (4) above, the problem with using Al or AI alloys as described above is solved, but these materials are compared to Al and Al alloys. Since the wire has a high resistivity, problems such as an increase in wiring resistance and an increase in wiring delay time have arisen.
問題点全解決するための手段
本発明の多層薄膜配線は、最上層を除く配線層の内の少
くとも一層はＡｌもしくはＡ１合金よりなる第１層と高
融点金属もしくは高融点金属合金よりなる第２層とをそ
れぞれ一層以上最上層に第２層がくる様に交互に堆積し
た多層膜を用いて形成される。続いて必要位置に層間コ
ンタクト孔を形成した層間絶縁膜をその上に被覆した後
かもしくはさらにコンタクト孔埋込み材料の堆積を行な
った後に第二の金属薄膜を堆積し次層の配線層を形成す
る。Means for Solving All Problems In the multilayer thin film wiring of the present invention, at least one of the wiring layers except the top layer includes a first layer made of Al or an A1 alloy and a first layer made of a high melting point metal or a high melting point metal alloy. It is formed using a multilayer film in which two or more layers are alternately deposited such that the second layer is the top layer. Subsequently, after coating the interlayer insulating film with interlayer contact holes formed at necessary positions, or after depositing a contact hole filling material, a second metal thin film is deposited to form the next wiring layer. .
作 用
高融点金属もしくは高融点金属合金層を表面に持つ多層
膜の表面には、Ａｌ、ｋｅ 合金の場合の＃２０３の
様な強固な絶縁膜層が容易に形成されることはない。従
ってＡｒスパッタ等の工程を追加することなく次層の金
属膜の堆積を行っても低い層間コンタクト抵抗を得るこ
とができる。しかも、高１散点金属、高融点金属合金層
は多層膜全体の膜厚に比してはるかに薄くしても上記の
作用は得られるため、多層膜の抵抗率をＡＩ、Ａ１合合
金膜それと同程度に寸で沃＜シ、それを用いて作製した
配線の抵抗をＭ、Ｍ合金を用いて作製した場合と同程度
に１で低くして、配属遅延時間を短くすることができる
。Function: On the surface of a multilayer film having a high melting point metal or high melting point metal alloy layer on the surface, a strong insulating film layer like #203 in the case of Al, ke alloy is not easily formed. Therefore, low interlayer contact resistance can be obtained even if the next layer of metal film is deposited without adding a process such as Ar sputtering. Moreover, the above effect can be obtained even if the high-1 dissipation point metal or high-melting point metal alloy layer is made much thinner than the thickness of the entire multilayer film, so the resistivity of the multilayer film can be reduced by the AI or A1 alloy film. The resistance of wiring made using it can be made as low as 1 to the same extent as when made using M and M alloys, and the placement delay time can be shortened.
実施例
以下、図面に基づいて本発明について更に詳しく説明す
る。EXAMPLES The present invention will be explained in more detail below based on the drawings.
第１図は本発明にかかる多層薄膜配線の一実施例の部分
拡大断面図を示す。図では省略されているが半導体基板
１は半導体装置として必要な各種構造のほとんどを含ん
でいる。ただし配線については一部のみしか含んでいな
い。第１層間絶縁膜２には熱酸化膜％ＣＶ Ｄ Ｓ
１０２膜（ＨＴ○、ＮＳＧ。FIG. 1 shows a partially enlarged sectional view of an embodiment of multilayer thin film wiring according to the present invention. Although not shown in the figure, the semiconductor substrate 1 includes most of the various structures necessary for a semiconductor device. However, only part of the wiring is included. The first interlayer insulating film 2 has a thermal oxide film %CV D S
102 membrane (HT○, NSG.
Ｐ ＳＧ 、ＢＰＳＧ等）、ＣＶ Ｄ −Ｓｉ３Ｎ４膜
、プラズマＳ ｉ０２ ｔプラズマＳｉＮ 膜等を使用
し、やはり図では省略されているが、必要な位置にコン
タクト孔を形成する。第１配線層３および第２配線層７
を構成するＴｉ 膜：ｐａ、７ａ、Ａｌ−５ｉ膜ｓｂ、
７ｂは真空蒸着法、スパッタ法、ＣＶＤ法などによって
堆積する。それぞれの膜厚は、たとえばＡｌ−３ｉが４
６０ ｎｍ、Ｔｉが３０ｎｍ程度である。本例で（佳い
ずれの配線層にもＴｉ ／Ａｌ −３ｉ ／Ｔｉ ／ｌ
’Ｊ・Ｓｔ／Ｔｉの５層膜を使用したが、当然、第１配
線層３にＴｉ、／Ａｌ−５ｉ（１５Ｊ！・Ｓｉ上にＴｉ
を堆積する）に２層膜を使用するのみで、第２配線層７
には通常のＡｌ−８ｉ合金膜を使用した場合においても
層間コンタクト抵抗および配線抵抗が低い多層薄膜配線
を得ることができる。しかし本例の様な多層膜を利用す
ることによって、エレクトロマイグレーションによる断
線の発生や熱処理中のヒーロック成長によるリークの発
生を防止することも可能になる。また、Ａｌ−３ｉ合金
膜のかわりに純Ａｌ膜やＡｌ−８ｉ−Ｃｕ。PSG, BPSG, etc.), CVD-Si3N4 film, plasma Si02t plasma SiN film, etc., and contact holes are formed at required positions, although these are also omitted in the figure. First wiring layer 3 and second wiring layer 7
Ti film constituting: pa, 7a, Al-5i film sb,
The layer 7b is deposited by vacuum evaporation, sputtering, CVD, or the like. The thickness of each film is, for example, 4 for Al-3i.
60 nm, and Ti is about 30 nm. In this example, Ti /Al -3i /Ti /l is used in any wiring layer.
'A five-layer film of J.St/Ti was used, but of course Ti was used on the first wiring layer 3, and Ti/Al-5i (15J!/Ti on Si) was used.
By using only a two-layer film for the second wiring layer 7
Even when a normal Al-8i alloy film is used, a multilayer thin film wiring with low interlayer contact resistance and low wiring resistance can be obtained. However, by using a multilayer film like the one in this example, it is also possible to prevent wire breakage due to electromigration and leakage due to heelock growth during heat treatment. Also, instead of the Al-3i alloy film, a pure Al film or Al-8i-Cu is used.
Ａ４・５ｉ−Ｔｔなどの合金膜を用いても、Ｔｉ膜のか
わりにＭｏ、Ｗなどの他の高融点合金膜やＴ Ｉ Ｓ
１２ ｔ Ｔ ｉＮなどの高融点金属合金膜を用いても
同様の効果を得ることができる。第２層間絶縁膜４およ
び表面保護膜１２にはＬＴＯ，ＰＳＧ、ＢＰＳＧ、プラ
ズマＳ １０２ ｔプラズマＳｉＮなどの低温で堆積で
きる絶縁膜を使用する。コンタクト孔埋込み材料６には
、たとえば選択ＣＶＤ法によるｗｌ、バイアススパッタ
法によるＡＩまたはＭｏ膜などを使用する。Even if an alloy film such as A4/5i-Tt is used, other high melting point alloy films such as Mo or W or TIS are used instead of the Ti film.
A similar effect can be obtained by using a high melting point metal alloy film such as 12 t TiN. For the second interlayer insulating film 4 and the surface protection film 12, an insulating film that can be deposited at a low temperature, such as LTO, PSG, BPSG, or plasma S102t plasma SiN, is used. As the contact hole filling material 6, for example, wl formed by selective CVD, AI or Mo film formed by bias sputtering, etc. is used.
なお、この埋込み材料は本例の様にコンタクト孔のアス
ペクト比が高い場合は必要だが、低い場合には必ずしも
必要ではない。Note that this filling material is necessary when the aspect ratio of the contact hole is high as in this example, but is not necessarily necessary when the aspect ratio is low.
以上の様な構成の多層薄膜配線は例えば次の様にして作
成される。すなわちまず、半導体装置として必要な各種
構造の作製を既に終えた半導体基板１の表面に第１層間
絶縁膜２としてＣＶＤ−３１０２膜を堆積し、必要な位
置にコンタクトホールを形成し必要ならばコンタクト埋
込材料を堆積した後にＴｉ膜３ａおよびＡｌ−８ｉ膜３
ｂをそれぞれ３層および２層、同一真空中で連続的にス
パッタ法によって堆積する（第２図ａ参照）。次にＴｉ
／Ａｌ −Ｓｔ ／Ｔｉ ／ＪＪ−Ｓｉ ／Ｔｉ多層
膜のパターンをフォトレジスト法＄・よび乾式蝕刻法に
よって形成し、第１配線層３とする。続いてプラズマＣ
ＶＤ法で５ＩＯｌを第１層間絶縁膜４を堆積し、フォト
レジスト法および乾式蝕刻法によって第１層間コンタク
ト孔５を形成する（第２図す参照）。次に減圧ＣＶＤ法
によってタングステン等の金属をコンタクト孔の内部に
のみ選択的に堆積し、コンタクト孔埋込み材料６とする
（第２図Ｃ参照）この工程において、第１配線層３が従
来のＡ１合金であった場合には表面Ａ４２０３層の存在
によって選択性が悪化する可能性があり、まだ、たとえ
ば金属フッ化物ガスも用いたＣＶＤを行なった場合、界
面にＡ１１１！フツ化物が残留する問題があるが本発明
の構造においては、配線層最上部の高融点金属もしくは
高融点金属合金の種類を適当に選定することにより、そ
の様な問題の発生を防止することができ、その効果が犬
である。最後に第２配線層７および表面保護膜１２をそ
れぞれ第１配線層３および第２層間絶縁膜と同様の方法
にて作製する（第２図Ｃ参照）。The multilayer thin film wiring having the above-mentioned configuration is produced, for example, in the following manner. That is, first, a CVD-3102 film is deposited as a first interlayer insulating film 2 on the surface of a semiconductor substrate 1 on which various structures necessary for a semiconductor device have already been fabricated, and contact holes are formed at required positions to make contacts if necessary. After depositing the embedding material, a Ti film 3a and an Al-8i film 3 are deposited.
3 and 2 layers of each of B are deposited successively in the same vacuum by sputtering (see FIG. 2a). Next, Ti
A pattern of /Al-St/Ti/JJ-Si/Ti multilayer film is formed by a photoresist method and a dry etching method to form a first wiring layer 3. Then plasma C
A first interlayer insulating film 4 of 5IOl is deposited by a VD method, and a first interlayer contact hole 5 is formed by a photoresist method and a dry etching method (see FIG. 2). Next, a metal such as tungsten is selectively deposited only inside the contact hole using a low pressure CVD method to form a contact hole filling material 6 (see FIG. 2C). In the case of an alloy, the selectivity may deteriorate due to the presence of the A4203 layer on the surface, and if CVD is also performed using metal fluoride gas, for example, A111! Although there is a problem that fluorides remain, in the structure of the present invention, such a problem can be prevented by appropriately selecting the type of high melting point metal or high melting point metal alloy at the top of the wiring layer. You can, and the effect is a dog. Finally, the second wiring layer 7 and the surface protection film 12 are formed in the same manner as the first wiring layer 3 and the second interlayer insulating film, respectively (see FIG. 2C).
第３図は本発明にかかる多層薄膜配線の第２の実施例の
部分拡大断面図を示す。ここでは第１図の例の場合より
もさらに工程を進めて３層多層配線構造をとっている。FIG. 3 shows a partially enlarged sectional view of a second embodiment of the multilayer thin film wiring according to the present invention. Here, the process is further advanced than in the case of the example shown in FIG. 1, and a three-layer multilayer wiring structure is obtained.
轟然のことながら、さらに配線店数の多い構造において
本発明を実施することも可能である。Of course, it is also possible to implement the present invention in a structure with an even greater number of wiring outlets.
また第３図においては第１配線層３／は多結晶Ｓｉ膜３
’ａ上にＣＶＤ法によってタングステン膜３′ｂを堆積
した材料を用いて作製している。この様に本発明を実施
する際には、すべての配線層にＡＩ もしくはＡ１合金
層と高融点金属もしくは高融点金属合金層との多層膜を
使用する必要はないのであって、目的に応じて他の材料
を使用することが可能である。In addition, in FIG. 3, the first wiring layer 3/ is a polycrystalline Si film 3.
It is fabricated using a material in which a tungsten film 3'b is deposited on 'a by CVD. In this manner, when carrying out the present invention, it is not necessary to use a multilayer film of an AI or A1 alloy layer and a high melting point metal or high melting point metal alloy layer for all wiring layers, and depending on the purpose, It is possible to use other materials.
最後に第４図に従来の技術を用いて２層多層配線を作製
した場合の実施例の部分拡大断面図を示す。第１配線層
３“にＡｌａＳＬ膜を用いており、コンタクト孔埋込み
材料堆積前にへτスパッタ処理を行ってはいるのだが、
第１層間コンタクト孔６が微細で高アスペクト比を持っ
ているためＡｅ−Ｓｉ表面のＡ４２０２層除去が完全に
は行えず、層間コンタクト抵抗が高くなっている。Finally, FIG. 4 shows a partially enlarged cross-sectional view of an example in which a two-layer multilayer interconnection is fabricated using a conventional technique. Although the AlaSL film is used for the first wiring layer 3'' and τ sputtering is performed before depositing the contact hole filling material,
Since the first interlayer contact hole 6 is minute and has a high aspect ratio, the A4202 layer on the Ae-Si surface cannot be completely removed, resulting in high interlayer contact resistance.
発明の効果
本発明による多層薄膜配線は以上の様な構成よりなるも
のであシ、配線層を形成する金属薄膜の表面にはＭ合金
の場合のＡｌ２Ｏ３の様な強固な絶縁膜が形成されるこ
とがないため、 Ａｒスバフタなどの処理を行わなくて
も層間コンタクト抵抗を低くすることが可能である。ま
た、配線層はその厚さの大部分をＡｌ もしくはＡ１
合金がしめる多層金属薄膜によって作製するため、配線
抵抗を従来のＡ１合金配線とほぼ同一の低い値に抑える
ことができる。従って本発明にかかる多層薄膜配線は極
めヤ産業上価値の高いものである。Effects of the Invention The multilayer thin film wiring according to the present invention has the above-mentioned structure, and a strong insulating film such as Al2O3 in the case of M alloy is formed on the surface of the metal thin film forming the wiring layer. Therefore, it is possible to lower the interlayer contact resistance without performing a process such as Ar buffing. In addition, most of the thickness of the wiring layer is made of Al or A1.
Since it is manufactured using a multilayer metal thin film made of an alloy, the wiring resistance can be suppressed to a low value that is almost the same as that of conventional A1 alloy wiring. Therefore, the multilayer thin film wiring according to the present invention is of extremely high industrial value.
第１図は本発明にかかる多層薄膜配線の一実施例の部分
拡大断面図、第２図は同多層薄膜配線を製造する工程の
一部を示す部分拡大断面図を、第３図は本発明の多層薄
膜配線の第２の実施例の部分拡大断面図、第４図は従来
の多層薄膜配線の一例の部分拡大断面図である。
１・・・・・・半導体基板、２・・・・・・第１層間絶
縁膜、３゜３′、３″−・・・・・第１配線層、３−１
・・・・・・Ｔｉ膜、３−２゜３Ｌ１・−・・・・Ａｌ
・Ｓｉ［，３′−１・・・・・・多結晶Ｓｉ膜。
３／−２・・・・・・ＣＶＤタングステン膜、４・・・
・・・第２，１間絶縁膜、６・・・・・・第１層間コン
タクト孔、６，１０・・・・・・コンタクト孔埋込み材
料、７．７′−一第２配線層、７−１・・・・・・Ｔｉ
膜、７−２．７”−１・・・・・・Ｍ・Ｓｉ膜、８・・
・・・・第２層間絶縁膜、９・・・・・・第２層間コン
タクト孔、１１・・・・・・第３配線層、１１−１・・
・・・・Ｔｉ膜、１１−２・山・・ＡｌｌｌＳｉ膜、１
２・・・・・・表面保護膜。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名１−
−−４町丁、１枚
？−名１冴開Ｖ昧朕
３− 不１配線量
３６．１ａ−−−−Ｔｉ 騰
５−−−４（４ｒ：Ｉコ＞ｆ７１−Ｅ
ｒ−−−、ンク２と島１５八と１■斗
７− 茶２鵠憾１
ｆ’１−−−ｆｚ順千遵朕
ｔ、ＩＱ−−・ｊンタへ）乙；テＪピ！と不・）ざ＋７
ｂ、 １１ｂ−Ａ４５μ裏
８−第３，４間馳′Ｐｋ換
派
ｄ −ロFIG. 1 is a partially enlarged sectional view of an embodiment of a multilayer thin film wiring according to the present invention, FIG. 2 is a partially enlarged sectional view showing a part of the process for manufacturing the same multilayer thin film wiring, and FIG. FIG. 4 is a partial enlarged sectional view of an example of a conventional multilayer thin film wiring. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... First interlayer insulating film, 3°3', 3''-... First wiring layer, 3-1
...Ti film, 3-2゜3L1...Al
-Si[,3'-1... Polycrystalline Si film. 3/-2...CVD tungsten film, 4...
...Second and first interlayer insulating film, 6...First interlayer contact hole, 6,10...Contact hole filling material, 7.7'-1 second wiring layer, 7 -1...Ti
Membrane, 7-2.7"-1... M.Si film, 8...
...Second interlayer insulating film, 9...Second interlayer contact hole, 11...Third wiring layer, 11-1...
...Ti film, 11-2 Mountain...AllSi film, 1
2...Surface protective film. Name of agent: Patent attorney Toshio Nakao and 1 other person1-
--4 towns, 1 piece? -Name 1 Clearance V Mechanism 3- Un1 wiring amount 36.1a----Ti rise 5---4 (4r: I > f71-E r---, Nku 2 and Island 158 and 1 ■斗7- 茶2鵠憾1 f'1---fz溭子朕t、IQ--・Junita）Otsu; TeJpi! Tofu・）za+7
b, 11b-A45μ back 8-3rd and 4th space 'Pk replacement d-ro
Claims (1)
しくは高融点金属合金よりなる第２層とをそれぞれ一層
以上、最上層に第２層がくる様交互に堆積した多層膜を
用いて形成した薄膜金続配線層上に、必要な位置に層間
コンタクト孔を形成した層間絶縁膜層を形成し、第２の
薄膜金属配線層を形成した構造を有してなる多層薄膜配
線。Formed using a multilayer film in which a first layer made of Al or an Al alloy and a second layer made of a high melting point metal or a high melting point metal alloy are deposited alternately such that the second layer is the top layer. A multilayer thin film wiring having a structure in which an interlayer insulating film layer with interlayer contact holes formed at required positions is formed on a thin film metal wiring layer, and a second thin film metal wiring layer is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61187122A JP2511892B2 (en) | 1986-08-08 | 1986-08-08 | Multilayer thin film wiring and method for forming the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61187122A JP2511892B2 (en) | 1986-08-08 | 1986-08-08 | Multilayer thin film wiring and method for forming the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6343349A true JPS6343349A (en) | 1988-02-24 |
| JP2511892B2 JP2511892B2 (en) | 1996-07-03 |
Family
ID=16200496
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61187122A Expired - Fee Related JP2511892B2 (en) | 1986-08-08 | 1986-08-08 | Multilayer thin film wiring and method for forming the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2511892B2 (en) |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63314851A (en) * | 1987-06-17 | 1988-12-22 | Nec Corp | Semiconductor device |
| JPS648645A (en) * | 1987-06-30 | 1989-01-12 | Nec Corp | Semiconductor integrated circuit |
| JPH01255250A (en) * | 1988-04-05 | 1989-10-12 | Fujitsu Ltd | Forming method for multilayer interconnection |
| JPH0235753A (en) * | 1988-07-26 | 1990-02-06 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH02181920A (en) * | 1989-01-09 | 1990-07-16 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPH02278827A (en) * | 1989-04-20 | 1990-11-15 | Nec Corp | Wiring structure of semiconductor integrated circuit device and its formation |
| JPH039522A (en) * | 1989-06-07 | 1991-01-17 | Nec Corp | Manufacture of semiconductor device |
| JPH03116932A (en) * | 1989-09-29 | 1991-05-17 | Sharp Corp | Formation of multilayer wiring |
| JPH03129755A (en) * | 1989-07-14 | 1991-06-03 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| US5128744A (en) * | 1988-09-12 | 1992-07-07 | Hitachi, Ltd. | Semiconductor integrated circuit and method of manufacturing same |
| JPH0594990A (en) * | 1991-10-01 | 1993-04-16 | Nec Corp | Manufacture of multilayer interconnection |
| JPH05251567A (en) * | 1992-03-09 | 1993-09-28 | Nec Corp | Semiconductor device |
| JPH09298198A (en) * | 1996-05-02 | 1997-11-18 | Nec Corp | Semiconductor device |
| US5877082A (en) * | 1996-06-14 | 1999-03-02 | Nec Corporation | Method of manufacturing semiconductor device without plasma damage |
| JP2009044194A (en) * | 1994-04-28 | 2009-02-26 | Xerox Corp | Thin film structure having multilayer metal line |
| JP2010141144A (en) | 2008-12-11 | 2010-06-24 | Cree Inc | Metallized structure for high electric power micro electronic device |
| US9024327B2 (en) | 2007-12-14 | 2015-05-05 | Cree, Inc. | Metallization structure for high power microelectronic devices |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5950544A (en) * | 1982-09-17 | 1984-03-23 | Hitachi Ltd | Formation of multi-layer wiring |
| JPS59202666A (en) * | 1983-05-04 | 1984-11-16 | Hitachi Ltd | Aluminum alloy wiring |
| JPS6186943U (en) * | 1984-11-13 | 1986-06-07 |
-
1986
- 1986-08-08 JP JP61187122A patent/JP2511892B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5950544A (en) * | 1982-09-17 | 1984-03-23 | Hitachi Ltd | Formation of multi-layer wiring |
| JPS59202666A (en) * | 1983-05-04 | 1984-11-16 | Hitachi Ltd | Aluminum alloy wiring |
| JPS6186943U (en) * | 1984-11-13 | 1986-06-07 |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63314851A (en) * | 1987-06-17 | 1988-12-22 | Nec Corp | Semiconductor device |
| JPS648645A (en) * | 1987-06-30 | 1989-01-12 | Nec Corp | Semiconductor integrated circuit |
| JPH01255250A (en) * | 1988-04-05 | 1989-10-12 | Fujitsu Ltd | Forming method for multilayer interconnection |
| JPH0235753A (en) * | 1988-07-26 | 1990-02-06 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| US5128744A (en) * | 1988-09-12 | 1992-07-07 | Hitachi, Ltd. | Semiconductor integrated circuit and method of manufacturing same |
| JPH02181920A (en) * | 1989-01-09 | 1990-07-16 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPH02278827A (en) * | 1989-04-20 | 1990-11-15 | Nec Corp | Wiring structure of semiconductor integrated circuit device and its formation |
| JPH039522A (en) * | 1989-06-07 | 1991-01-17 | Nec Corp | Manufacture of semiconductor device |
| JPH03129755A (en) * | 1989-07-14 | 1991-06-03 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JPH03116932A (en) * | 1989-09-29 | 1991-05-17 | Sharp Corp | Formation of multilayer wiring |
| JPH0594990A (en) * | 1991-10-01 | 1993-04-16 | Nec Corp | Manufacture of multilayer interconnection |
| JPH05251567A (en) * | 1992-03-09 | 1993-09-28 | Nec Corp | Semiconductor device |
| JP2009044194A (en) * | 1994-04-28 | 2009-02-26 | Xerox Corp | Thin film structure having multilayer metal line |
| JPH09298198A (en) * | 1996-05-02 | 1997-11-18 | Nec Corp | Semiconductor device |
| US5877082A (en) * | 1996-06-14 | 1999-03-02 | Nec Corporation | Method of manufacturing semiconductor device without plasma damage |
| US9024327B2 (en) | 2007-12-14 | 2015-05-05 | Cree, Inc. | Metallization structure for high power microelectronic devices |
| JP2010141144A (en) | 2008-12-11 | 2010-06-24 | Cree Inc | Metallized structure for high electric power micro electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2511892B2 (en) | 1996-07-03 |
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