JPH0567686A - Semiconductor device wiring - Google Patents

Abstract

PURPOSE:To provide a wiring structure where a Cu wiring layer is protected against etching damage when a through-hole is provided to an interlayer insulating film without deteriorating the lower Cu wiring layer in characteristics. CONSTITUTION:A Cu wiring is formed into a four-layered structure composed of an adhesive layer, a Cu wiring layer 6, a barrier layer 9, and an etching stopper layer 8, etching damage 16 induced when a through-hole is provided to the insulating film 9 is prevented from spreading beyond the etching stopper 8. By this setup, when a through-hole is provided to an interlayer insulating film on a wiring, the wiring can be protected against etching damage by an etching stopper layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device wiring, and more particularly to a multilayer wiring structure suitable for ULSI.

[0002]

2. Description of the Related Art Conventionally, an Al alloy has been used for semiconductor device wiring. However, in order to further reduce the wiring resistance and improve the electromigration resistance, C
It is necessary to use u or Cu alloy for the wiring.
Since Cu is a single layer and difficult to use for wiring, it is used in a laminated structure with a barrier layer or the like. As the laminated structure of Cu wiring, the Al / Cu / Al laminated structure disclosed in JP-A-63-88843 is known. However, this structure causes a problem because Al and Cu react with each other to form a high resistance intermetallic compound.

[0003]

In the conventional laminated Cu wiring, no consideration has been given to the formation of multilayer wiring, particularly the processing of the interlayer insulating film. In the conventional technique, when forming a through hole in an interlayer insulating film, the lower layer wiring itself is opened as an etching stopper by a dry etching technique.
In this case, it is difficult to avoid etching damage to the opening of the lower layer wiring. When Cu, which is suitable for lowering the resistance, is used for the wiring, the fluorocarbon-based gas used for etching the interlayer insulating film has a low vapor pressure and forms an insulative metal fluoride, which is a problem. In particular, copper fluoride is a serious problem because it is easily formed thick. A laminated structure in which a TiN protective layer is provided on a wiring layer is also known, but it is not sufficient to prevent etching damage because the protective layer cannot be made too thick. Although Al is suitable as the protective layer, Al and Cu have a problem because they easily form an intermetallic compound.

An object of the present invention is to prevent Cu from being formed during the formation of through holes in the interlayer insulating film without impairing the performance of the Cu wiring.
An object of the present invention is to provide a wiring structure that prevents etching damage to the wiring layer.

[0005]

The above object can be achieved by forming the Cu wiring into a four-layer structure including an adhesive layer, a Cu wiring layer, a barrier layer and an etching stopper layer from the substrate side.

[0006]

In the above-mentioned four-layer structure Cu wiring, there is a barrier layer between the Cu wiring and the etching stopper layer to prevent the reaction between both layers, so that the etching stopper layer is irrespective of the reactivity with Cu. The optimum material can be selected as. Therefore, when the through hole is opened in the interlayer insulating film on the wiring, etching damage on the wiring can be stopped by the etching stopper layer.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a cross-sectional view of a semiconductor device wiring according to the present invention, and FIG. 2 is a view showing a forming method thereof.

An element is formed on a part of the surface, and a TiN film 5 is formed by reactive sputtering on the Si substrate 1 covered with the thermally oxidized SiO ₂ film 2 and the CVD-SiO ₂ film 4 except the opening.
The Cu film 6 is 50 nm by 0 nm, DC magnetron sputtering method.
0 nm, TiN film 7 of 30 nm by reactive sputtering method, D
An Al film 8 having a thickness of 100 nm is sequentially formed by a C magnetron sputtering method, and the laminated film is patterned by a photolithography technique and a dry etching method to form wiring. The lower TiN film plays a role of ensuring adhesion between the insulating film and the Cu film and preventing Cu diffusion into Si, and the upper TiN film is Al
Plays a role of preventing mutual diffusion between Cu and Cu. Where Ti
Instead of N, a nitride of another metal such as ZrN or TaN or a refractory metal such as W or Mo may be used. Further, the adhesive layer and the barrier layer may be made of different materials (a).

A PSG film (9) of 500 nm is formed on this substrate by the atmospheric pressure CVD method, and a through hole having a diameter of 800 nm is formed at a required place by the photolithography technique and the dry etching method. A fluorocarbon-based etching gas is used for etching the PSG film, but Al is hardly etched by this gas, and the wiring below Al is not damaged by etching. Here, since Al only functions as an etching stopper, it suffices if it is in the through hole portion, and as shown in FIG. 3, Al other than the through hole portion may be removed. Unnecessary Al
By removing Al, the possibility that Al and Cu react to increase the resistance of the wiring is reduced, and the reliability of the wiring can be improved. This can be achieved by dry etching the surrounding Al while leaving the resist only around the through holes by the photolithography process. In this case, since it is not necessary to form an accurate pattern on the Al film, the patterning rule may be somewhat loose (b).

Further, the TiN film 11 is 50 nm thick by the reactive sputtering method, the Cu film 12 is 500 nm thick by the DC magnetron sputtering method, and the TiN film 13 is 30 nm thick by the reactive sputtering method.
m, DC Al magnetron spattering method 100
nm sequentially. Patterning this Cu wiring layer by photolithography and dry etching,
A second layer of Cu wiring is formed (c).

A PSG film 15 is formed thereon by an atmospheric pressure CVD method.
Is formed to a thickness of 500 nm, and through holes are formed at required locations by photolithography and dry etching. Here again, Al functions as an etching stopper (d).

Further, in the case of multi-layered Cu wiring, similar steps are repeated to form Cu wiring. If necessary, a glass such as a PSG film by atmospheric pressure CVD is further formed on the glass for passivation.

[0013]

According to the present invention, since there is no reaction between the Cu wiring and the etching stopper layer, the wiring performance is not impaired, and a laminated Cu wiring capable of preventing etching damage at the time of forming a through hole can be formed. .

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device wiring according to an embodiment of the present invention.

FIG. 2 is a process diagram showing a method for forming a semiconductor device wiring according to the present invention.

FIG. 3 is a sectional view of a semiconductor device wiring of another embodiment according to the present invention.

[Explanation of symbols]

1 ... p-type Si substrate, 2 ... thermal oxide SiO ₂ film, 3 ... n-type diffusion layer, 4 ... CVD-SiO ₂ film, 5, 7, 11, 13 ...
TiN film, 6, 12 ... Cu film, 8, 14 ... Al film, 9,
15 ... PSG film, 10, 16 ... Etching damage part.

Claims (5)

[Claims] 1. A thin-film multi-layered wiring in which a wiring layer and an insulating layer are sequentially laminated, wherein at least one of the wiring layers is composed of four layers of a conductive material including an adhesive layer, a conductive layer, a barrier layer and an etching stopper layer. A semiconductor wiring having the following laminated structure, wherein the conductive layer is thickest and is made of Cu or an alloy containing Cu as a main component. 2. The method for forming a semiconductor device wiring according to claim 1, wherein over-etching at the time of opening a through hole connecting the wiring layers to an interlayer insulating film remains in the etching stopper layer. 3. The adhesive layer according to claim 1, which secures the adhesiveness between the underlying insulating layer and the conductive layer, and the barrier layer which prevents mutual diffusion between the conductive layer and the etching stopper layer. Semiconductor device wiring which is a pure metal or alloy of W, Mo, Ti, Ta or Zr or a nitride of these metals. 4. The semiconductor device wiring according to claim 1, wherein the etching stopper layer is made of Al or an alloy containing Al as a main component. 5. The semiconductor device wiring according to claim 1, wherein the etching stopper layer does not exist on at least a part of the Cu wiring except the through hole opening.