JP3137719B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3137719B2 JP3137719B2 JP04084031A JP8403192A JP3137719B2 JP 3137719 B2 JP3137719 B2 JP 3137719B2 JP 04084031 A JP04084031 A JP 04084031A JP 8403192 A JP8403192 A JP 8403192A JP 3137719 B2 JP3137719 B2 JP 3137719B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- film
- wiring film
- barrier
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方法
に係り、特に、多層配線構造を有する半導体装置の配線
間同志の接続抵抗を減少し、集積回路の特性を向上させ
た半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a multilayer wiring structure, in which the connection resistance between wirings is reduced and the characteristics of an integrated circuit are improved. It relates to a manufacturing method.
【０００２】[0002]
【従来の技術】従来、多層配線構造を有する半導体装置
では、微細化、高集積化が進むにつれて、配線の信頼性
を確保することが困難となってきている。このため、前
記配線の信頼性を確保するため、種々の方法が紹介され
ている。前記配線の信頼性を向上する方法としては、例
えば、配線を形成する際に、先ず、カバレッジ特性の良
い高融点金属化合物からなるバリア用配線膜を下地にし
てから、アルミニウム等の主配線膜を形成し、この上
に、前記主配線膜より反射率が小さい高融点金属化合物
からなる反射防止用配線膜を形成する方法が知られてお
り、この三層構造を有する配線が広く使用されている。2. Description of the Related Art Conventionally, in a semiconductor device having a multilayer wiring structure, it has become difficult to secure the reliability of wiring as miniaturization and high integration progress. Therefore, various methods have been introduced to ensure the reliability of the wiring. As a method of improving the reliability of the wiring, for example, when forming the wiring, first, a base wiring film made of a high melting point metal compound having good coverage characteristics, and then a main wiring film such as aluminum There is known a method of forming and forming an anti-reflection wiring film made of a refractory metal compound having a lower reflectance than the main wiring film on this, and a wiring having this three-layer structure is widely used. .
【０００３】また、前記三層構造を有する配線からなる
多層配線構造では、当該下層配線上に、絶縁膜を介し
て、当該下層配線と同様の三層構造を有すると共に、当
該下層配線と接続する上層配線を形成している。そし
て、この多層配線構造は、一般的に、以下の方法で製造
されている。先ず、半導体基板上に、前記下層配線を形
成し、当該半導体基板上、及び下層配線上に、前記絶縁
膜を形成する。次に、前記下層配線上の絶縁膜にコンタ
クト孔を開口し、露出した下層配線の反射防止用配線膜
を除去して、この部分の主配線膜を露出する。ここで、
前記下層配線の反射防止用配線膜の除去は、当該下層配
線と前記上層配線とを接続した際に、高融点金属同志が
接触して配線間の接触抵抗が大きくなるのを避ける目的
で行う。その後、前記コンタクト孔が開口された絶縁膜
上及び露出した主配線膜上に、バリア用配線膜として、
窒化高融点金属化合物（例えば、ＴｉＮ等）を、反応性
スパッタ法により形成する。その後、前記バリア用配線
膜上に、主配線膜及び反射防止用配線膜を形成した後、
パターニング等、所望の工程を行っている。In a multilayer wiring structure composed of the wiring having a three-layer structure, the lower wiring has the same three-layer structure as the lower wiring via an insulating film, and is connected to the lower wiring. The upper wiring is formed. This multilayer wiring structure is generally manufactured by the following method. First, the lower wiring is formed on a semiconductor substrate, and the insulating film is formed on the semiconductor substrate and the lower wiring. Next, a contact hole is opened in the insulating film on the lower wiring, the antireflection wiring film of the exposed lower wiring is removed, and the main wiring film in this portion is exposed. here,
The removal of the anti-reflection wiring film of the lower wiring is performed for the purpose of avoiding an increase in contact resistance between the wirings due to contact between refractory metals when the lower wiring and the upper wiring are connected. Thereafter, on the insulating film in which the contact hole is opened and on the exposed main wiring film, as a barrier wiring film,
A nitrided high melting point metal compound (for example, TiN or the like) is formed by a reactive sputtering method. Then, after forming the main wiring film and the anti-reflection wiring film on the barrier wiring film,
A desired process such as patterning is performed.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、前記多
層配線構造は、前記コンタクト孔を開口し、次に、下層
配線の反射防止用配線膜を除去した後、反応性スパッタ
法により、露出した主配線膜上に、上層配線のバリア用
配線膜を形成している。従って、前記反応性スパッタを
行った際、前記主配線膜表面に、窒化物が形成され、こ
の部分の抵抗が非常に高くなると共に、上層と下層の配
線間の接続抵抗にバラツキが生じるという問題があっ
た。However, in the multilayer wiring structure, after opening the contact hole and removing the antireflection wiring film of the lower wiring, the exposed main wiring is formed by the reactive sputtering method. A barrier wiring film for the upper wiring is formed on the film. Therefore, when the reactive sputtering is performed, a nitride is formed on the surface of the main wiring film, and the resistance of this portion becomes extremely high, and the connection resistance between the upper and lower wirings varies. was there.
【０００５】本発明は、このような問題を解決すること
を課題とするものであり、多層配線構造を有する半導体
装置の配線間同志の接続抵抗を減少すると共に、配線間
の抵抗のバラツキを抑制し、集積回路の特性を向上させ
た半導体装置の製造方法を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to solve such a problem, and to reduce the connection resistance between wirings of a semiconductor device having a multilayer wiring structure and to suppress the variation in resistance between wirings. It is another object of the present invention to provide a method of manufacturing a semiconductor device with improved characteristics of an integrated circuit.
【０００６】[0006]
【課題を解決するための手段】この目的を達成するため
に、本発明は、窒素化合物の高融点金属であるバリア用
配線膜、主配線膜及び反射防止用配線膜を順次形成して
なる三層構造を有する下層配線と、当該下層配線上に形
成した絶縁膜と、当該絶縁膜上に、バリア用配線膜、主
配線膜及び反射防止用配線膜を順次形成してなる三層構
造を有する上層配線と、を備え、前記上層配線と下層配
線とを接続した構造を有する半導体装置の製造方法にお
いて、前記上層配線のバリア用配線膜は、前記絶縁膜上
及び露出した前記下層配線の主配線膜上に高融点金属膜
を形成した後、当該高融点金属膜に窒素を導入して形成
することを特徴とする半導体装置の製造方法を提供する
ものである。In order to achieve this object, the present invention provides a method of forming a barrier wiring film, a main wiring film and an anti-reflection wiring film, which are refractory metals of a nitrogen compound, in that order. It has a three-layer structure in which a lower wiring having a layer structure, an insulating film formed on the lower wiring, and a barrier wiring film, a main wiring film, and an antireflection wiring film are sequentially formed on the insulating film. A method of manufacturing a semiconductor device having an upper wiring and a structure in which the upper wiring and the lower wiring are connected to each other, wherein the barrier wiring film of the upper wiring is formed on the insulating film.
A method of manufacturing a semiconductor device, comprising: forming a refractory metal film on an exposed main wiring film of the lower wiring; and introducing nitrogen into the refractory metal film. .
【０００７】[0007]
【作用】本発明によれば、前記上層配線のバリア用配線
膜は、前記絶縁膜上及び露出した前記下層配線の主配線
膜上に高融点金属膜を形成した後、当該高融点金属膜に
窒素を導入して形成される。このため、前記バリア用配
線膜を形成する際に、前記下層配線の主配線膜上には、
先ず、高融点金属膜が形成される。従って、この高融点
金属膜が前記主配線膜を保護するため、当該主配線膜表
面に、窒化物が形成されることがない。このため、下層
配線と上層配線との接触抵抗を減少することができる。
さらに、前記上層配線は、部分的に高抵抗となることが
ないため、配線間の抵抗のバラツキを抑制することがで
きる。According to the present invention, the barrier wiring film of the upper wiring is a main wiring of the lower wiring exposed on the insulating film and exposed.
After forming a refractory metal film on the membrane is formed by introducing nitrogen into the high melting point metal film. For this reason, when forming the barrier wiring film, on the main wiring film of the lower layer wiring,
First, a refractory metal film is formed. Therefore, since the refractory metal film protects the main wiring film, no nitride is formed on the surface of the main wiring film. For this reason, the contact resistance between the lower wiring and the upper wiring can be reduced.
Further, since the upper wiring does not partially have a high resistance, it is possible to suppress a variation in resistance between the wirings.
【０００８】[0008]
【実施例】次に、本発明に係る実施例について、図面を
参照して説明する。図１ないし図５は、本発明の実施例
に係る半導体装置の製造工程の一部を示す断面図であ
る。図１に示す工程では、半導体基板１上に、絶縁膜２
を形成する。次いで、前記絶縁膜２上に、膜厚が１００
０Å程度の高融点金属化合物（ＴｉＮ）からなるバリア
用配線膜３を形成する。次いで、前記バリア用配線膜３
上に、膜厚が９０００Å程度のＡｌ合金からなる主配線
膜４を形成する。さらに、前記主配線膜４上に、Ａｌよ
り反射率の低い高融点金属化合物（ＴｉＮ）からなる反
射防止用配線膜５を、３００Å程度の膜厚で形成する。
次いで、前記バリア用配線膜３、主配線膜４及び反射防
止用配線膜５をパターニングして、前記三層構造を有す
る下層配線６を形成する。Next, embodiments of the present invention will be described with reference to the drawings. 1 to 5 are cross-sectional views showing a part of a manufacturing process of a semiconductor device according to an embodiment of the present invention. In the step shown in FIG. 1, an insulating film 2
To form Next, a film thickness of 100
A barrier wiring film 3 made of a metal compound (TiN) having a high melting point of about 0 ° is formed. Next, the barrier wiring film 3
A main wiring film 4 made of an Al alloy having a thickness of about 9000 ° is formed thereon. Further, on the main wiring film 4, an antireflection wiring film 5 made of a refractory metal compound (TiN) having a lower reflectance than Al is formed to a thickness of about 300 °.
Next, the barrier wiring film 3, the main wiring film 4, and the antireflection wiring film 5 are patterned to form the lower wiring 6 having the three-layer structure.
【０００９】次に、図２に示す工程では、図１に示す工
程で得た下層配線６及び絶縁膜２上に、膜厚が７０００
Å程度の層間絶縁膜７を形成する。次いで、図３に示す
工程では、図２に示す工程で、下層配線６上に形成した
層間絶縁膜７に、選択的にコンタクト孔８を開口し、こ
の部分の反射防止用配線５を露出した後、これを選択的
に除去し、主配線膜４を露出する。Next, in the step shown in FIG. 2, a thickness of 7000 is formed on the lower wiring 6 and the insulating film 2 obtained in the step shown in FIG.
An interlayer insulating film 7 of about Å is formed. Next, in the step shown in FIG. 3, a contact hole 8 is selectively opened in the interlayer insulating film 7 formed on the lower layer wiring 6 in the step shown in FIG. 2, and the antireflection wiring 5 in this portion is exposed. Thereafter, this is selectively removed to expose the main wiring film 4.
【００１０】次に、図４に示す工程では、図３に示す工
程で露出した主配線膜４上、及び層間絶縁膜７上に、ス
パッタ法により、高融点金属膜（Ｔｉ）を、３００Å程
度の膜厚で形成する。その後、前記高融点金属膜に、パ
ワー＝５００Ｗ、真空度＝９Ｔｏｒｒ、Ｎ2 量＝３ｌ／
ｍｉｎ、の条件で、５〜３０分間、好ましくは、１０分
間程度、Ｎ2 をプラズマ照射する。このようにして、前
記高融点金属膜に、Ｎ 2 を導入し、高融点金属化合物
（ＴｉＮ）からなるバリア用配線膜９を形成する。ここ
で、前記方法では、バリア用配線膜９の形成時に、前記
主配線膜４を前記高融点金属膜により保護することがで
きる。従って、前記主配線膜４表面に、窒化物が形成さ
れることがない。尚、この工程で得たバリア用配線膜９
は、前記下層配線６のバリア用配線膜３に比べ、その厚
さ方向に対するＴｉとＮの組成非が若干変化している
が、バリア用配線としての機能は、十分に備えている。Next, in the step shown in FIG. 4, the process shown in FIG.
On the main wiring film 4 and the interlayer insulating film 7
A refractory metal film (Ti) is deposited by the
It is formed with a film thickness of a degree. After that, the refractory metal film is
Work = 500W, degree of vacuum = 9Torr, NTwoVolume = 3 l /
min, 5 to 30 minutes, preferably 10 minutes
Around, NTwoIs irradiated with plasma. In this way, before
The refractory metal film is coated with N TwoIntroduction of high melting point metal compounds
A barrier wiring film 9 made of (TiN) is formed. here
In the method, when the barrier wiring film 9 is formed,
The main wiring film 4 can be protected by the refractory metal film.
Wear. Therefore, nitride is not formed on the surface of the main wiring film 4.
Never be. The barrier wiring film 9 obtained in this step
Is thicker than the barrier wiring film 3 of the lower wiring 6.
The composition of Ti and N is slightly changed
However, the function as a barrier wiring is sufficiently provided.
【００１１】次いで、図５に示す工程では、図４に示す
工程で得たバリア用配線膜９上に、膜厚が９０００Å程
度のＡｌ合金からなる主配線膜１０を形成する。さら
に、前記主配線膜１０上に、Ａｌより反射率の低い高融
点金属化合物（ＴｉＮ）からなる反射防止用配線膜１１
を、３００Å程度の膜厚で形成する。次いで、前記バリ
ア用配線膜９、主配線膜１０及び反射防止用配線膜１１
に、所望のパターニングを行い、前記三層構造を有する
上層配線１２を形成する。Next, in a step shown in FIG. 5, a main wiring film 10 made of an Al alloy having a thickness of about 9000 ° is formed on the barrier wiring film 9 obtained in the step shown in FIG. Further, on the main wiring film 10, an antireflection wiring film 11 made of a refractory metal compound (TiN) having a lower reflectance than Al.
Is formed with a thickness of about 300 °. Next, the barrier wiring film 9, the main wiring film 10, and the antireflection wiring film 11
Then, desired patterning is performed to form the upper wiring 12 having the three-layer structure.
【００１２】その後、必要に応じて、さらに上層配線を
形成する等、所望の工程を行い、半導体装置を完成す
る。尚、本実施例では、高融点金属として、Ｔｉを使用
したが、これに限らず、ＷやＭｏ等、他の高融点金属を
使用してもよい。また、本実施例では、バリア用配線膜
３及び９と、反射防止用配線膜５及び１１とを、同じ高
融点金属化合物（ＴｉＮ）で形成したが、これに限ら
ず、バリア用配線膜３及び９と、反射防止用配線膜５及
び１１は、必ずしも同じ高融点金属化合物で形成しなく
てもよい。Thereafter, if necessary, a desired process such as forming an upper layer wiring is performed to complete a semiconductor device. In this embodiment, Ti is used as the high melting point metal. However, the present invention is not limited to this, and another high melting point metal such as W or Mo may be used. In the present embodiment, the barrier wiring films 3 and 9 and the antireflection wiring films 5 and 11 are formed of the same refractory metal compound (TiN). However, the present invention is not limited to this. And 9 and the antireflection wiring films 5 and 11 need not necessarily be formed of the same high melting point metal compound.
【００１３】そして、本実施例では、主配線膜４及び１
０として、Ａｌ合金を使用したが、これに限らず、所望
により、他の金属を使用してもよい。In this embodiment, the main wiring films 4 and 1
Although an Al alloy was used as 0, the present invention is not limited to this, and another metal may be used if desired.
【００１４】[0014]
【発明の効果】以上説明したように、本発明によれば、
前記上層配線のバリア用配線膜を、前記絶縁膜上及び露
出した前記下層配線の主配線膜上に高融点金属膜を形成
した後、当該高融点金属膜に窒素を導入して形成したこ
とで、前記バリア用配線膜を形成する際に、前記下層配
線の主配線膜上には、先ず、高融点金属膜が形成され
る。従って、この高融点金属膜が前記主配線膜を保護す
るため、当該主配線膜表面に、窒化物が形成されること
がない。このため、下層配線と上層配線との接触抵抗を
減少することができる。さらに、前記上層配線は、部分
的に高抵抗となることがないため、配線間の抵抗のバラ
ツキを抑制することができる。この結果、より信頼性が
向上した多層配線構造を有する半導体装置を製造するこ
とができる。As described above, according to the present invention,
The barrier wiring film of the upper wiring is placed on the insulating film and exposed.
Forming a high-melting point metal film on the main wiring film of the lower-layer wiring, and forming the high-melting point metal film by introducing nitrogen into the high-melting point metal film. First, a refractory metal film is formed on the main wiring film. Therefore, since the refractory metal film protects the main wiring film, no nitride is formed on the surface of the main wiring film. For this reason, the contact resistance between the lower wiring and the upper wiring can be reduced. Further, since the upper wiring does not partially have a high resistance, it is possible to suppress a variation in resistance between the wirings. As a result, a semiconductor device having a multilayer wiring structure with improved reliability can be manufactured.
【図１】本発明の実施例に係る半導体装置の製造工程の
一部を示す断面図である。FIG. 1 is a sectional view showing a part of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
【図２】本発明の実施例に係る半導体装置の製造工程の
一部を示す断面図である。FIG. 2 is a cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the present invention.
【図３】本発明の実施例に係る半導体装置の製造工程の
一部を示す断面図である。FIG. 3 is a cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the present invention.
【図４】本発明の実施例に係る半導体装置の製造工程の
一部を示す断面図である。FIG. 4 is a cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the present invention.
【図５】本発明の実施例に係る半導体装置の製造工程の
一部を示す断面図である。FIG. 5 is a cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the present invention.
１ 半導体基板 ２ 絶縁膜 ３ バリア用配線膜 ４ 主配線膜 ５ 反射防止用配線膜 ６ 下層配線 ７ 層間絶縁膜 ８ コンタクト孔 ９ バリア用配線膜 １０ 主配線膜 １１ 反射防止用配線膜 １２ 下層配線 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulating film 3 Barrier wiring film 4 Main wiring film 5 Antireflection wiring film 6 Lower wiring 7 Interlayer insulating film 8 Contact hole 9 Barrier wiring film 10 Main wiring film 11 Antireflection wiring film 12 Lower wiring
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平３−131032（ＪＰ，Ａ) 特開 平３−40433（ＪＰ，Ａ) 特開 昭61−142739（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/28 - 21/288 H01L 21/3205 - 21/3213 H01L 21/768 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-131032 (JP, A) JP-A-3-40433 (JP, A) JP-A-61-142739 (JP, A) (58) Field (Int.Cl. 7 , DB name) H01L 21/28-21/288 H01L 21/3205-21/3213 H01L 21/768
Claims (1)
配線膜、主配線膜及び反射防止用配線膜を順次形成して
なる三層構造を有する下層配線と、当該下層配線上に形
成した絶縁膜と、当該絶縁膜上に、バリア用配線膜、主
配線膜及び反射防止用配線膜を順次形成してなる三層構
造を有する上層配線と、を備え、前記上層配線と下層配
線とを接続した構造を有する半導体装置の製造方法にお
いて、前記上層配線のバリア用配線膜は、前記絶縁膜上
及び露出した前記下層配線の主配線膜上に高融点金属膜
を形成した後、当該高融点金属膜に窒素を導入して形成
することを特徴とする半導体装置の製造方法。1. A lower wiring having a three-layer structure in which a barrier wiring film, a main wiring film, and an anti-reflection wiring film, which are refractory metals of a nitrogen compound, are sequentially formed, and an insulating film formed on the lower wiring. A wiring having a three-layer structure in which a barrier wiring film, a main wiring film, and an anti-reflection wiring film are sequentially formed on the insulating film, and the upper wiring and the lower wiring are connected to each other. In the method for manufacturing a semiconductor device having the above-mentioned structure, the barrier wiring film of the upper wiring is formed on the insulating film.
And forming a high melting point metal film on the exposed main wiring film of the lower wiring, and then introducing nitrogen into the high melting point metal film to form the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04084031A JP3137719B2 (en) | 1992-04-06 | 1992-04-06 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04084031A JP3137719B2 (en) | 1992-04-06 | 1992-04-06 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05291410A JPH05291410A (en) | 1993-11-05 |
| JP3137719B2 true JP3137719B2 (en) | 2001-02-26 |
Family
ID=13819171
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP04084031A Expired - Fee Related JP3137719B2 (en) | 1992-04-06 | 1992-04-06 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3137719B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100369483B1 (en) * | 1995-12-29 | 2003-03-26 | 주식회사 하이닉스반도체 | Method for forming metal wiring in semiconductor device |
| KR100412145B1 (en) * | 2002-01-18 | 2003-12-31 | 주식회사 하이닉스반도체 | A method for forming via hole of semiconductor device |
| JP2006261705A (en) * | 2006-06-23 | 2006-09-28 | Sharp Corp | Thin film transistor and its manufacturing method |
-
1992
- 1992-04-06 JP JP04084031A patent/JP3137719B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05291410A (en) | 1993-11-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4937652A (en) | Semiconductor device and method of manufacturing the same | |
| US5289035A (en) | Tri-layer titanium coating for an aluminum layer of a semiconductor device | |
| JP2545184B2 (en) | Semiconductor device and manufacturing method thereof | |
| US5963827A (en) | Method for producing via contacts in a semiconductor device | |
| JP2845788B2 (en) | Contact hole plug formation method | |
| JP2511892B2 (en) | Multilayer thin film wiring and method for forming the same | |
| US5656542A (en) | Method for manufacturing wiring in groove | |
| EP0628998B1 (en) | Wiring layer for semi conductor device and method for manufacturing the same | |
| JP2770945B2 (en) | Tungsten coating method | |
| JP3137719B2 (en) | Method for manufacturing semiconductor device | |
| JPH0212859A (en) | Formation of multilayer interconnection | |
| US5985754A (en) | Method of forming a void-free contact plug | |
| JPH11312734A (en) | Forming method and structure of contact to copper layer inside insulating layer via of semiconductor wafer | |
| JP2757796B2 (en) | Semiconductor integrated circuit device | |
| JP4221737B2 (en) | Metal wiring manufacturing method | |
| JPH10106972A (en) | Manufacture of electrode wiring structure | |
| JP3301466B2 (en) | Method for manufacturing semiconductor device | |
| JP2002184858A (en) | Method for fabricating semiconductor element | |
| JP3096551B2 (en) | Method for manufacturing semiconductor device | |
| JPH0621236A (en) | Semiconductor device and manufacture thereof | |
| JPH11233517A (en) | Copper wiring in semiconductor devices | |
| JP3154433B2 (en) | Multilayer metal wiring structure and method of forming the same | |
| JP3731497B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH08250495A (en) | Formation of laminated wiring film | |
| JPH06275725A (en) | Manufacture of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071208 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081208 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091208 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101208 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101208 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111208 Year of fee payment: 11 |
|
| LAPS | Cancellation because of no payment of annual fees |