JPS63229839A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63229839A JPS63229839A JP6656887A JP6656887A JPS63229839A JP S63229839 A JPS63229839 A JP S63229839A JP 6656887 A JP6656887 A JP 6656887A JP 6656887 A JP6656887 A JP 6656887A JP S63229839 A JPS63229839 A JP S63229839A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- hole
- internal stress
- top layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 238000002161 passivation Methods 0.000 claims abstract description 22
- 239000012212 insulator Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 25
- 229910052782 aluminium Inorganic materials 0.000 abstract description 13
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 13
- 239000000377 silicon dioxide Substances 0.000 abstract description 12
- 239000011229 interlayer Substances 0.000 abstract description 6
- 229910052751 metal Inorganic materials 0.000 abstract description 6
- 239000002184 metal Substances 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 5
- 239000000463 material Substances 0.000 abstract description 3
- 230000006866 deterioration Effects 0.000 abstract description 2
- 239000002904 solvent Substances 0.000 abstract description 2
- 238000000992 sputter etching Methods 0.000 abstract description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 abstract description 2
- 239000000126 substance Substances 0.000 abstract 2
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000006263 metalation reaction Methods 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は多層配線を有する半導体装置に関し、特に最上
層配線と下層配船を接続するスルーホール部の構造に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having multilayer wiring, and particularly to the structure of a through hole portion connecting the uppermost layer wiring and the lower layer wiring.
従来、多層配線を有する半導体装置、例えば２層配線構
造の場合は下層配線および層間絶縁膜の形成後、眉間絶
縁膜にスルーホールを設けて上層配線を形成しその上層
部にパッシベーション膜が被覆される。Conventionally, in the case of a semiconductor device having multilayer wiring, for example, a two-layer wiring structure, after forming a lower layer wiring and an interlayer insulating film, a through hole is formed in the glabella insulating film to form an upper layer wiring, and the upper layer is covered with a passivation film. Ru.
しかしながら上述した多層配線を有する半導体装置の構
造ではスルーホール部における最上層配線に凹部が生じ
るので、この部分におけるパッシベーション膜のステッ
プ・カバレッジが悪いと耐湿性不良をおこす、また、仮
りにステップ・カバレッジが良好である場合でも配線金
属とパッシベーション膜との間に存在する熱膨張係数の
相違、或いは内部応力の差によりスルーホール部におけ
る配線金属にストレス・マイグレーションが発生しやす
くなる。近年配線構造が微細化されるに伴ないスルーホ
ールにおける高温短期の耐熱性試験または定温長期の耐
熱性試験で導通不良事故をおこすスルーホール部が多発
する傾向にあり、特に配線金属材にアルミニウムまたは
その合金が用いられ他方パッシベーション膜に応力の大
きな例えばプラズマ窒化膜等使用したときな著しくなる
。However, in the structure of a semiconductor device having multilayer wiring as described above, a recess is formed in the top layer wiring in the through-hole area, so if the step coverage of the passivation film in this area is poor, moisture resistance will be poor. Even when the wiring metal is good, stress migration tends to occur in the wiring metal in the through-hole portion due to the difference in thermal expansion coefficient or internal stress between the wiring metal and the passivation film. In recent years, with the miniaturization of wiring structures, there has been a tendency for through holes to frequently cause conduction failure accidents during short-term heat resistance tests at high temperatures or long-term heat resistance tests at constant temperature. This becomes noticeable when such an alloy is used and the passivation film is a highly stressed plasma nitride film, for example.
本発明の目的は、上記の状況に鑑み、配線金属とパッシ
ベーションとの熱膨張差および内部応力差に基づくスル
ーホール部の耐湿性および耐熱性の劣化を解決し得る構
造を備えた半導体装置を提供することである。In view of the above-mentioned circumstances, an object of the present invention is to provide a semiconductor device having a structure capable of solving the deterioration of moisture resistance and heat resistance of a through-hole portion due to a difference in thermal expansion and a difference in internal stress between wiring metal and passivation. It is to be.
本発明によれば、多層配線を有する半導体装置は、最上
層配線と下層配線を接続するスルーホール部の最上層配
線上の凹部がパッシベーション膜に対し小なる内部応力
をもつ絶縁物質によって少なくとも一部が埋設されるこ
とを含む。According to the present invention, in a semiconductor device having multilayer wiring, at least a portion of the recess on the top layer wiring of the through-hole portion connecting the top layer wiring and the lower layer wiring is made of an insulating material having a small internal stress with respect to the passivation film. This includes being buried.
すなわち、本発明によれば最上層配線と下層配線を接続
するスルーホール部の最上層配線上の凹部はパッシベー
ション膜とは内部応力が小さな絶縁物質により少なくと
もその一部が埋設され、その上にパッシベーション膜が
形成される。従って、パッシベーション膜のカバレッジ
の改善による耐湿性の向上と共にスルーホール部の最上
層配線に対するパッシベーション膜の応力（ストレス）
の影響を大幅に緩和できるので最上層配線のスルーホー
ル部における導通不良などを有効に阻止することが可能
となる。That is, according to the present invention, the recess on the top layer wiring of the through-hole portion connecting the top layer wiring and the lower layer wiring is at least partially buried with an insulating material having low internal stress, which is different from the passivation film, and the passivation film is formed on the recessed portion of the top layer wiring. A film is formed. Therefore, the moisture resistance is improved by improving the coverage of the passivation film, and the stress of the passivation film on the top layer wiring in the through-hole area is increased.
Since the influence of this can be greatly alleviated, it becomes possible to effectively prevent conduction failures in the through-hole portions of the uppermost layer wiring.
〔実施例〕 ・ 次に、本発明について図面を参照して説明する。〔Example〕 · Next, the present invention will be explained with reference to the drawings.
第１図は、本発明の一実施例を示すスルーホール部の断
面図である。本実施例によれば、本発明の半導体装置は
半導体基板１１と、フィールド絶縁膜１２と、下層アル
ミ配線１３と、層間絶縁膜１４と、層間絶縁膜１４に開
口されたスルーホール部１５と、スルーホール部１５を
介し下層アルミ配線１３と接続する最上層アルミ配線１
６と、最上層アルミ配線１６のスルーホール部上部に形
成される凹部に埋設されたシリカ・フィルム１７と、プ
ラズマ窒化物からなるパッシベーション膜１８とを含む
。かかる構造の半導体装置は先ず通常のプロセス技術に
より下層アルミ配線１３、層間絶縁膜１４および最上層
アルミ配線１６をそれぞれ０．６μｍ、１．３μｍの膜
厚で形成した後、シリカ・フィルムを平坦部で５００〜
２０００人の膜厚になるように塗布し、ついで通常の方
法で溶剤を飛散させた後、例えば、四弗化炭素ガスを用
いてアクティブ・イオン・エツチングしシリカフィルム
の平坦部分のみを除去すれば、シリカ・フィルムの塗布
膜がスルーホールの凹部のみに残るのできわめて容易に
製造することができる。この際、スルーホール上にでき
る凹部を埋める材質としてはパッシベーション膜と異な
る小さな内部応力をもつ絶縁物質であれば如何なるもの
でも使用可能で、例えばシリカフィルムの代わりにポリ
イミド系の有機塗布膜を用いてもよい。何れにせよ凹部
に埋設されたパッシベーション膜より小さな内部応力を
もつシリカまたはポリイミド樹脂の物質はパッシベーシ
ョン膜１８の段差を解消すると共にスルーホール部１５
に及ぼす機械的応力を緩和するように作用するので、ス
ルーホール部の耐湿性および耐熱性を向上せしめ得る。FIG. 1 is a sectional view of a through-hole portion showing an embodiment of the present invention. According to this embodiment, the semiconductor device of the present invention includes a semiconductor substrate 11, a field insulating film 12, a lower aluminum wiring 13, an interlayer insulating film 14, a through hole portion 15 opened in the interlayer insulating film 14, Top layer aluminum wiring 1 connected to lower layer aluminum wiring 13 via through-hole portion 15
6, a silica film 17 buried in a recess formed above the through-hole portion of the uppermost layer aluminum wiring 16, and a passivation film 18 made of plasma nitride. In a semiconductor device having such a structure, first, the lower layer aluminum wiring 13, the interlayer insulating film 14, and the uppermost layer aluminum wiring 16 are formed with a thickness of 0.6 μm and 1.3 μm, respectively, using a normal process technique, and then a silica film is deposited on the flat part. 500~
After coating the silica film to a film thickness of 2,000 mm and then scattering the solvent using the usual method, active ion etching is performed using, for example, carbon tetrafluoride gas to remove only the flat parts of the silica film. Since the silica film coating remains only in the concave portion of the through hole, it can be manufactured very easily. At this time, any insulating material that has a small internal stress different from that of a passivation film can be used to fill the recess formed on the through hole. For example, a polyimide-based organic coating film may be used instead of a silica film. Good too. In any case, the silica or polyimide resin material, which has a smaller internal stress than the passivation film buried in the recess, eliminates the level difference in the passivation film 18 and also eliminates the step in the through-hole portion 15.
Since it acts to relieve the mechanical stress exerted on the through-hole portion, the moisture resistance and heat resistance of the through-hole portion can be improved.
第２図は本発明の他の実施例を示すスルーホール部の断
面図である０本実施例によれば、凹部を埋める絶縁物質
２７は凹部近傍の最上層アルミ配線２６上に延在するよ
う塗布形成される。従って、プラズマ窒化膜またはスパ
ッタシリコン酸化膜などから成るパッシベーション膜２
８が有する大きな内部応力のスルーホールに対する影響
をより一層効果的に緩和し得る。ここで、２１は半導体
基板、２２はフィールド酸化膜、２３，２４゜２５はそ
れぞれ下層アルミ配線、眉間絶縁膜、スルーホール部で
ある。本実施例の半導体装置を製造するには前実施例と
同様に最上層アルミ配線までを通常のプロセスで形成し
た後シリカフィルム等を塗布し通常のフォトリングラフ
ィにより所望の部分のみレジストパターンを形成し、プ
ラズマエツチング等により不要な塗布膜を除去しついで
レジストを剥利後パッシベーション膜２８を形成すれば
容易に完成することができる。FIG. 2 is a sectional view of a through-hole portion showing another embodiment of the present invention. According to this embodiment, the insulating material 27 filling the recess extends over the top layer aluminum wiring 26 near the recess. Formed by coating. Therefore, the passivation film 2 made of a plasma nitride film or a sputtered silicon oxide film, etc.
The influence of the large internal stress of No. 8 on the through hole can be alleviated even more effectively. Here, 21 is a semiconductor substrate, 22 is a field oxide film, 23, 24.degree. 25 is a lower layer aluminum wiring, an insulating film between the eyebrows, and a through hole portion, respectively. To manufacture the semiconductor device of this example, as in the previous example, after forming up to the top layer aluminum wiring using the normal process, a silica film or the like is applied, and a resist pattern is formed only on the desired portion using normal photolithography. However, it can be easily completed by removing unnecessary coating films by plasma etching or the like, and then forming the passivation film 28 after stripping off the resist.
以上詳細に説明したように、本発明によれば、最上層配
線のスルーホール部上の凹部がパッシベーション膜とは
内部応力の小さな物質により少なくともその一部が埋設
されることにより、スルーホール部において最上層配線
金属がパッシベーション膜から受ける応力（ストレス）
を緩和することが可能となり、高温短期の耐熱性試験お
よび低温長期の高温保管に際して配線接続が不良となる
ことを防止し得るので半導体装置の信頼性向上に顕著な
る効果を奏することができる。As described above in detail, according to the present invention, the recesses on the through-hole portions of the uppermost layer wiring are at least partially buried with a material having low internal stress, which is different from a passivation film. Stress that the top layer wiring metal receives from the passivation film
This makes it possible to prevent wiring connections from becoming defective during short-term high-temperature heat resistance tests and long-term high-temperature storage, which can have a significant effect on improving the reliability of semiconductor devices.
第１図は本発明の一実施例を示すスルーホール部の断面
図、第２図は本発明の他の実施例を示すスルーポール部
の断面図である。
１１．２１・・・半導体基板、１２．２２・・・フィー
ルド絶縁膜、１３．２３・・・下層アルミ配線、１４．
２４・・・層間絶縁膜、１５．２５・・・スルーホール
部、１６．２６・・・最上層アルミ配線、１７゜２７・
・・シリカ等の絶縁塗布膜、１８．２８・・・パッシベ
ーション膜。
第 １ 百
茅 ２＠FIG. 1 is a cross-sectional view of a through-hole portion showing one embodiment of the present invention, and FIG. 2 is a cross-sectional view of a through-pole portion showing another embodiment of the present invention. 11.21... Semiconductor substrate, 12.22... Field insulating film, 13.23... Lower layer aluminum wiring, 14.
24...Interlayer insulating film, 15.25...Through hole part, 16.26...Top layer aluminum wiring, 17°27.
... Insulating coating film such as silica, 18.28... Passivation film. 1st Hyakumaya 2@
Claims (1)
と下層配線を接続するスルーホールの最上層配線上の凹
部がパッシベーション膜に対し小なる内部応力をもつ絶
縁物によって少なくとも一部が埋設されることを特徴と
する半導体装置。In a semiconductor device having a multilayer wiring structure, a recess on the top layer wiring of a through hole connecting the top layer wiring and the lower layer wiring is at least partially buried with an insulator having a small internal stress with respect to the passivation film. Characteristic semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6656887A JPS63229839A (en) | 1987-03-19 | 1987-03-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6656887A JPS63229839A (en) | 1987-03-19 | 1987-03-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63229839A true JPS63229839A (en) | 1988-09-26 |
Family
ID=13319690
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6656887A Pending JPS63229839A (en) | 1987-03-19 | 1987-03-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63229839A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7183189B2 (en) | 1996-12-04 | 2007-02-27 | Seiko Epson Corporation | Semiconductor device, circuit board, and electronic instrument |
| US7470979B2 (en) | 1996-12-04 | 2008-12-30 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
-
1987
- 1987-03-19 JP JP6656887A patent/JPS63229839A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7183189B2 (en) | 1996-12-04 | 2007-02-27 | Seiko Epson Corporation | Semiconductor device, circuit board, and electronic instrument |
| US7470979B2 (en) | 1996-12-04 | 2008-12-30 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| US7511362B2 (en) | 1996-12-04 | 2009-03-31 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| US7521796B2 (en) | 1996-12-04 | 2009-04-21 | Seiko Epson Corporation | Method of making the semiconductor device, circuit board, and electronic instrument |
| US7842598B2 (en) | 1996-12-04 | 2010-11-30 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| US7888260B2 (en) | 1996-12-04 | 2011-02-15 | Seiko Epson Corporation | Method of making electronic device |
| US8115284B2 (en) | 1996-12-04 | 2012-02-14 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board and electronic instrument |
| US8384213B2 (en) | 1996-12-04 | 2013-02-26 | Seiko Epson Corporation | Semiconductor device, circuit board, and electronic instrument |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4123565A (en) | Method of manufacturing semiconductor devices | |
| JP2785338B2 (en) | Method for manufacturing semiconductor device | |
| US4185294A (en) | Semiconductor device and a method for manufacturing the same | |
| JPS63229839A (en) | Semiconductor device | |
| JPS62295437A (en) | Forming method for multilayer interconnection | |
| JPH038581B2 (en) | ||
| JP2000183108A (en) | Semiconductor integrated circuit device and its manufacture | |
| JPS60109248A (en) | Semiconductor ic device and manufacture thereof | |
| JPH01154536A (en) | Manufacture of semiconductor device | |
| JP2003218116A (en) | Semiconductor device and its manufacturing method | |
| JPH0766201A (en) | Semiconductor device for electromigration test, manufacture thereof, and method of electromigration test | |
| JPS5966147A (en) | Manufacture of multilayer wirings | |
| JPH0614523B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2000091368A (en) | Manufacture of semiconductor element and the semiconductor element | |
| JPS6085514A (en) | Manufacture of semiconductor device | |
| JPH0618239B2 (en) | Semiconductor device | |
| JPS6322067B2 (en) | ||
| JPH0547764A (en) | Semiconductor device and its manufacture | |
| JPH0330991B2 (en) | ||
| JPS63107045A (en) | Semiconductor device | |
| JPH02237137A (en) | Manufacture of semiconductor device | |
| JPS59163838A (en) | Manufacture of semiconductor device | |
| JPS62271453A (en) | Manufacture of semiconductor element | |
| JPH06163814A (en) | Forming method of thin film resistor | |
| JPH02285659A (en) | Semiconductor device |