JPH0614523B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor device and a method of manufacturing the same, and more specifically, in the case of forming a wiring made of Al or Al alloy and a plasma CVD insulating protective film on the wiring. The present invention relates to a structure for preventing defects such as wiring loss and a method for forming the structure.

[Technical Background of the Invention] A plasma silicon nitride film (hereinafter, referred to as a P-SiN film) formed by a plasma CVD method contains moisture or N.
Since it has a high ability to block a ions and can be formed at a relatively low temperature, it has extremely excellent properties as a semiconductor device passivation film after wiring is formed. It is used as a protective film and an interlayer insulating film between multilayer wirings.

[Problems of the Background Art] Since the P-SiN film has a thermal expansion coefficient much smaller than that of Al, which is a wiring material, when the P-SiN film is formed on the Al wiring, the Al wiring is formed in the cooling process after the film formation. Is P
-Negative hydrostatic pressure due to the compressive stress of the SiN film comes to be exerted (there is a tendency also in the plasma CVD insulating film other than the P-SiN film), and as a result, the Al wiring is fluidized (migrated). It is known that such a phenomenon occurs that the rising wiring disappears.

FIG. 3 illustrates the phenomenon as described above in the conventional semiconductor device. In the figure, 1 is a semiconductor substrate,
Reference numeral 2 is an insulating film such as SiO ₂ , 3 is a wiring such as Al formed on the insulating film 2, and 4 is an insulating protective film made of P—SiN formed on the wiring 3 and the insulating film 2. When the insulating protective film 4 is formed on the wiring 3 as shown in the figure, Al and P
-There is a considerable difference in the coefficient of thermal expansion from SiN (Al: 2
3.8 × 10 ^-6 / ° C, P-SiN: 4 × 10 ^-6 / ° C), so P
-SiN film formation (P-SiN formation temperature is approximately 400 ° C)
In the subsequent cooling process, the shrinkage amount of the wiring 3 is reduced by the insulating protective film 4.
As a result, a negative hydrostatic pressure (tensile stress perpendicular to each surface) outward acts on each surface of the wiring 3 by the insulating protective film 4. In that case, if there is some kind of defect or contamination in the wiring 3, stress concentration or the like occurs therein, and a part 3a of the wiring 3 flows and disappears, so that the substantial width of the wiring 3 becomes significantly larger than the design value. This results in a decrease in wiring resistance and a significant increase in wiring resistance. This partial disappearance of the wiring proceeds until the internal stress of the wiring 3 and the resistance of fluidization (migration) are balanced.

Therefore, conventionally, measures such as designing a large wiring width in advance (for example, 6 μm or more) in consideration of partial loss of wiring, or hardening the wiring surface to suppress wiring fluidization (migration) have been taken. Has been done.

However, if the wiring width is increased, the degree of integration is reduced, the chip area is increased, and as a result, the yield is reduced, which is not preferable. (That is, when the line width is increased from 4 μm to 6 μm, the area per element of the bipolar LSI is, for example, 6 × 10 ³ μm.
^{The number} is increased from ² / element to 15 × 10 ³ μm ² / element, and thus the integration degree of the bipolar LSI is significantly reduced. ) In addition, the conventional method for hardening the wiring surface is to implant boron ions into the wiring surface (implantation amount 1 × 10 ¹⁶ cm ^-2
Hereinafter, accelerating voltage of 50 keV) and a method of coating the wiring surface with TiSi ₂ (film thickness 500Å) are known, but these methods are high in process cost and cannot completely suppress wiring loss. , Was not suitable for practical use.

On the other hand, in the conventional semiconductor device and the manufacturing method thereof, the hillock 3b is formed on the wiring surface together with the disappearance of the wiring as described above.
There was a problem when it occurred. As is well known, when a hillock 3b is formed on the surface of the wiring 3, an interlayer insulating film or a passivation film (P- in the semiconductor device of FIG.
The passivation film and the interlayer insulating film are flattened as much as possible, because defects and surface protrusions 4a also occur in the SiN film) and insulation defects of the protective insulating film itself, formation defects of upper layer wirings, and the like are likely to occur. Is desirable.

[Object of the Invention] A first object of the present invention is to solve the problems existing in the conventional semiconductor device as described above, there is no fear that a part of the wiring will be lost, and a defective protective film or upper wiring due to hillocks. It is an object of the present invention to provide a semiconductor device capable of almost completely suppressing the above. A second object of the present invention is to provide a manufacturing method capable of manufacturing a semiconductor device having a flat protective film and preventing the partial disappearance of the wiring as described above with a high yield.

[Summary of the Invention] A semiconductor device according to the present invention includes a wiring made of Al or an Al alloy, a resin film made of a polyimide resin (having the same pattern as the wiring) deposited on the upper surface of the wiring, and the resin film. And an insulating protective film formed by a plasma CVD method so as to cover the surface and the side surface of the resin film and the wiring. Further, the manufacturing method of the present invention is characterized in that a wiring metal film and a resin film are laminated, etched in the same pattern, and then covered with an insulating protective film by a plasma CVD method. In the semiconductor device of the present invention, there is no possibility that a part of the wiring will be lost, and the surface of the insulating protective film will not have surface defects due to hillocks on the wiring surface.

[Embodiment of the Invention] An embodiment of a semiconductor device and a manufacturing method thereof according to the present invention will be described below with reference to FIGS. 1 and 2.

1 and 2 show the outline of the method for manufacturing the semiconductor device of the present invention, and FIG. 2 is a sectional view showing the structure of the semiconductor device of the present invention.

1 and 2, portions indicated by the same reference numerals as those in FIG. 3 represent the same portions as those of the semiconductor device shown in FIG.
Reference numeral 1 is a semiconductor substrate, 2 is an insulating film such as SiO ₂ , 3 is wiring made of Al or Al alloy, and 4 is an insulating protective film such as a P-SiN film.

As shown in FIG. 2, in the semiconductor device of the present invention, the upper surface of the wiring 3 is covered with a resin film 5 made of a polyimide resin, and the surface of the resin film 5 and the side surface of the wiring 3 and the surface of the insulating film 2 are covered with P. It is characterized by being covered with an insulating protective film 4 made of a —SiN film or the like. In the semiconductor device of the present invention having such a structure, since the resin film 5 is interposed on the upper surface of the wiring 3, the upper surface of the wiring 3 directly contacts the insulating protection film 4 when the insulating protection film 4 is formed. Since there is no contact, the tensile force from the insulating protective film 4 is reduced, and as a result,
It is possible to prevent the wiring 3 from partially disappearing.

When the hillock 3b on the upper surface of the wiring 3 is covered with the resin film 5 formed on the upper surface of the wiring 3, the resin film 5 fills the hillock 3b of the wiring 3 and becomes flat, so that the surface of the insulating protective film 4 is also covered. It can be flattened.

The semiconductor device of the present invention as described above is manufactured through the following steps.

First, after an insulating film ₂ such as SiO ₂ is formed on the entire surface of the semiconductor substrate 1, Al or Al alloy is vapor-deposited on the insulating film 2 to a predetermined thickness to form a metal film, and then the metal film is formed. A resin film made of polyimide resin was formed on the film to a thickness of 1000Å to 3000Å. The resin film is formed by applying the liquid resin onto the semiconductor substrate 1 by a spinner and then, for example, at 100 ° C. for 1 hour.
It was carried out by heating the resin at 50 ° C. for 1 hour and at 350 ° C. for 1 hour to cure the resin.

After forming the resin film, a resist pattern 6 is formed on the resin film by a known method (for example, the resist film formed on the resin film is selectively exposed through a predetermined mask, and then developed and washed). The resist pattern 6
First, the resin film is etched by reactive ion etching (RIE) using as a mask (oxygen gas 7 Pa as reaction gas, RF power 150 W), and then the metal film is RIE etched (reaction gas; CCl _4). , Pressure 50
As shown in FIG. 1, the wiring 3, the resin film 5 and the resist pattern 6 are formed on the insulating film 2 by applying Pa and electric power of 100 W).

Next, after removing the resist pattern 6 with an organic solvent, an insulating protective film 4 made of a P-SiN film is applied to the entire surface by a plasma CVD device to a thickness of 1.0 .mu.m, and the semiconductor device of the present invention as shown in FIG. Was formed. When forming a multi-layer wiring, an upper layer wiring is further formed on the insulating protection film 4.

Further, it can be easily understood that other known processes are combined with respect to predetermined portions such as contact holes which do not require the structure in the present invention.

[Effects of the Invention] A large number of semiconductor devices having multi-layer interconnections were manufactured using the above method, and compared with a semiconductor device having multi-layer interconnections having a conventional structure produced by the conventional method.

In FIG. 4, the horizontal axis represents the total cross-sectional area A (mm ² ) of the upper and lower wirings and the vertical axis represents the non-defective rate ε (%), which is a comparative display of the conventional semiconductor device and the semiconductor device of the present invention. (A) of the figure is the non-defective rate of the semiconductor device of the present invention, and (b) of the figure.
Shows the non-defective rate of the conventional semiconductor device.

As is clear from FIG. 4, in the semiconductor device of the present invention,
Although the non-defective rate is maintained at 100% even if the crossing area of the wiring is increased, it can be seen that in the conventional semiconductor device, the non-defective rate is sharply decreased when the crossing area of the wiring is increased. This means that in the semiconductor device of the present invention, the stress relaxation effect of the resin film causes less damage or partial disappearance of the wiring, and the hillocks of the resin film are filled with the interlayer insulating film and the passivation film being flat. It means that.

On the other hand, the same number of semiconductor devices of the present invention and conventional semiconductor devices were manufactured with the width of the wiring being 4 μm, and the amount of disappearance of the wiring in these semiconductor devices was examined. As a result, the semiconductor device of the present invention showed no wiring disappearance. Contrary to nothing happening,
In the conventional semiconductor device, 20 to 40% of the volume of the wiring is lost, and in the conventional improved semiconductor device in which boron is ion-implanted into the wiring, 10 to 20% of the volume of the wiring is lost. I understood.

On the other hand, the cost required for applying the polyimide resin in the method of the present invention is the same as that in the conventional method such as B ion implantation or TiS _2.
Comparing with the cost of coating etc., the cost required for applying the polyimide resin is 1/5 or less of the cost of B ion implantation and TiS ₂ coating, and the method of the present invention can be carried out at a lower cost than the conventional method. It became clear.

As described above, according to the semiconductor device of the present invention, the defect rate such as wiring disappearance and protective film insulation failure is lower than that of the conventional semiconductor device, and the wiring can be made thinner than the conventional one, and the yield is high. A semiconductor device that can be manufactured at low cost is provided. Further, according to the manufacturing method of the present invention, there is provided a semiconductor device manufacturing method capable of manufacturing the semiconductor device of the present invention having the above excellent characteristics at a lower cost and a higher yield than the conventional method.

[Brief description of drawings]

1 is a sectional view showing one step of the method of the present invention, FIG. 2 is a sectional view of a semiconductor device of the present invention, FIG. 3 is a sectional view of a conventional semiconductor device, and FIG. 4 is a semiconductor device of the present invention. It is the figure which compared and displayed the non-defective rate and the non-defective rate of the conventional semiconductor device. 1 ... Semiconductor substrate, 2 ... Insulating film, 3 ... Wiring, 3a ...
... (disappearing) edge portion, 3b ... hillock, 4 ... insulating protective film, 4a ... protruding portion of insulating protective film, 5 ... resin film,
6 ... Resist pattern.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takashi Yasushima 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Stock company, Toshiba Tamagawa Plant (56) Reference JP-A-55-22865 (JP, A) JP Sho 53-99882 (JP, A)

Claims (2)

[Claims] 1. A wiring made of Al or an Al alloy, a resin film made of a polyimide resin having the same pattern deposited on the upper surface of the wiring other than a predetermined portion of the wiring, the surface of the resin film, the resin film, and Plasma CV deposited over the sides of the wiring
A semiconductor device having an insulating protective film formed by the D method. 2. A step of directly or indirectly forming a metal film of Al or an Al alloy on a semiconductor substrate, a step of forming a polyimide resin resin film on the metal film, and a step of forming a polyimide resin resin film on the metal film. A step of forming a predetermined resist pattern,
A step of continuously etching the resin film and the metal film using the resist pattern as a mask; and an insulating protective film formed by a plasma CVD method over the entire surface of the semiconductor substrate from the resin film after peeling the resist pattern. A method of manufacturing a semiconductor device, which comprises a step of covering.