JP2820281B2 - A1 Multilayer wiring structure of semiconductor device - Google Patents
A1 Multilayer wiring structure of semiconductor deviceInfo
- Publication number
- JP2820281B2 JP2820281B2 JP21868289A JP21868289A JP2820281B2 JP 2820281 B2 JP2820281 B2 JP 2820281B2 JP 21868289 A JP21868289 A JP 21868289A JP 21868289 A JP21868289 A JP 21868289A JP 2820281 B2 JP2820281 B2 JP 2820281B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- insulating film
- normal
- pressure cvd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Description
【発明の詳細な説明】 （産業上の利用分野） この発明は半導体素子のAl多層配線構造に係り、特に
層間絶縁膜部分に関するものである。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an Al multilayer wiring structure of a semiconductor device, and more particularly to an interlayer insulating film portion.
（従来の技術） 半導体素子（IC,LSI）においては、配線の自由度が増
し、パターン設計が容易になるなどの利点から、多層配
線構造が採用される傾向にある。この多層配線構造にお
いては、金属配線層間に層間絶縁膜を形成する必要があ
るが、現在、金属配線材料としてはAl系合金が主に用い
られているため、層間絶縁膜は、450℃以下の低温で生
成しなければならない。つまり、層間絶縁膜の形成時に
は既に下層Al配線が形成されており、これを保護する目
的から450℃以下の低温で層間絶縁膜を生成する必要が
ある。(Prior Art) In a semiconductor element (IC, LSI), a multilayer wiring structure tends to be adopted because of an advantage that a degree of freedom of wiring is increased and a pattern design is facilitated. In this multilayer wiring structure, it is necessary to form an interlayer insulating film between metal wiring layers, but since an Al-based alloy is mainly used as a metal wiring material at present, the interlayer insulating film has a temperature of 450 ° C. or less. Must be produced at low temperatures. In other words, when the interlayer insulating film is formed, the lower Al wiring is already formed, and it is necessary to form the interlayer insulating film at a low temperature of 450 ° C. or lower for the purpose of protecting this.
このため、層間絶縁膜材質としては、常圧CVD酸化膜
（AP−SiO,AP−PSG,AP−BPSG等。APはAtmosphere Press
ure（常圧）の略）あるいはプラズマCVD酸化膜（PE−Si
O等。PEはPlasma Enhanced（プラズマ生成）の略）が主
に使用されている。また、最近は、低温形成が可能な上
に、形成と同時に平坦膜が得られるため、常圧TEOS酸化
膜（AP−TEOS。TEOSはテトラ・エチル・オキシ・シラン
を意味する）、プラズマTEOS酸化膜（PE−TEOS）が注目
され、使用されている。For this reason, as the material of the interlayer insulating film, a normal pressure CVD oxide film (AP-SiO, AP-PSG, AP-BPSG, etc., AP is Atmosphere Press)
ure (abbreviation for normal pressure)) or plasma CVD oxide film (PE-Si
O etc. For PE, Plasma Enhanced (abbreviation of plasma generation) is mainly used. In recent years, since low-temperature formation is possible and a flat film can be obtained simultaneously with the formation, a normal-pressure TEOS oxide film (AP-TEOS; TEOS means tetra-ethyl-oxy-silane) and a plasma TEOS oxide Attention has been paid to membranes (PE-TEOS).
（発明が解決しようとする課題） しかるに、層間絶縁膜として常圧CVD酸化膜あるいは
常圧TEOS酸化膜などの常圧CVD系絶縁膜を用いると、そ
の上に上層Al配線を形成し、その上にパッシベーション
膜としてプラズマCVD SiN膜（シリコン窒化膜）を形成
した時に、前記上層Al配線に「Alボイド」と呼ばれるAl
欠損不良が多発する問題点があった。ここで、「Alボイ
ド」とは第２図に示すように、Al配線パターン１の一部
が符号２で示すように欠落する現象で、パッシベーショ
ン膜などのAl配線被覆膜の膜ストレスによりAlが高温ク
リープすることが原因だと言われている。そして、「Al
ボイド」が存在すると、その付近の電流密度が大きくな
り、エレクトロマイグレーションによる断線不良を引き
起したりするため好ましくない。(Problems to be Solved by the Invention) However, if a normal-pressure CVD insulating film such as a normal-pressure CVD oxide film or a normal-pressure TEOS oxide film is used as an interlayer insulating film, an upper Al wiring is formed thereon, and When a plasma CVD SiN film (silicon nitride film) is formed as a passivation film on the
There was a problem that defective defects frequently occurred. Here, the "Al void" is a phenomenon in which a part of the Al wiring pattern 1 is lost as shown by reference numeral 2 as shown in FIG. 2, and the Al void is formed by a film stress of an Al wiring coating film such as a passivation film. Is said to be caused by high temperature creep. And "Al
The presence of “voids” is not preferable because the current density in the vicinity of the “voids” increases and a disconnection failure due to electromigration is caused.
さて、上述のように、層間絶縁膜として常圧CVD系絶
縁膜を用いた場合、その上に上層Al配線を形成し、その
上にパッシベーション膜としてプラズマCVD SiN膜を形
成した時に前記上層Al配線にAlボイドが発生するわけで
あるが、その原因が以下に述べることであることを本発
明者は実験により確かめた。As described above, when a normal-pressure CVD-based insulating film is used as an interlayer insulating film, an upper Al wiring is formed thereon, and a plasma CVD SiN film is formed thereon as a passivation film. Al voids are generated in the sample, and the present inventors have confirmed through experiments that the cause is as described below.
つまり、第３図（ａ）に示すように常圧CVD系絶縁膜1
1上にAl配線12が形成されている場合、この上にパッシ
ベーション膜としてプラズマCVD SiN膜を形成すると、
次のような現象が起きる。すなわち、常圧CVD系絶縁膜1
1は、加熱すると水分を放出して収縮する性質を持ち、
プラズマCVD SiN膜の生成温度（350〜400℃）では、こ
の水分放出が起き、常圧CVD系絶縁増11はどんどん収縮
しようとする。ところが、プラズマCVD SiN膜は水分を
ほとんど透過させないため、該プラズマCVD SiN膜の厚
さがある程度以上になると、常圧CVD系絶縁膜11からの
水分放出がストップし、膜収縮が起きなくなる。ところ
が、第３図（ｂ）に示すように、Al配線12の側壁部にお
いてはプラズマCVD SiN膜13の膜質が良くないために、
この部分からは水分（H2O）がある程度透過してしま
う。そのため、Al配線12近傍の常圧CVD絶縁膜11だけ
に、第３図（ｂ）に矢印で示すように水分放出による膜
収縮が生じる。このため、プラズマCVD SiN膜13の持つ
圧縮応力の作用に、下地常圧CVD系絶縁膜11の上述した
ような局部的な膜収縮の作用が加わって、Al配線12内に
大きな引張り応力が発生して、多数の大きなAlボイドが
発生してしまう。That is, as shown in FIG.
When an Al wiring 12 is formed on 1 and a plasma CVD SiN film is formed thereon as a passivation film,
The following phenomena occur: That is, the normal pressure CVD insulating film 1
1 has the property of releasing moisture and shrinking when heated,
At the formation temperature of the plasma CVD SiN film (350 to 400 ° C.), this water release occurs, and the normal pressure CVD-based insulating insulation 11 tends to shrink more and more. However, since the plasma CVD SiN film hardly permeates moisture, when the thickness of the plasma CVD SiN film exceeds a certain level, the release of moisture from the atmospheric pressure CVD insulating film 11 stops, and the film shrinkage does not occur. However, as shown in FIG. 3B, the quality of the plasma CVD SiN film 13 on the side wall of the Al wiring 12 is not good.
Water (H 2 O) permeates to some extent from this part. Therefore, only the normal-pressure CVD insulating film 11 in the vicinity of the Al wiring 12 undergoes film shrinkage due to moisture release as shown by an arrow in FIG. 3 (b). As a result, the action of the compressive stress of the plasma CVD SiN film 13 is added to the action of the local film shrinkage of the base normal-pressure CVD insulating film 11 as described above, and a large tensile stress is generated in the Al wiring 12. As a result, many large Al voids are generated.
この発明は上記の点に鑑みなされたもので、層間絶縁
膜として常圧CVD系絶縁膜を用いた場合における、パッ
シベーション膜（SiN膜）生成時の、上層Al配線上のAl
ボイドの発生を防止できる半導体素子のAl多層配線構造
を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has been described in connection with the case where a normal-pressure CVD insulating film is used as an interlayer insulating film.
An object of the present invention is to provide an Al multilayer wiring structure of a semiconductor device which can prevent generation of voids.
（課題を解決するための手段） 本発明は、下地層上に第１のAl配線を形成し、この第
１のAl配線上に常圧CVD系絶縁膜を形成し、この常圧CVD
系絶縁膜上に第１のシリコン窒化膜を形成し、その上に
第２のAl配線を形成し、その上にパッシベーション膜と
しての第２のシリコン窒化膜を形成するようにしたもの
である。(Means for Solving the Problems) According to the present invention, a first Al wiring is formed on a base layer, and a normal pressure CVD based insulating film is formed on the first Al wiring.
A first silicon nitride film is formed on a system insulating film, a second Al wiring is formed thereon, and a second silicon nitride film as a passivation film is formed thereon.
（作 用） 上記この発明のAl多層配線構造においては、層間絶縁
膜としての常圧CVD系絶縁膜上の全面が、パッシベーシ
ョン膜と同様な第１のSiN膜（水分を遮断する膜）であ
らかじめ覆われている。したがって、製造時、最終工程
でパッシベーション膜（第２のSiN膜）を形成した時
に、その膜質が第２のAl配線の側壁部で良くなく、この
部分では、層間絶縁膜（常圧CVD系絶縁膜）からの局部
的な水分放出が起る恐れがあっても、この水分放出は、
常圧CVD系絶縁膜上の全面にあらかじめ形成されているS
iN膜で防止される。すなわち、この発明の構造とすれ
ば、パーシベーション膜生成時に、常圧CVD系絶縁膜か
らの局部的な水分放出がなく、その水分放出に伴う常圧
CVD系絶縁膜の局部的な膜収縮が防止される。したがっ
て、パッシベーション膜生成時の上層Al配線上でのAlボ
イドの発生がなくなる。(Operation) In the Al multilayer wiring structure of the present invention, the entire surface of the normal-pressure CVD-based insulating film as the interlayer insulating film is previously formed with a first SiN film (a film that blocks moisture) similar to the passivation film. Covered. Therefore, when a passivation film (second SiN film) is formed in the final step during manufacturing, the quality of the film is not good at the side wall portion of the second Al wiring, and in this portion, an interlayer insulating film (normal pressure CVD insulating film) is formed. Water release from the membrane) may occur,
S previously formed on the entire surface of the normal-pressure CVD insulating film
It is prevented by the iN film. In other words, according to the structure of the present invention, there is no local water release from the normal-pressure CVD-based insulating film during the generation of the passivation film.
Local film shrinkage of the CVD insulating film is prevented. Therefore, the generation of Al voids on the upper Al wiring when the passivation film is generated is eliminated.
（実施例） 以下この発明の一実施例を図面を参照して説明する。
第１図はこの発明のAl多層配線構造の一実施例を示す断
面図である。この図において、21は半導体基板にIC回路
を作り込み、その上を絶縁膜で覆った下地層である。こ
の下地層21上に100％AlまたはAl系合金からなる第１層A
l配線22が形成される。さらにその第１層Al配線22を覆
って下地層21上の全面には、層間絶縁膜としての常圧CV
D系絶縁膜23例えばAP−PSG膜,AP−SiO2膜,AP−BPSG膜,A
P−TEOS膜、が5000Å〜１μｍ厚に形成される。そし
て、この常圧CVD系絶縁膜23上には、該絶縁膜23上の全
面を覆って第１のプラズマCVD SiN膜24が約500Å以上の
厚さに形成される。そして、このプラズマCVD SiN膜24
上に、第１層と同一材質の第２層Al配線25が形成され、
さらにこの第２層Al配線25を覆ってパッシベーション膜
としての第２のプラズマCVD SiN膜26が前記SiN膜24上の
全面に5000Å以上の厚さに形成される。An embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 is a sectional view showing an embodiment of an Al multilayer wiring structure of the present invention. In this figure, reference numeral 21 denotes a base layer in which an IC circuit is formed on a semiconductor substrate and the IC circuit is covered with an insulating film. A first layer A made of 100% Al or an Al-based alloy on the underlayer 21
l Wiring 22 is formed. Further, a normal pressure CV as an interlayer insulating film is formed on the entire surface of the underlayer 21 so as to cover the first layer Al wiring 22.
D-based insulating film 23 for example AP-PSG film, AP-SiO 2 film, AP-BPSG film, A
A P-TEOS film is formed to a thickness of 5000-1 μm. Then, a first plasma CVD SiN film 24 having a thickness of about 500 ° or more is formed on the normal pressure CVD type insulating film 23 so as to cover the entire surface of the insulating film 23. And this plasma CVD SiN film 24
A second layer Al wiring 25 of the same material as the first layer is formed thereon,
Further, a second plasma CVD SiN film 26 as a passivation film is formed on the entire surface of the SiN film 24 to have a thickness of 5000 mm or more, covering the second layer Al wiring 25.
このようなAl多層配線構造は次のように製造される。
まず下地層21上に通常のスパッタ蒸着法およびホトリソ
・エッチング技術によって第１層Al配線22を形成した
後、それらの上に、常圧CVD法により450℃以下の低温で
常圧CVD系絶縁膜23を5000Å〜１μｍ厚に形成する。そ
の後、その常圧CVD系絶縁膜23上の全面にプラズマCVD法
によりプラズマCVD SiN膜24を約500Å以上の厚さに均一
に生成した後、そのプラズマCVD SiN膜24上に第１層と
同様な方法で第２層Al配線25を形成する。最後に、この
第２層Al配線25とプラズマCVD SiN膜24上の全面に、パ
ッシベーション膜としてのプラズマCVD SiN膜26をプラ
ズマCVD法により5000Å以上の厚さに形成する。この
時、プラズマCVD SiN膜26は、第２層Al配線25の側壁部
においては膜質が良くなく、この部分では、常圧CVD系
絶縁膜23からの局部的な水分放出が起る恐れがあるが、
この方法（この構造）によれば、常圧CVD系絶縁膜23上
の全面にあらかじめプラズマCVD SiN膜24が均一に形成
されているので、このプラズマCVD SiN膜24により局部
的な水分放出が防止される。したがって、局部的な水分
放出に伴う常圧CVD系絶縁膜23の局部的な膜収縮もな
く、その結果として第２層Al配線25上でのAlボイドの発
生も防止される。Such an Al multilayer wiring structure is manufactured as follows.
First, a first layer Al wiring 22 is formed on the underlayer 21 by a normal sputter deposition method and a photolitho etching technique, and then a normal pressure CVD insulating film is formed thereon by a normal pressure CVD method at a low temperature of 450 ° C. or less. 23 is formed to a thickness of 5000-1 μm. Thereafter, a plasma CVD SiN film 24 is uniformly formed to a thickness of about 500 mm or more on the entire surface of the normal-pressure CVD insulating film 23 by a plasma CVD method, and the same as the first layer is formed on the plasma CVD SiN film 24. The second layer Al wiring 25 is formed by a suitable method. Finally, a plasma CVD SiN film 26 as a passivation film is formed on the entire surface of the second layer Al wiring 25 and the plasma CVD SiN film 24 to a thickness of 5000 mm or more by a plasma CVD method. At this time, the quality of the plasma CVD SiN film 26 is not good in the side wall portion of the second layer Al wiring 25, and in this portion, there is a possibility that local moisture release from the atmospheric pressure CVD insulating film 23 may occur. But,
According to this method (this structure), since the plasma CVD SiN film 24 is uniformly formed in advance on the entire surface of the normal-pressure CVD insulating film 23, local discharge of moisture is prevented by the plasma CVD SiN film 24. Is done. Accordingly, there is no local film shrinkage of the normal-pressure CVD insulating film 23 due to local water release, and as a result, generation of Al voids on the second-layer Al wiring 25 is also prevented.
なお、上記一実施例では、プラズマCVD SiN膜26単層
でパッシベーション膜を構成したが、前記プラズマCVD
SiN膜26の下にPSG膜を設けてパッシベーション膜を２層
構造としてもよい。この２層構造においても、従来同様
にしてAlボイドの問題点があり、この発明によればそれ
を解決できる。ただし、パッシベーション膜がPSG膜単
層の場合は、この発明は不要である。それは、PSG膜の
場合は、膜質の良し悪しに関係なく全面で常圧CVD系絶
縁膜（層間絶縁膜）からの水分の放出が行われるからで
ある。全面で水分の放出が行われれば、層間絶縁膜の局
部的な膜収縮が起らず、延いては第２層Al配線上にAlボ
イドが生じないのである。この発明は、パッシベーショ
ン膜の少なくとも一部がSiN膜（水分を遮断する膜）で
あって、該SiN膜が上層Al配線の側壁部では膜質が悪
く、その部分では層間絶縁膜（常圧CVD系絶縁膜）から
の水分放出が起る場合に必要となるのである。In the above-described embodiment, the passivation film is constituted by a single layer of the plasma CVD SiN film 26.
A PSG film may be provided below the SiN film 26, and the passivation film may have a two-layer structure. Even in this two-layer structure, there is a problem of Al void as in the conventional case, and according to the present invention, it can be solved. However, when the passivation film is a single layer of the PSG film, the present invention is unnecessary. This is because, in the case of a PSG film, moisture is released from the normal-pressure CVD insulating film (interlayer insulating film) over the entire surface regardless of the quality of the film. If moisture is released over the entire surface, local film shrinkage of the interlayer insulating film does not occur, and thus no Al voids are formed on the second-layer Al wiring. According to the present invention, at least a part of the passivation film is a SiN film (a film that blocks moisture), and the SiN film has poor film quality on the side wall portion of the upper Al wiring, and an interlayer insulating film (normal pressure CVD system) This is necessary when moisture is released from the insulating film).
（発明の効果） 以上詳細に説明したようにこの発明によれば、層間絶
縁膜として常圧CVD系絶縁膜を用い、パッシベーション
膜としてSiN膜を用いたAl多層配線構造において、層間
絶縁膜上の全面をSiN膜で覆い、その上に上層Al配線を
形成し、その上にパッシベーション膜としてのSiN膜を
形成するようにしたので、製造時、最終工程でパッシベ
ーション膜（SiN膜）を形成した時に、その膜質が上層A
l配線の側壁部で良くなくても、前記層間絶縁膜上の全
面にあらかじめ形成してあるSiN膜によって、層間絶縁
膜からの局部的な水分放出、それに伴う層間絶縁膜の局
部的な膜収縮を防止でき、延いては上層Al配線上のAlボ
イドの発生を防止できる。したがって、信頼性の高いAl
多層配線構造を得ることができる。(Effects of the Invention) As described above in detail, according to the present invention, in an Al multilayer wiring structure using a normal-pressure CVD insulating film as an interlayer insulating film and an SiN film as a passivation film, Since the entire surface is covered with a SiN film, an upper layer Al wiring is formed on it, and a SiN film as a passivation film is formed on it, so when the passivation film (SiN film) is formed in the final process during manufacturing , Its film quality is upper layer A
l Even if the side wall of the wiring is not good, the pre-formed SiN film over the entire surface of the interlayer insulating film causes local moisture release from the interlayer insulating film and accompanying local film shrinkage of the interlayer insulating film. This can prevent the occurrence of Al voids on the upper Al wiring. Therefore, reliable Al
A multilayer wiring structure can be obtained.
第１図はこの発明の半導体素子のAl多層配線構造の一実
施例を示す断面図、第２図はAlボイドを説明するための
斜視図、第３図はAlボイドの発生理由を説明するための
断面図である。 21……下地層、22……第１層Al配線、23……常圧CVD系
絶縁膜、24……プラズマCVD SiN膜、25……第２層Al配
線、26……プラズマCVD SiN膜。FIG. 1 is a cross-sectional view showing an embodiment of an Al multilayer wiring structure of a semiconductor device according to the present invention, FIG. 2 is a perspective view for explaining Al voids, and FIG. 3 is for explaining the reason for the occurrence of Al voids. FIG. 21 ... Underlayer, 22 ... First layer Al wiring, 23 ... Normal pressure CVD insulating film, 24 ... Plasma CVD SiN film, 25 ... Second layer Al wiring, 26 ... Plasma CVD SiN film.
Claims (1)
と、 （ｂ）この第１のAl配線上に形成された常圧CVD系絶縁
膜と、 （ｃ）この常圧CVD系絶縁膜上に形成された第１のシリ
コン窒化膜と、 （ｄ）この第１のシリコン窒化膜上に形成された第２の
Al配線と、 （ｅ）この第２のAl配線上に形成された第２のシリコン
窒化膜あるいはシリコン窒化膜を含む多層膜 とを具備してなる半導体素子のAl多層配線構造。(A) a first Al wiring formed on a base layer; (b) a normal pressure CVD insulating film formed on the first Al wiring; and (c) a normal pressure CVD insulating film. A first silicon nitride film formed on the CVD insulating film; and (d) a second silicon nitride film formed on the first silicon nitride film.
An Al multilayer wiring structure of a semiconductor device comprising: an Al wiring; and (e) a second silicon nitride film or a multilayer film including a silicon nitride film formed on the second Al wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21868289A JP2820281B2 (en) | 1989-08-28 | 1989-08-28 | A1 Multilayer wiring structure of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21868289A JP2820281B2 (en) | 1989-08-28 | 1989-08-28 | A1 Multilayer wiring structure of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0383340A JPH0383340A (en) | 1991-04-09 |
| JP2820281B2 true JP2820281B2 (en) | 1998-11-05 |
Family
ID=16723768
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21868289A Expired - Lifetime JP2820281B2 (en) | 1989-08-28 | 1989-08-28 | A1 Multilayer wiring structure of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2820281B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2438206B (en) * | 2006-01-23 | 2009-02-04 | Lotus Car | A two-stroke internal combustion engine with variable compression ratio and an exhaust port shutter |
| JP2017005227A (en) | 2015-06-16 | 2017-01-05 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method of the same |
-
1989
- 1989-08-28 JP JP21868289A patent/JP2820281B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0383340A (en) | 1991-04-09 |
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