JPH03252155A - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPH03252155A JPH03252155A JP5059690A JP5059690A JPH03252155A JP H03252155 A JPH03252155 A JP H03252155A JP 5059690 A JP5059690 A JP 5059690A JP 5059690 A JP5059690 A JP 5059690A JP H03252155 A JPH03252155 A JP H03252155A
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- ceramic substrate
- plating
- bonding
- melting point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000000919 ceramic Substances 0.000 claims abstract description 27
- 238000007747 plating Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000004020 conductor Substances 0.000 claims abstract description 16
- 239000011521 glass Substances 0.000 claims abstract description 14
- 238000002844 melting Methods 0.000 claims abstract description 11
- 230000008018 melting Effects 0.000 claims description 7
- 239000000463 material Substances 0.000 abstract description 13
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 229910052759 nickel Inorganic materials 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000005355 lead glass Substances 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000001914 filtration Methods 0.000 description 2
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は、ピングリッドアレイ等の半導体パッケージ
に関し、詳しくはヒートシンクとセラミック基板°を接
合してなる半導体パッケージに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor package such as a pin grid array, and more particularly to a semiconductor package formed by bonding a heat sink and a ceramic substrate.
［従来の技術］
近時、半導体素子の高密度化、高集積化にともないその
発熱量が増大し、半導体素子を正常に作動させるために
、その発熱をいかに効率よく放熱するかが検討課題とな
っている。その有力な方法として、高熱伝導性のＣｕ−
Ｗ、Ｃｕ−Ｍｏ等のヒートシンク材に必要なメッキを備
えたヒートシンクをセラミック基板にＡｇろ−付けする
構造がある６第２図は、従来例のＡｇろ−付けによる半
導体パッケージである。図において、セラミック基板１
０には、セラミック１にＷメタライズ等の導体配線４が
備えられ、その導体配線の内部表面の露出部にＮｉメッ
キが施されている。さらにスルーホールを通して外部表
面に導体配線を導出している。その導出部にピングリッ
ドアレイ等のビン９はＡｇろ−（図示せず）で接合され
ることにより備えられる。一方、半導体素子搭載部とな
るヒートシンク材２はセラミック基板１０の一方の主面
にＡｇろ−８で接合されて備えられる。[Prior Art] Recently, as semiconductor devices have become denser and more highly integrated, the amount of heat generated has increased, and it has become an issue to consider how to efficiently dissipate this heat in order to allow semiconductor devices to operate properly. It has become. As a promising method, Cu-
There is a structure in which a heat sink provided with the necessary plating for a heat sink material such as W or Cu-Mo is attached to a ceramic substrate with Ag braze.6 FIG. 2 shows a conventional semiconductor package using Ag braze. In the figure, ceramic substrate 1
0, a ceramic 1 is provided with a conductor wiring 4 such as W metallization, and the exposed portion of the inner surface of the conductor wiring is plated with Ni. Furthermore, conductor wiring is led out to the external surface through a through hole. A pin 9 such as a pin grid array is connected to the lead-out portion by an Ag groove (not shown). On the other hand, a heat sink material 2 serving as a semiconductor element mounting portion is bonded to one main surface of the ceramic substrate 10 with an Ag groove 8.
導体配線の内部表面の露出部、Ａｇろ−で接合されるピ
ンおよびヒートシンク材のそれぞれの表面は、Ｎｉメッ
キされ、その上にＡｕメッキされる。（ただし、ピンの
メッキは図示せず、） 次いで、メッキ導通パターンを
カットし、ショート・リーク検査等をして半導体パッケ
ージとなる。The exposed inner surface of the conductor wiring, the pins to be joined with the Ag groove, and the surfaces of the heat sink material are each plated with Ni and then with Au. (However, the plating of the pins is not shown in the figure.) Next, the plating conductive pattern is cut and a short/leak test is performed to complete the semiconductor package.
［発明が解決しようとする課題］
しかし、従来法による半導体パッケージは、次のような
課題がある。（１）熱膨張係数は、セラミックが約７
Ｘｌ０−６／”Ｃ１Ｃｕ−Ｗ等のヒートンク材が約６
Ｘｌ０−６／’Ｃで、両者は同程度であるが、Ａｇろ−
が約２０Ｘ １０−６／”Ｃと極めて高く、またＡｇろ
−の接合のための加熱温度は約８６０℃と高いので、ス
トレスによる残留応力が内在して、接合不良の原因とな
る。［２１Ａｇろ−の腐食防止のためヒートシンク材表
面およびＡｇろ一部は露出面にＡｕメッキが必要である
。[Problems to be Solved by the Invention] However, the conventional semiconductor package has the following problems. (1) The thermal expansion coefficient of ceramic is approximately 7.
Heat tank material such as Xl0-6/”C1Cu-W is approximately 6
At Xl0-6/'C, both are at the same level, but Agro-
is extremely high at about 20X 10-6/''C, and the heating temperature for bonding Ag filters is as high as about 860℃, so residual stress due to stress is inherent and causes bonding failure. [21Ag In order to prevent corrosion of the filter, Au plating is required on the exposed surface of the heat sink material surface and a portion of the Ag filter.
以上のため、ヒートシンクとセラミック基板の接合に、
Ａｇろ−に替わり、接合のための加熱温度がより低くか
つ経済的な接合材を用いた半導体パッケージの提供を目
的とする。For the above reasons, for bonding the heat sink and ceramic substrate,
The purpose of the present invention is to provide a semiconductor package that uses an economical bonding material that requires lower heating temperatures for bonding instead of Ag filters.
［課題を解決するための手段］
上述の課題を解決するため、本発明は導体配線および該
導体配線の露出部を被膜するメッキ、を備えたセラミッ
ク基板と、Ｎｉ、ＣｏまたはＣｒの１種または２種以上
のメッキを備えたヒートシンクとを低融点ガラスで接合
したことを特徴とする半導体パッケージである。[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides a ceramic substrate having conductor wiring and plating for coating the exposed portion of the conductor wiring, and one or more of Ni, Co, or Cr. This is a semiconductor package characterized by bonding a heat sink with two or more types of plating using low melting point glass.
［作用］
上記の構成の低融点ガラスによる接合の作用は、（１）
低融点ガラスは熱膨張係数が約６ Ｘｌ０−６／”Ｃと
セラミック基板のセラミックおよびヒートシンク材とほ
ぼ一致しているので、接合面の残留応力が小さい。 （
２）従来、サーディプで使用された低融点ガラスであり
、入手は容易で、信頼性も安定したシール材である。
（３１接合のためのガラス層の形成は、セラミック基
板の一面に印刷する方法、プリフォームしたガラスフィ
ルムを用いる方法等で容易である。（４１接合のための
加熱温度は約４５０℃と低温であり、メッキ層の信頼性
を損なうことがない。 （（５）Ａｇろ一法では錆防止
のためにＡｕメッキを必要としたが、接合温度が比較的
低いので必要がない。[Effect] The effect of bonding using the low melting point glass of the above configuration is (1)
Low melting point glass has a coefficient of thermal expansion of about 6 Xl0-6/''C, which is almost the same as the ceramic of the ceramic substrate and the heat sink material, so the residual stress on the bonding surface is small. (
2) It is a low melting point glass conventionally used in cerdip, is easily available, and is a reliable and stable sealing material.
(The formation of the glass layer for 31 bonding is easy by printing on one side of a ceramic substrate, using a preformed glass film, etc.) (The heating temperature for 41 bonding is as low as approximately 450°C. (5) The Ag filtration method required Au plating to prevent rust, but since the bonding temperature is relatively low, it is not necessary.
ヒートシンク材にＮｉ、 ＣｏまたはＣｒの１ｍｔなは
２種以上のヒートシンク用メッキ６を備える理由は、ヒ
ートシンク材の錆の発生を防ぐためで、それらの酸化膜
により金属の不動態膜が形成される。The reason why the heat sink material is provided with two or more types of heat sink plating 6 of 1 m thick of Ni, Co, or Cr is to prevent the heat sink material from rusting, and their oxide films form a metal passive film. .
その酸化膜は、ガラスに対して濡れ性がよい。The oxide film has good wettability to glass.
［実施例］ 以下実施例について、図面を参照して説明する。[Example] Examples will be described below with reference to the drawings.
第１図は本発明の一実施例を示した断面図である。セラ
ミック基板１０は、セラミック１にＷメタライズ等によ
る導体配線４が備えられ、さらにスルーホールを通して
外部表面に導体配線４が導出されている。その導出部に
ピングリドアレイ等のピン９がＡｇろ一接合（Ａｇろ一
部は図示せず）して備えられる。その導体配線の内部表
面の露出部およびピン表面（Ａｇろ一部は図示していな
いがそれを含む）には、後工程でＮｉメッキおよびＡｕ
メッキのメッキ３が施される（ピンへのメッキは図示せ
ず）。そして、メッキ導通パターンをカットし、ショー
ト・リーク検査し準備される。FIG. 1 is a sectional view showing an embodiment of the present invention. In the ceramic substrate 10, a ceramic 1 is provided with a conductor wiring 4 made of W metallization or the like, and the conductor wiring 4 is further led out to the external surface through a through hole. A pin 9 such as a pin grid array is connected to the lead-out portion of the pin 9 by an Ag filter (a portion of the Ag filter is not shown). The exposed internal surface of the conductor wiring and the pin surface (including the Ag filter part not shown) will be plated with Ni and Au in a later process.
Plating 3 is applied (the plating on the pin is not shown). Then, the plated conductive pattern is cut, shorts and leaks are inspected, and preparations are made.
一方、ヒートシンク１１は、ヒートシンク材２の表面に
、Ｎｉ、 ＣｏまたはＣｒの１種丈たは２種以上のヒー
トシンク用メッキ６が常法によりメッキし準備される。On the other hand, the heat sink 11 is prepared by plating the surface of the heat sink material 2 with one or more types of heat sink plating 6 of Ni, Co, or Cr using a conventional method.
上記のセラミック基板１０とヒートシンク１１は、ホウ
ケイ酸鉛ガラス等の低融点ガラス７を必要部分に塗布し
、次いで、約４５０℃に加熱して接合され半導体パッケ
ージとなる。The above ceramic substrate 10 and heat sink 11 are bonded together by applying low-melting glass 7 such as lead borosilicate glass to the necessary parts and then heating to about 450° C. to form a semiconductor package.
本発明は、経済的に安価にできる利点も有する。The invention also has the advantage of being economically inexpensive.
すなわち、高価なヒートシンク１１の接合が、検査され
た良品のセラミック基板１０との接合であるので、ヒー
トシンクを効率よく利用できる。That is, since the expensive heat sink 11 is bonded to the inspected non-defective ceramic substrate 10, the heat sink can be used efficiently.
［発明の効果］
本発明は、以上の説明のように、ヒートシンクとセラミ
ック基板との接合にサーブイブ用の低融点ガラスを用い
るため、従来法のＡｇろ一法の接合に比し、ヒートシン
ク材に防錆のための高価なＡｕメッキを施すことなく、
また熱膨張係数がセラミックおよびヒートシンクの両方
にほぼマツチしているため、接合後の残留応力が少なく
、品質および製造コスト面から極め優れた高放熱性で高
信頼性の半導体パッケージを提供できる効果がある。[Effects of the Invention] As described above, the present invention uses a low melting point glass for serveve to bond the heat sink and the ceramic substrate, so compared to the conventional bonding method using Ag filtration, the heat sink material is Without expensive Au plating for rust prevention,
In addition, because the coefficient of thermal expansion almost matches both the ceramic and the heat sink, there is little residual stress after bonding, making it possible to provide semiconductor packages with high heat dissipation and high reliability that are extremely superior in terms of quality and manufacturing cost. be.
第１図は本発明の一実施例の半導体パッケージの断面図
である。第２図は従来例の半導体パッケージの断面図で
ある。
１・・・セラミック、２・・・ヒートシンク材、３・・
・ＮｉメッキおよびＡｕメッキ、４・・・導体配線、６
・・・ヒートシンク用メッキ、７・・・低融点ガラス、
８・・・Ａｇろ−９・・・ピン、１０・・・セラミック
基板、１１・・・ヒートシンク。FIG. 1 is a sectional view of a semiconductor package according to an embodiment of the present invention. FIG. 2 is a sectional view of a conventional semiconductor package. 1... Ceramic, 2... Heat sink material, 3...
・Ni plating and Au plating, 4... Conductor wiring, 6
...Plating for heat sink, 7...Low melting point glass,
8... Agro-9... Pin, 10... Ceramic board, 11... Heat sink.
Claims (1)
導体パッケージにおいて、導体配線および該導体配線の
露出部を被膜するメッキを備えたセラミック基板と、Ｎ
ｉ、ＣｏまたはＣｒの１種または２種以上のメッキを備
えたヒートシンクとを低融点ガラスで接合したことを特
徴とする半導体パッケージ。(1) In a semiconductor package formed by bonding a heat sink and a ceramic substrate, the ceramic substrate includes a conductor wiring and plating that covers the exposed portion of the conductor wiring;
1. A semiconductor package comprising a heat sink plated with one or more of i, Co, or Cr and bonded with low melting point glass.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5059690A JPH03252155A (en) | 1990-02-28 | 1990-02-28 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5059690A JPH03252155A (en) | 1990-02-28 | 1990-02-28 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03252155A true JPH03252155A (en) | 1991-11-11 |
Family
ID=12863356
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5059690A Pending JPH03252155A (en) | 1990-02-28 | 1990-02-28 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03252155A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5719433A (en) * | 1995-07-25 | 1998-02-17 | Thomson-Csf | Semiconductor component with integrated heat sink |
| US5828126A (en) * | 1992-06-17 | 1998-10-27 | Vlsi Technology, Inc. | Chip on board package with top and bottom terminals |
| US6392309B1 (en) * | 1995-08-25 | 2002-05-21 | Sony Corporation | Semiconductor device including solid state imaging device |
| JP2011210911A (en) * | 2010-03-30 | 2011-10-20 | Nippon Electric Glass Co Ltd | Method for manufacturing semiconductor light emitting element device |
| US11175249B2 (en) | 2017-11-07 | 2021-11-16 | Netzsch Japan K.K. | Physical property value measurement device, physical property value measurement method, and recording medium |
-
1990
- 1990-02-28 JP JP5059690A patent/JPH03252155A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5828126A (en) * | 1992-06-17 | 1998-10-27 | Vlsi Technology, Inc. | Chip on board package with top and bottom terminals |
| US5719433A (en) * | 1995-07-25 | 1998-02-17 | Thomson-Csf | Semiconductor component with integrated heat sink |
| US6392309B1 (en) * | 1995-08-25 | 2002-05-21 | Sony Corporation | Semiconductor device including solid state imaging device |
| JP2011210911A (en) * | 2010-03-30 | 2011-10-20 | Nippon Electric Glass Co Ltd | Method for manufacturing semiconductor light emitting element device |
| US11175249B2 (en) | 2017-11-07 | 2021-11-16 | Netzsch Japan K.K. | Physical property value measurement device, physical property value measurement method, and recording medium |
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