JP2564827B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2564827B2 JP2564827B2 JP62149534A JP14953487A JP2564827B2 JP 2564827 B2 JP2564827 B2 JP 2564827B2 JP 62149534 A JP62149534 A JP 62149534A JP 14953487 A JP14953487 A JP 14953487A JP 2564827 B2 JP2564827 B2 JP 2564827B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- semiconductor device
- semiconductor substrate
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明はフリップチップ方式により実装された半導体
装置に関し、特に配線保護用絶縁膜に起因する不良を低
減したフリップチップ実装半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounted by a flip chip method, and more particularly to a flip chip mounting semiconductor device in which defects due to a wiring protection insulating film are reduced.
［従来の技術］ IC実装技術において半導体基板と配線基板とをフリッ
プチップ技術により接続するようにした半導体装置（以
下フリップチップICという）が知られている。この装置
は半導体基板の配線保護用絶縁膜（以下パッシベーショ
ン膜という）の上に形成された外部出力用電極部材（以
下コンタクト電極という）と配線基板の配線電極層とを
ハンダにより接続するものであり、コンタクト電極に突
起電極（バンプ）を設けたバンプ方式と、配線電極層を
盛上げたペデスタル方式とがある。[Prior Art] There is known a semiconductor device (hereinafter referred to as a flip chip IC) in which a semiconductor substrate and a wiring substrate are connected by a flip chip technique in the IC mounting technique. This device connects an external output electrode member (hereinafter referred to as a contact electrode) formed on a wiring protection insulating film (hereinafter referred to as a passivation film) of a semiconductor substrate and a wiring electrode layer of a wiring substrate by soldering. There are a bump method in which a bump electrode is provided on the contact electrode and a pedestal method in which a wiring electrode layer is raised.
フリップチップICの上記パッシベーション膜としては
一般に、CVD法又はPVD法により形成された酸化シリコン
膜、窒化シリコン膜などの無機絶縁膜（無機絶縁堆積膜
という）が使用されていた。また、本出願人の出願によ
る特開昭61年121456号公報は上記パッシベーション膜と
してポリイミド膜またはPSG膜を使用するフリップフロ
ップICを開示している。As the passivation film of the flip chip IC, an inorganic insulating film (referred to as an inorganic insulating deposition film) such as a silicon oxide film or a silicon nitride film formed by a CVD method or a PVD method is generally used. Further, Japanese Patent Application Laid-Open No. 121456/1986 filed by the present applicant discloses a flip-flop IC using a polyimide film or a PSG film as the passivation film.
［解決を必要とする問題点］ ところが上記無機パッシベーション膜を使用するフリ
ップチップICにおいては、ハンダをリフローする時の熱
ストレスにより、上記無機パッシベーション膜に縦方向
にクラック（以下縦クロックという。）が発生する問題
があった。上記縦クラックは縦方向に隣接する２層の電
極（たとえばコンタクト電極とその下にパッシベーショ
ン膜を介して隣接する電極層）間をショートしたり、電
極層を断線したり、その他耐久性劣化の原因になるので
極力防止する必要がある。[Problems Requiring Solution] However, in the flip-chip IC using the inorganic passivation film, a crack (hereinafter referred to as a vertical clock) is vertically generated in the inorganic passivation film due to thermal stress when reflowing the solder. There was a problem that occurred. The vertical cracks cause a short circuit between two layers of electrodes vertically adjacent to each other in the vertical direction (for example, a contact electrode and an electrode layer adjacent to the contact electrode via a passivation film), disconnection of the electrode layer, and other causes of deterioration of durability. Therefore, it is necessary to prevent it as much as possible.
上記縦クラックの発生問題を以下に説明する。 The problem of occurrence of the vertical crack will be described below.
ハンダのリフローは過剰にリフローさせないために比
較的短時間に実施されるので半導体基板上に金属配線電
極（たとえばコンタクト電極やその上のバリヤー電極）
周辺は急速な温度変化により大きな熱ストレスを発生
し、その結果それに接する無機パッシベーション膜に縦
クラックが発生する。たとえば無機パッシベーション膜
として窒化シリコン膜を使用する時に、その熱膨張係数
は1.8×10-6/Kであり、メタル電極の熱膨張率は大抵２
×10-5/Kであり、メタル電極の熱膨張率は大抵２×10-6
゜K-1であり約１桁異なる。Solder reflow is performed in a relatively short time in order to prevent excessive reflow, so metal wiring electrodes (for example, contact electrodes and barrier electrodes above them) are formed on the semiconductor substrate.
A large thermal stress is generated in the periphery due to a rapid temperature change, and as a result, a vertical crack is generated in the inorganic passivation film in contact with it. For example, when a silicon nitride film is used as the inorganic passivation film, its coefficient of thermal expansion is 1.8 × 10 -6 / K, and the coefficient of thermal expansion of the metal electrode is usually 2
× 10 -5 / K, the coefficient of thermal expansion of the metal electrode is usually 2 × 10 -6
K ° -1 , which differs by about one digit.
またフリップチップICのパッシベーション膜としてポ
リイミド膜などの耐熱樹脂膜を使用する場合、上記ポリ
イミド膜は無機絶縁膜に比較して大きい熱膨張係数を持
つので、上記ハンダの加熱リフロー時にポリイミド膜が
伸縮して、配線基板とシリコン基板とに実質的に固定さ
れているハンダ接続部分を破壊したり基板に形成された
半導体素子自体を破壊したりする場合があった。たとえ
ば、一般にPIQ膜として知られている低熱膨張性膜を使
用する場合、その熱膨張係数は4.5×10-6/Kであり、配
線基板として一般に使用されるアルミナ基板の熱膨張係
数は６×10-6/Kであり、シリコン基板の熱膨張係数は3.
5×10-6/Kであり、それぞれ大幅に異なる。また、ポリ
イミド膜などの耐熱性樹脂膜は無機絶縁堆積膜に比べて
吸湿性が大きいことが良く知られている。When a heat-resistant resin film such as a polyimide film is used as the passivation film of the flip chip IC, the polyimide film has a larger coefficient of thermal expansion than the inorganic insulating film, and therefore the polyimide film expands or contracts during the heat reflow of the solder. In some cases, the solder connection portion that is substantially fixed to the wiring substrate and the silicon substrate may be destroyed, or the semiconductor element itself formed on the substrate may be destroyed. For example, when a low thermal expansion film generally known as a PIQ film is used, its thermal expansion coefficient is 4.5 × 10 −6 / K, and an alumina substrate generally used as a wiring board has a thermal expansion coefficient of 6 ×. It is 10 -6 / K, and the thermal expansion coefficient of silicon substrate is 3.
It is 5 × 10 -6 / K, which are significantly different. It is well known that a heat-resistant resin film such as a polyimide film has a higher hygroscopic property than an inorganic insulating deposited film.
また、PSG膜などの低融点ガラス膜をパッシベーショ
ン膜として使用するフリップチップICも可能であるが、
工程が複雑であり量産性に劣るという問題をもってい
る。A flip-chip IC that uses a low melting point glass film such as a PSG film as a passivation film is also possible.
It has a problem that the process is complicated and mass productivity is poor.
従って本発明は上記問題を改善し、封止能力が高く配
線不良の少ないパッシベーション膜をもつフリップチッ
プICを提供することを目的とする。Therefore, it is an object of the present invention to provide a flip chip IC having a passivation film having a high sealing ability and a few wiring defects, by improving the above problems.
［問題点を解決するための手段］ 本発明の半導体装置は、半導体素子が形成された一主
表面上に配線保護用絶縁膜をもち上記保護用絶縁膜上に
外部出力用電極部材をもつ半導体基板と、上記半導体基
板と対向して配置され配線電極層をもつ配線基板と、上
記外部出力用電極部材と上記配線電極層とを直接にまた
はバンプを介して接続するハンダと、をもつ半導体装置
において、上記配線保護用絶縁膜は耐熱性樹脂膜とその
上に形成された無機絶縁堆積膜とを備えるように構成さ
れている。[Means for Solving the Problems] A semiconductor device of the present invention is a semiconductor having an insulating film for wiring protection on one main surface on which a semiconductor element is formed and an electrode member for external output on the insulating film for protection. A semiconductor device having a substrate, a wiring substrate arranged to face the semiconductor substrate and having a wiring electrode layer, and solder for connecting the external output electrode member to the wiring electrode layer directly or via bumps. In the above, the wiring protection insulating film is configured to include a heat resistant resin film and an inorganic insulating deposition film formed thereon.
また、本発明の半導体装置の製造方法は、半導体素子
が形成された一主表面上に配線保護用絶縁膜をもち上記
配線保護用絶縁膜上に外部出力用電極部材をもつ半導体
基板と、上記半導体基板と対向して配置され配線電極層
をもつ配線基板と、上記外部出力用電極部材と上記配線
電極層とを直接にまたはバンプを介して接続するハンダ
とをもつ半導体装置において、 耐熱性樹脂膜の形成後、上記耐熱性樹脂膜上に堆積に
より無機絶縁堆積膜を形成して上記配線保護用絶縁膜と
なすことを特徴としている。Further, the method for manufacturing a semiconductor device of the present invention includes a semiconductor substrate having an insulating film for wiring protection on one main surface on which a semiconductor element is formed and an electrode member for external output on the insulating film for wiring protection, In a semiconductor device having a wiring substrate arranged facing a semiconductor substrate and having a wiring electrode layer, and solder for connecting the external output electrode member and the wiring electrode layer directly or via bumps, a heat-resistant resin After the film is formed, an inorganic insulating deposition film is formed on the heat resistant resin film by deposition to form the wiring protection insulating film.
なお、上記無機絶縁堆積膜とは、CVD法やPVD法など無
機物質のガス状物の堆積により形成された絶縁膜をいう
ものとする。The inorganic insulating deposited film means an insulating film formed by depositing a gaseous substance of an inorganic substance such as a CVD method or a PVD method.
［作用］ 本発明の半導体装置及びその製造方法によれば、半導
体基板と配線基板とをハンダのリフローにより接続する
時に、下層パッシベーション膜であり大きな熱膨張率を
もつ耐熱性樹脂膜（たとえばポリイミド膜）の熱膨張
は、その上に堆積され小さな熱膨張率をもつ上層パッシ
ベーション膜（たとえば酸化シリコン膜または窒化シリ
コン膜）により良好に抑圧される。[Operation] According to the semiconductor device and the method of manufacturing the same of the present invention, when the semiconductor substrate and the wiring substrate are connected by solder reflow, a heat-resistant resin film (for example, a polyimide film) that is a lower passivation film and has a large coefficient of thermal expansion. 2) is well suppressed by an upper passivation film (for example, a silicon oxide film or a silicon nitride film) deposited thereon and having a small coefficient of thermal expansion.
更に、下層パッシベーション膜である耐熱樹脂膜の吸
湿は上層パッシベーション膜である無機絶縁膜により防
止され、逆に上層パッシベーション膜である無機絶縁膜
のクラックは下層パッシベーション膜である耐熱樹脂膜
により封止される。Further, moisture absorption of the heat resistant resin film which is the lower layer passivation film is prevented by the inorganic insulating film which is the upper layer passivation film, and conversely cracks in the inorganic insulating film which is the upper layer passivation film are sealed by the heat resistant resin film which is the lower layer passivation film. It
［効果］ 上記説明したように、本発明の半導体装置及び本発明
の製造装置により製造された半導体装置はフリップチッ
プICの配線保護のために、耐熱樹脂膜である下層パッシ
ベーション膜と無機絶縁膜である上層パッシベーション
膜とを備えているので、ハンダのリフロー時に発生する
下層パッシベーション膜の熱膨張を、下層パッシベーシ
ョン膜の下の絶縁膜と上層パッシベーション膜とのサン
ドイッチ構造により良好に抑止でき、半導体基板と配線
基板とに固定されているハンダなどの接続部の接続不良
を防止することができる。[Effects] As described above, the semiconductor device of the present invention and the semiconductor device manufactured by the manufacturing apparatus of the present invention include the lower layer passivation film and the inorganic insulating film, which are heat-resistant resin films, for the wiring protection of the flip chip IC. Since it has a certain upper layer passivation film, the thermal expansion of the lower layer passivation film that occurs during solder reflow can be effectively suppressed by the sandwich structure of the insulating film below the lower layer passivation film and the upper layer passivation film. It is possible to prevent the connection failure of the connection part such as solder fixed to the wiring board.
また、下層パッシベーション膜の吸湿を上層パッシベ
ーション膜により防止し、上層パッシベーション膜のク
ラックを下層パッシベーション膜により封止できる。従
って本発明によれば、高い配線保護能力をもち接続不良
の少ないフリップチップICを製造することができる。Further, moisture absorption of the lower layer passivation film can be prevented by the upper layer passivation film, and cracks in the upper layer passivation film can be sealed by the lower layer passivation film. Therefore, according to the present invention, it is possible to manufacture a flip-chip IC having a high wiring protection ability and few connection failures.
［実施例］ 実施例１ 本発明のフリップチップICの１実施例模式図を第１図
に示し、ハンダバンプ２の周辺部の拡大断面図を第２図
に示す。[Embodiment] Embodiment 1 A schematic view of an embodiment of a flip chip IC of the present invention is shown in FIG. 1, and an enlarged cross-sectional view of a peripheral portion of a solder bump 2 is shown in FIG.
本発明装置は、半導体基板１と、それと対向して配置
された配線基板２と、半導体基板１のコンタクト電極14
と配線基板２の配線電極層22とをフエイスダウン接続す
るハンダバンプ３とからなる。The device of the present invention comprises a semiconductor substrate 1, a wiring substrate 2 arranged to face the semiconductor substrate 1, and a contact electrode 14 of the semiconductor substrate 1.
And a solder bump 3 for connecting the wiring electrode layer 22 of the wiring substrate 2 in a face-down manner.
半導体基板１は、Ｐ形シリコン基板11と、その表面に
LOCOS酸化法により形成された0.6μｍ厚の酸化シリコン
膜12と、酸化シリコン膜12を選択的に開孔して基板11の
表面にドープされたN+領域13と、N+領域13と酸化シリコ
ン膜12上に真空蒸着またはスパッタリングで形成された
0.3μｍ厚のアルミ電極線（コンタクト電極）14と、そ
の上に形成された0.8μｍ厚のポリイミド膜15と、その
上にプラズマCVD法により堆積された0.4μｍ厚の窒化シ
リコン膜16とからなり、更にポリイミド膜15及び酸化シ
リコン膜16の開孔部18にコンタクト電極14に接続される
ように形成されたバリヤメタル電極17をもつ。The semiconductor substrate 1 includes a P-type silicon substrate 11 and a surface thereof.
A 0.6μm silicon oxide film 12 having a thickness which is formed by the LOCOS oxidation method, oxidation with N + region 13 doped to a surface of the substrate 11 a silicon oxide film 12 are selectively opening, the N + region 13 Silicon Formed on the film 12 by vacuum evaporation or sputtering
It is composed of an aluminum electrode wire (contact electrode) 14 having a thickness of 0.3 μm, a polyimide film 15 having a thickness of 0.8 μm formed thereon, and a silicon nitride film 16 having a thickness of 0.4 μm deposited thereon by a plasma CVD method. Further, a barrier metal electrode 17 formed so as to be connected to the contact electrode 14 is provided in the opening 18 of the polyimide film 15 and the silicon oxide film 16.
バリアメタル電極17は基板側から順番にCr、Cu、Auの
順に形成された複層電極であり、真空蒸着またはスパッ
タリングで形成されるものである。The barrier metal electrode 17 is a multilayer electrode in which Cr, Cu, and Au are sequentially formed from the substrate side, and is formed by vacuum vapor deposition or sputtering.
ポリイミド膜15はスピンコートして400℃で硬化させ
たものある。The polyimide film 15 is spin-coated and cured at 400 ° C.
上記開孔部（コンタクトホール）18はまずフォトレジ
ストマスクにより窒化シリコン膜16を選択エッチング
し、次に窒化シリコン膜16をマスクとしてポリイミド膜
15を選択エッチングして開孔されている。The opening portion (contact hole) 18 is formed by first selectively etching the silicon nitride film 16 with a photoresist mask, and then with the silicon nitride film 16 as a mask.
15 are selectively etched and opened.
配線基板２は、アルミナ基板21の表面に真空蒸着また
はスパッタリングで形成されたアルミ配線電極層22をも
つ。The wiring board 2 has an aluminum wiring electrode layer 22 formed on the surface of an alumina substrate 21 by vacuum vapor deposition or sputtering.
ハンダバンブ３は、バリアメタル電極17の上にメッキ
法により形成されるものである。The solder bump 3 is formed on the barrier metal electrode 17 by a plating method.
半導体基板１と配線基板２とを接続するには、それら
を対向させて所定位置に保持しつつリフロー用加熱炉中
で約250℃、数十秒間保持することによりハンダバンプ
３をリフローさせ、その後で上記真空加熱炉から取出し
て冷却し、両基板を結合すればよい。In order to connect the semiconductor substrate 1 and the wiring substrate 2, the solder bumps 3 are reflowed by holding them in a reflow heating furnace at about 250 ° C. for several tens of seconds while holding them facing each other at a predetermined position. It suffices to take out from the vacuum heating furnace, cool it, and bond both substrates.
なお本実施例のフリップチップICにおいて、上層パッ
シベーション膜は窒化シリコン膜16に限定されず、耐熱
樹脂膜よりも小さい熱膨張係数をもつ多くの無機絶縁膜
を使用できる。たとえば、減圧CVD法により400℃で酸化
シリコン膜を堆積することも可能である。In the flip-chip IC of this embodiment, the upper passivation film is not limited to the silicon nitride film 16, and many inorganic insulating films having a smaller thermal expansion coefficient than the heat resistant resin film can be used. For example, it is possible to deposit a silicon oxide film at 400 ° C. by the low pressure CVD method.
また、ハンダバンプ３は他のバンプを介してバリヤメ
タル電極に接続してもよい。Further, the solder bump 3 may be connected to the barrier metal electrode via another bump.
第１図は本発明のフリップチップ実装半導体装置の１実
施例模式図である。第２図は第１図図示装置の拡大断面
図である。 １……半導体基板 ２……配線基板 ３……ハンダバンプ（ハンダ）FIG. 1 is a schematic view of one embodiment of a flip chip mounting semiconductor device of the present invention. FIG. 2 is an enlarged sectional view of the apparatus shown in FIG. 1 ... Semiconductor substrate 2 ... Wiring substrate 3 ... Solder bump (solder)
───────────────────────────────────────────────────── フロントページの続き (72)発明者 真山 恵次 刈谷市昭和町１丁目１番地 日本電装株 式会社内 (56)参考文献 特開 昭60−180147（ＪＰ，Ａ) 特開 昭62−57223（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Keiji Mayama 1-1, Showamachi, Kariya city Nippon Denso Co., Ltd. (56) References JP-A-60-180147 (JP, A) JP-A-62- 57223 (JP, A)
Claims (4)
保護用絶縁膜をもち上記配線保護用絶縁膜上に外部出力
用電極部材をもつ半導体基板と、上記半導体基板と対向
して配置され配線電極層をもつ配線基板と、上記外部出
力用電極部材と上記配線電極層とを直接にまたはバンプ
を介して接続するハンダとをもつ半導体装置において、 上記配線保護用絶縁膜は、耐熱性樹脂膜とその上に形成
された無機絶縁堆積膜とで構成されていることを特徴と
する半導体装置。1. A semiconductor substrate having a wiring protection insulating film on one main surface on which a semiconductor element is formed and having an external output electrode member on the wiring protection insulating film, and the semiconductor substrate is arranged so as to face the semiconductor substrate. In a semiconductor device having a wiring board having a wiring electrode layer and solder for connecting the external output electrode member and the wiring electrode layer directly or via bumps, the wiring protection insulating film is heat-resistant. A semiconductor device comprising a resin film and an inorganic insulating deposition film formed thereon.
上記無機絶縁堆積膜は窒化シリコン膜である特許請求の
範囲第１項記載の半導体装置。2. The heat resistant resin film is a polyimide film,
The semiconductor device according to claim 1, wherein the inorganic insulating deposited film is a silicon nitride film.
保護用絶縁膜をもち上記配線保護用絶縁膜上に外部出力
用電極部材をもつ半導体基板と、上記半導体基板と対向
して配置され配線電極層をもつ配線基板と、上記外部出
力用電極部材と上記配線電極層とを直接にまたはバンプ
を介して接続するハンダとをもつ半導体装置の製造方法
において、 耐熱性樹脂膜の形成後、上記耐熱性樹脂膜上に堆積によ
り無機絶縁堆積膜を形成して上記配線保護用絶縁膜とな
すことを特徴とする半導体装置の製造方法。3. A semiconductor substrate having a wiring protection insulating film on one main surface on which a semiconductor element is formed and having an external output electrode member on the wiring protection insulating film, and the semiconductor substrate is arranged so as to face the semiconductor substrate. In a method for manufacturing a semiconductor device having a wiring board having a wiring electrode layer and solder for connecting the external output electrode member and the wiring electrode layer directly or via bumps, after forming a heat resistant resin film, A method for manufacturing a semiconductor device, wherein an inorganic insulating deposition film is formed on the heat resistant resin film by deposition to form the wiring protection insulating film.
積される特許請求の範囲第３項記載の半導体装置。4. The semiconductor device according to claim 3, wherein the inorganic insulating deposited film is deposited by a CVD method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62149534A JP2564827B2 (en) | 1987-06-16 | 1987-06-16 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62149534A JP2564827B2 (en) | 1987-06-16 | 1987-06-16 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63312646A JPS63312646A (en) | 1988-12-21 |
| JP2564827B2 true JP2564827B2 (en) | 1996-12-18 |
Family
ID=15477239
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62149534A Expired - Lifetime JP2564827B2 (en) | 1987-06-16 | 1987-06-16 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2564827B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01196146A (en) * | 1988-02-01 | 1989-08-07 | Matsushita Electron Corp | Semiconductor device |
| US7579681B2 (en) | 2002-06-11 | 2009-08-25 | Micron Technology, Inc. | Super high density module with integrated wafer level packages |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60180147A (en) * | 1984-02-27 | 1985-09-13 | Nippon Denso Co Ltd | Semiconductor device |
| JPS6257223A (en) * | 1985-09-06 | 1987-03-12 | Seiko Epson Corp | Manufacture of semiconductor device |
-
1987
- 1987-06-16 JP JP62149534A patent/JP2564827B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63312646A (en) | 1988-12-21 |
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