JPH058570B2 - - Google Patents
Info
- Publication number
- JPH058570B2 JPH058570B2 JP57226135A JP22613582A JPH058570B2 JP H058570 B2 JPH058570 B2 JP H058570B2 JP 57226135 A JP57226135 A JP 57226135A JP 22613582 A JP22613582 A JP 22613582A JP H058570 B2 JPH058570 B2 JP H058570B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- metal layer
- metal
- semiconductor device
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910052751 metal Inorganic materials 0.000 claims description 39
- 239000002184 metal Substances 0.000 claims description 39
- 229910000679 solder Inorganic materials 0.000 claims description 34
- 239000004065 semiconductor Substances 0.000 claims description 31
- 238000005530 etching Methods 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 238000001704 evaporation Methods 0.000 claims description 8
- 230000008020 evaporation Effects 0.000 claims description 7
- 239000010453 quartz Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 150000002739 metals Chemical class 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims description 2
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 claims 2
- 229910001120 nichrome Inorganic materials 0.000 claims 2
- 239000007789 gas Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 106
- 229910017813 Cu—Cr Inorganic materials 0.000 description 7
- 238000007740 vapor deposition Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 238000010008 shearing Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052740 iodine Inorganic materials 0.000 description 2
- 239000011630 iodine Substances 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- XZXYQEHISUMZAT-UHFFFAOYSA-N 2-[(2-hydroxy-5-methylphenyl)methyl]-4-methylphenol Chemical compound CC1=CC=C(O)C(CC=2C(=CC=C(C)C=2)O)=C1 XZXYQEHISUMZAT-UHFFFAOYSA-N 0.000 description 1
- 229910020220 Pb—Sn Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229940107816 ammonium iodide Drugs 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05557—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05563—Only on parts of the surface of the internal layer
- H01L2224/05564—Only on the bonding interface of the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明はフリツプチツプ型の半導体装置に関
し、特に半田バンプの強度の向上及び位置精度の
向上を図つた半導体装置及びその製造方法に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a flip-chip type semiconductor device, and more particularly to a semiconductor device and a method for manufacturing the same in which the strength and positional accuracy of solder bumps are improved.
フリツプチツプ型の半導体装置では、半導体基
板の表面に形成したAl配線層上に半田バンプを
形成しているが、Alと半田との接着を可能とす
るために例えばCr−Cu−Au層からなる多層の下
地層を形成し、この下地層上に半田バンプを設け
ている。この場合、前記下地層はメタルマスクを
使用した蒸着法により形成している。しかしなが
ら、この蒸着は通常250℃以上の高温条件の基で
行なつているため、メタルマスクと半導体基板と
の熱膨張係数の差等が原因となつて両者間で位置
ずれが発生してしまう。特に近年の大型ウエーハ
における処理では位置ずれ量も比例的に増大し、
所要箇所におけるバンプの高精度位置決めが困難
になつて歩留りの低下を生ずることになる。 In flip-chip semiconductor devices, solder bumps are formed on an Al wiring layer formed on the surface of a semiconductor substrate, but in order to enable adhesion between Al and solder, a multilayer bump consisting of, for example, a Cr-Cu-Au layer is used. A base layer is formed, and solder bumps are provided on this base layer. In this case, the base layer is formed by a vapor deposition method using a metal mask. However, since this vapor deposition is normally performed under high temperature conditions of 250° C. or higher, misalignment occurs between the metal mask and the semiconductor substrate due to differences in thermal expansion coefficients between the two. In particular, in the processing of large wafers in recent years, the amount of positional deviation increases proportionally.
High-precision positioning of bumps at required locations becomes difficult, resulting in a decrease in yield.
また、従来の半田バンプ構造では剪断強度に十
分なものが得がたく、剪断試験を行なつた結果で
は半田バンプ下地層のCr層と下地石英スパツタ
膜の界面剥離が発生して簡単に破断され、必要と
される剪断強度の1/3にも満たない。これは、本
発明者の検討によれば、下地層の周側面が垂直に
近い形状とされているため、剪断時の応力が下地
層周側面に集中され、下地層と半導体基板との接
着が破壊されるものと考えられる。 In addition, it is difficult to obtain sufficient shear strength with conventional solder bump structures, and the results of shear tests show that interface peeling occurs between the Cr layer of the solder bump underlying layer and the underlying quartz spatter film, resulting in easy rupture. , less than 1/3 of the required shear strength. According to the inventor's study, the circumferential side of the base layer is nearly vertical, so stress during shearing is concentrated on the circumferential side of the base layer, and the adhesion between the base layer and the semiconductor substrate is impaired. It is thought that it will be destroyed.
したがつて本発明の目的は半田バンプにおける
剪断強度の向上を図ると共に位置精度の向上を図
ることができ、これにより信頼性及び歩留りの向
上を達成することができる半導体装置の製造方法
を提供することにある。 SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device that can improve the shear strength of solder bumps and improve positional accuracy, thereby improving reliability and yield. There is a particular thing.
本発明に係る半導体装置の製造方法は、半導体
基板の表面に金属配線層を形成し、上記金属配線
層上を含む上記半導体基板上に絶縁層を形成し、
上記絶縁層の選択エツチングにより上記金属配線
層の所定部分を露呈し、次に、互いに異なる金属
の順次の蒸着によつて多層構造の下地層を形成
し、上記下地層上の半田バンプ形成位置にホトレ
ジスト層を形成し、上記ホトレジスト層をエツチ
ングマスクとして上記下地層を選択エツチング
し、上記ホトレジスト層を除去した後にマスク蒸
着により上記半導体基板表面上に選択的に半田蒸
着膜を形成し、その後、上記半田蒸着膜を加熱溶
融することにより、上記下地層上に半田バンプを
形成する半導体装置の製造方法であつて、
上記選択エツチング時に、上記下地層を構成す
る多層の金属層のうちの最も下層の金属層を成す
第１金属層のエツチング速度と、この第１金属層
上の第２金属層のエツチング速度とを相違せしめ
ることによつて、上記第２金属層の周側面が上記
第１金属層の周側面よりも内側とされた状態の段
階状とすることを特徴とする。 A method for manufacturing a semiconductor device according to the present invention includes forming a metal wiring layer on a surface of a semiconductor substrate, forming an insulating layer on the semiconductor substrate including on the metal wiring layer,
A predetermined portion of the metal wiring layer is exposed by selectively etching the insulating layer, and then a base layer of a multilayer structure is formed by sequentially depositing different metals, and solder bump formation positions on the base layer are formed. A photoresist layer is formed, the base layer is selectively etched using the photoresist layer as an etching mask, and after the photoresist layer is removed, a solder vapor deposition film is selectively formed on the surface of the semiconductor substrate by mask vapor deposition. A method for manufacturing a semiconductor device in which solder bumps are formed on the base layer by heating and melting a solder vapor deposited film, the method comprising: forming solder bumps on the base layer by heating and melting the solder vapor deposited film; By making the etching rate of the first metal layer forming the metal layer different from the etching rate of the second metal layer on the first metal layer, the peripheral side of the second metal layer can be It is characterized by being in a step-like state inside the circumferential side of the.
以下、本発明を図示の実施例により説明する。 Hereinafter, the present invention will be explained with reference to illustrated embodiments.
第１図は本発明の一実施例である半導体装置の
製造方法によつて製造された半導体装置の要部、
特に半田バンプ部位を示しており、半導体基板１
の表面部に形成した図外の回路素子に接続される
配線用Al層２の一部を半田バンプ形成位置にま
で延設している。このAl層２はその上に形成し
た層間絶縁層３、例えば、高周波スパツタリング
法により被着した石英スパツタ膜で絶縁保護され
ているが前記バンプ形成位置ではこれをエツチン
グ除去してAl層２を露呈している。そして、露
呈されたAl層２乃至その周囲の絶縁層３上にわ
たつて下地層４を形成し、更に下地層４上に略半
球状の半田バンプ５を形成している。前記下地層
４は下からCr層６、Cu・Cr・混合層７、Cu層
８、Au層９を積層状態に形成しており、しかも
各層はその周側位置を相違させることにより下地
層４全体としてはその周側面を階段状に形成して
いるのである。 FIG. 1 shows the main parts of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to an embodiment of the present invention.
In particular, the solder bump area is shown, and the semiconductor substrate 1
A part of the wiring Al layer 2, which is connected to a circuit element (not shown) formed on the surface thereof, is extended to the solder bump formation position. This Al layer 2 is insulated and protected by an interlayer insulating layer 3 formed thereon, for example, a quartz sputtered film deposited by high frequency sputtering, but this is removed by etching at the bump formation position to expose the Al layer 2. are doing. Then, a base layer 4 is formed over the exposed Al layer 2 and the surrounding insulating layer 3, and a substantially hemispherical solder bump 5 is further formed on the base layer 4. The base layer 4 is formed of a Cr layer 6, a Cu/Cr/mixed layer 7, a Cu layer 8, and an Au layer 9 in a laminated state from the bottom, and each layer is arranged at a different position on the circumferential side to form the base layer 4. As a whole, the circumferential surface is formed into a step-like shape.
次に前記半田バンプの製造方法を説明する。 Next, a method for manufacturing the solder bump will be explained.
先ず第２図Ａのように半導体基板１の表面に配
線用Al層２と層間絶縁層３を形成しかつその一
部をエツチング除去して半田バンプ形成位置に前
記Al層２を露呈させる。次いで表面上に蒸着法
による下地層４を形成する。下地層４は、Cr蒸
着、Cu−Cr同時蒸着、Cu蒸着、Au蒸着を順次行
なつて下からCr層６、Cu−Cr・層７、Cu層８、
Au層９を積層状態に形成する。本例では、各層
の厚さは下から0.13、0.27、0.6、0.1μmに形成し
ている。 First, as shown in FIG. 2A, an Al layer 2 for wiring and an interlayer insulating layer 3 are formed on the surface of a semiconductor substrate 1, and a portion thereof is removed by etching to expose the Al layer 2 at the position where solder bumps are to be formed. Next, a base layer 4 is formed on the surface by a vapor deposition method. The base layer 4 is formed by sequentially performing Cr evaporation, Cu-Cr simultaneous evaporation, Cu evaporation, and Au evaporation to form a Cr layer 6, a Cu-Cr layer 7, a Cu layer 8,
The Au layer 9 is formed in a laminated state. In this example, the thickness of each layer is 0.13, 0.27, 0.6, and 0.1 μm from the bottom.
次に同図Ｂのようにホトレジスト層１０を形成
し、その上で公知の露光、現像処理を施して半田
バンプ形成位置にのみホトレジストを残存させ、
これをエツチングマスクとする。 Next, a photoresist layer 10 is formed as shown in FIG.
This will be used as an etching mask.
この状態でヨウ素ヨウ化アンモンの水溶液をエ
ツチング液としてエツチングを行なえば、下地層
４の中でもAu層９とCu層８がエツチングされ、
更にオーバエツチングによりCu−Cr層７のCu成
分がエツチングされる。この結果、AuとCuのエ
ツチング速度の相違により、同図ＣのようにAu
層９の周側がCu層８の周側よりも外方に張り出
した状態でエツチングされる。 If etching is performed in this state using an aqueous solution of iodine and ammonium iodide as an etching solution, the Au layer 9 and the Cu layer 8 in the base layer 4 will be etched.
Furthermore, the Cu component of the Cu-Cr layer 7 is etched by over-etching. As a result, due to the difference in etching speed between Au and Cu, the etching rate of Au
The circumferential side of the layer 9 is etched so as to protrude outward from the circumferential side of the Cu layer 8.
次に、今度はCF4と４％O2のガスを使用したプ
ラズマエツチングを行なえば、Cu−Cr層７のCr
成分とCr層６がエツチングされる。このとき、
エツチング速度の相違によりCu−Cr層７の周側
がCr層６の周側よりも小さくなる。そして、こ
のエツチング量を適宜コントロールすることによ
り、同図Ｄのように下地層の各層６，７，８，９
の周側を階段状に形成することができる。 Next, if plasma etching is performed using CF 4 and 4% O 2 gas, the Cr of the Cu-Cr layer 7 will be etched.
The components and the Cr layer 6 are etched. At this time,
Due to the difference in etching speed, the circumferential side of the Cu--Cr layer 7 becomes smaller than the circumferential side of the Cr layer 6. By appropriately controlling the amount of etching, each layer of the base layer 6, 7, 8, 9 is etched as shown in figure D.
The circumferential side of the can be formed into a stepped shape.
その後、ホトレジスト層１０を除去し、次に、
下地層４上に低温（50〜120℃）のメタルマスク
蒸着法により、選択的にPb−Snの半田蒸着膜を
形成し、N2雰囲気中の電気炉内で半田蒸着膜を
溶解する、このときAu層とCu層の１部分は半田
内に拡散され、その直後に冷却を行い、第１図の
半田バンプ５を固着形成させる、
以上の構成によれば、下地層４を構成する積層
された各層６，７，８，９の周側面を階段状に形
成しているので、半田バンプ５に剪断力が作用し
てもこの剪断力に基づく応力と、下地層の周辺に
集中する残留応力の和が最大値をとらないよう
に、下地各層の周辺位置を外側に階段状に移すこ
とにより、応力の集中が防止される。これによ
り、特に絶縁層３とCr層６との間に生じる集中
応力を低減して絶縁層３のクラツクを防止し、か
つ両者界面の密着力（接着力）を向上できる。因
みに本実施例では1.7Kg／mm2以上の密着力を得る
ことができた。 Thereafter, the photoresist layer 10 is removed, and then
A Pb-Sn solder evaporation film is selectively formed on the base layer 4 by a metal mask evaporation method at a low temperature (50 to 120°C), and the solder evaporation film is melted in an electric furnace in an N 2 atmosphere. At this time, parts of the Au layer and the Cu layer are diffused into the solder, and immediately thereafter cooled to firmly form the solder bumps 5 in FIG. Since the circumferential side of each layer 6, 7, 8, and 9 is formed in a step-like manner, even if shearing force is applied to the solder bump 5, stress based on this shearing force and residual stress concentrated around the base layer are reduced. Stress concentration is prevented by moving the peripheral position of each base layer outward in a stepwise manner so that the sum of the base layers does not reach its maximum value. As a result, it is possible to reduce the concentrated stress generated particularly between the insulating layer 3 and the Cr layer 6, prevent cracks in the insulating layer 3, and improve the adhesion (adhesive force) at the interface between the two. Incidentally, in this example, it was possible to obtain an adhesion force of 1.7 Kg/mm 2 or more.
一方、下地層４をホトレジストを利用してエツ
チング形成しているので、従来のようなマスク位
置ずれを防止でき、半田バンプの形成位置を高精
度に設定できる。因みに従来では33μm程度あつ
たずれ量を最大でも3.5μm程度に抑えることがで
きた。 On the other hand, since the base layer 4 is formed by etching using photoresist, it is possible to prevent the mask position from shifting as in the conventional case, and the formation position of the solder bump can be set with high precision. Incidentally, in the past, it was possible to suppress the amount of heat deviation by about 33 μm to about 3.5 μm at the maximum.
これらのことから、半田バンプの剪断破壊によ
る歩留りを従来の90％から99％に向上でき、また
位置ずれによる歩留りを従来の90％から99.9％に
向上することができる。 For these reasons, the yield due to shear failure of solder bumps can be improved from 90% to 99%, and the yield due to misalignment can be improved from 90% to 99.9%.
ここで、前記下地層４の積層構造は前例のもの
に限られるものではなく、例えばTi−Cu−Au
−、NiCr−Ni−Au、Cr−Ni−Auの積層構造で
あつてもよく、これ以外の構成でもよい。 Here, the laminated structure of the base layer 4 is not limited to the previous example, for example, Ti-Cu-Au
-, NiCr-Ni-Au, Cr-Ni-Au, or other configurations may be used.
また、下地層の各層周側面を階段状に形成する
他の方法として、第３図に要部を示すように、先
ずヨウ素系エツチング液にてAu層９、Cu層８、
Cu−Cr層７のCu成分を同図のａのようにエツチ
ングした後にHClをエツチング液としてCu−Cr
層７とCr層６を同図のｂのようにオーバエツチ
ングし、その後再び条件を相違させたヨウ素系エ
ツチング液にてAu層９、Cu層８を同図のｃのよ
うにエツチングして、下地層全体を前例と同様な
階段状に形成してもよい。 In addition, as another method for forming the circumferential side surface of each layer of the base layer in a step-like manner, first, as shown in FIG. 3, the Au layer 9, Cu layer 8,
After etching the Cu component of the Cu-Cr layer 7 as shown in a of the figure, the Cu-Cr layer 7 is etched using HCl as an etching solution.
The layer 7 and the Cr layer 6 are over-etched as shown in b of the same figure, and then the Au layer 9 and the Cu layer 8 are etched again as shown in c of the same figure using an iodine-based etching solution under different conditions. The entire base layer may be formed into a stepped shape similar to the previous example.
以上のように本発明の半導体装置によれば、半
田バンプの下地層を多層構造とした上で各層の周
側面位置を相違させて下地層全体としての周側面
を階段状に形成しているので、下地層に作用され
る剪断応力を厚さ方向に分散させることができ、
これにより半田バンプの強度を高めて信頼性の向
上を図ることができる。 As described above, according to the semiconductor device of the present invention, the base layer of the solder bump has a multilayer structure, and the position of the circumferential side of each layer is different, so that the circumferential side of the base layer as a whole is formed in a step-like manner. , the shear stress applied to the underlying layer can be dispersed in the thickness direction,
This makes it possible to increase the strength of the solder bump and improve reliability.
また、本発明方法によれば、多層に形成した下
地層の各層を順序的にエツチング処理して各層の
周側面位置を相違させ、これにより下地層の周側
面を階段状にして半田バンプを形成しているの
で、所謂ホトエツチング方法が採用可能であり、
半田バンプ位置を高精度に設定できる。これによ
り、前述した信頼性の向上と相俟つて歩留りの向
上を実限できる。 Further, according to the method of the present invention, each layer of the base layer formed in multiple layers is sequentially etched to vary the position of the circumferential side of each layer, thereby making the circumferential side of the base layer step-like and forming solder bumps. Therefore, the so-called photoetching method can be adopted.
Solder bump positions can be set with high precision. This makes it possible to improve yield in combination with the aforementioned improvement in reliability.
第１図は本発明の一実施例である半導体装置の
製造方法によつて製造された半導体装置の要部の
断面図、第２図Ａ〜Ｄは製造方法を説明するため
の工程断面図、第３図は他の方法を説明するため
の模式的な断面図である。
１…半導体基板、２…Al層、３…層間絶縁層、
４…下地層、５…半田バンプ、６…Cr層、７…
Cu−Cr層、８…Cu層、９…Au層、１０…ホトレ
ジスト層。
FIG. 1 is a cross-sectional view of a main part of a semiconductor device manufactured by a semiconductor device manufacturing method according to an embodiment of the present invention, and FIGS. 2A to 2D are process cross-sectional views for explaining the manufacturing method. FIG. 3 is a schematic cross-sectional view for explaining another method. 1... Semiconductor substrate, 2... Al layer, 3... Interlayer insulating layer,
4... Base layer, 5... Solder bump, 6... Cr layer, 7...
Cu-Cr layer, 8...Cu layer, 9...Au layer, 10...photoresist layer.
Claims (1)
記金属配線層上を含む上記半導体基板上に絶縁層
を形成し、上記絶縁層の選択エツチングにより上
記金属配線層の所定部分を露呈し、次に、互いに
異なる金属の順次の蒸着によつて多層構造の下地
層を形成し、上記下地層上の半田バンプ形成位置
にホトレジスト層を形成し、上記ホトレジスト層
をエツチングマスクとして上記下地層を選択エツ
チングし、上記ホトレジスト層を除去した後にマ
スク蒸着により上記半導体基板表面上に選択的に
半田蒸着膜を形成し、その後、上記半田蒸着膜を
加熱溶融することにより、上記下地層上に半田バ
ンプを形成する半導体装置の製造方法であつて、 上記選択エツチング時に、上記下地層を構成す
る多層の金属層のうちの最も下層の金属層を成す
第１金属層のエツチング速度と、この第１金属層
上の第２金属層のエツチング速度とを相違せしめ
ることによつて、上記第２金属層の周側面が上記
第１金属層の周側面よりも内側とされた状態の段
階状とすることを特徴とする半導体装置の製造方
法。 ２ 上記下地層は、Crから成る上記第１金属層
と、CrとCuの混合層から成る上記第２金属層と、
上記第２金属層上のCu層と、上記Cu層上のAu層
とから成ることを特徴とする特許請求の範囲第１
項記載の半導体装置の製造方法。 ３ 上記第２金属層と上記第１金属層とのエツチ
ングは、CF4とO2のガスを使用したプラズマエツ
チングであることを特徴とする特許請求の範囲第
２項記載の半導体装置の製造方法。 ４ 上記下地層は、Tiから成る上記第１金属層
と、Cuから成る上記第２金属層と、上記第２金
属層上のAu層とから成ることを特徴とする特許
請求の範囲第１項記載の半導体装置の製造方法。 ５ 上記下地層は、NiCrから成る上記第１金属
層と、Niから成る上記第２金属層と、上記第２
金属層上のAu層とから成ることを特徴とする特
許請求の範囲第１項記載の半導体装置の製造方
法。 ６ 上記下地層は、Crから成る上記第１金属層
と、Niから成る上記第２金属層と、上記第２金
属層上のAu層とから成ることを特徴とする特許
請求の範囲第１項記載の半導体装置の製造方法。 ７ 上記金属配線層は、Al層から成り、上記絶
縁層は石英スパツタ膜から成ることを特徴とする
特許請求の範囲第１項ないし第５項のうちの１に
記載の半導体装置の製造方法。[Scope of Claims] 1. A metal wiring layer is formed on a surface of a semiconductor substrate, an insulating layer is formed on the semiconductor substrate including on the metal wiring layer, and a predetermined portion of the metal wiring layer is formed by selectively etching the insulating layer. Then, a base layer of a multilayer structure is formed by sequentially depositing different metals, a photoresist layer is formed on the base layer at the position where the solder bumps are to be formed, and the photoresist layer is used as an etching mask. After selectively etching the base layer and removing the photoresist layer, a solder deposited film is selectively formed on the surface of the semiconductor substrate by mask evaporation, and then the solder deposited film is heated and melted to form the base layer. A method of manufacturing a semiconductor device on which solder bumps are formed, the method comprising: during the selective etching, the etching rate of a first metal layer forming the lowest metal layer of the multilayer metal layers forming the base layer; By making the etching rate of the second metal layer on the first metal layer different, a stepwise state is formed in which the circumferential side of the second metal layer is inside the circumferential side of the first metal layer. A method for manufacturing a semiconductor device, characterized in that: 2 The base layer includes the first metal layer made of Cr and the second metal layer made of a mixed layer of Cr and Cu,
Claim 1 comprising a Cu layer on the second metal layer and an Au layer on the Cu layer.
A method for manufacturing a semiconductor device according to section 1. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the etching of the second metal layer and the first metal layer is plasma etching using CF 4 and O 2 gases. . 4. Claim 1, wherein the base layer is comprised of the first metal layer made of Ti, the second metal layer made of Cu, and an Au layer on the second metal layer. A method of manufacturing the semiconductor device described above. 5 The base layer includes the first metal layer made of NiCr, the second metal layer made of Ni, and the second metal layer made of NiCr.
2. The method of manufacturing a semiconductor device according to claim 1, further comprising an Au layer on a metal layer. 6. Claim 1, wherein the base layer is comprised of the first metal layer made of Cr, the second metal layer made of Ni, and an Au layer on the second metal layer. A method of manufacturing the semiconductor device described above. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the metal wiring layer is made of an Al layer, and the insulating layer is made of a quartz sputtered film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57226135A JPS59117135A (en) | 1982-12-24 | 1982-12-24 | Semiconductor device and manufacture of the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57226135A JPS59117135A (en) | 1982-12-24 | 1982-12-24 | Semiconductor device and manufacture of the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59117135A JPS59117135A (en) | 1984-07-06 |
| JPH058570B2 true JPH058570B2 (en) | 1993-02-02 |
Family
ID=16840393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57226135A Granted JPS59117135A (en) | 1982-12-24 | 1982-12-24 | Semiconductor device and manufacture of the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59117135A (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61141155A (en) * | 1984-12-14 | 1986-06-28 | Hitachi Ltd | Solder-base electrode |
| US4950623A (en) * | 1988-08-02 | 1990-08-21 | Microelectronics Center Of North Carolina | Method of building solder bumps |
| JP2533634B2 (en) * | 1989-01-31 | 1996-09-11 | 松下電器産業株式会社 | Method of manufacturing semiconductor device having bump electrodes |
| US5289631A (en) * | 1992-03-04 | 1994-03-01 | Mcnc | Method for testing, burn-in, and/or programming of integrated circuit chips |
| US5268072A (en) * | 1992-08-31 | 1993-12-07 | International Business Machines Corporation | Etching processes for avoiding edge stress in semiconductor chip solder bumps |
| JPH07105586B2 (en) * | 1992-09-15 | 1995-11-13 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Semiconductor chip connection structure |
| US5376584A (en) * | 1992-12-31 | 1994-12-27 | International Business Machines Corporation | Process of making pad structure for solder ball limiting metallurgy having reduced edge stress |
| US5384283A (en) * | 1993-12-10 | 1995-01-24 | International Business Machines Corporation | Resist protection of ball limiting metal during etch process |
| JP2664878B2 (en) * | 1994-01-31 | 1997-10-22 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Semiconductor chip package and method of manufacturing the same |
| US5503286A (en) * | 1994-06-28 | 1996-04-02 | International Business Machines Corporation | Electroplated solder terminal |
| EP0815593B1 (en) | 1995-03-20 | 2001-12-12 | Unitive International Limited | Solder bump fabrication methods and structure including a titanium barrier layer |
| JP2011249564A (en) * | 2010-05-27 | 2011-12-08 | Renesas Electronics Corp | Semiconductor device manufacturing method and mounting structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS572548A (en) * | 1980-06-06 | 1982-01-07 | Citizen Watch Co Ltd | Ic electrode structure |
| JPS57198647A (en) * | 1981-06-01 | 1982-12-06 | Nec Corp | Semiconductor device and manufacture therefor |
-
1982
- 1982-12-24 JP JP57226135A patent/JPS59117135A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS572548A (en) * | 1980-06-06 | 1982-01-07 | Citizen Watch Co Ltd | Ic electrode structure |
| JPS57198647A (en) * | 1981-06-01 | 1982-12-06 | Nec Corp | Semiconductor device and manufacture therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59117135A (en) | 1984-07-06 |
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