JPH03262137A - Manufacture of semiconductor integrated circuit device - Google Patents
Manufacture of semiconductor integrated circuit deviceInfo
- Publication number
- JPH03262137A JPH03262137A JP2061398A JP6139890A JPH03262137A JP H03262137 A JPH03262137 A JP H03262137A JP 2061398 A JP2061398 A JP 2061398A JP 6139890 A JP6139890 A JP 6139890A JP H03262137 A JPH03262137 A JP H03262137A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor chip
- integrated circuit
- circuit device
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000463 material Substances 0.000 claims abstract description 23
- 238000005219 brazing Methods 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 3
- 238000001465 metallisation Methods 0.000 claims description 8
- 230000005496 eutectics Effects 0.000 abstract description 7
- 229910052737 gold Inorganic materials 0.000 abstract description 5
- 230000004888 barrier function Effects 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 3
- 239000010936 titanium Substances 0.000 abstract description 3
- 229910052719 titanium Inorganic materials 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 239000010931 gold Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000000956 alloy Substances 0.000 description 2
- 238000005275 alloying Methods 0.000 description 2
- 229910017401 Au—Ge Inorganic materials 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野１
本発明は半導体集積回路装置の製造方法に関し、特に半
導体チップのパッケージへのマウント方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application 1] The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a method for mounting a semiconductor chip onto a package.
［従来の技術］
従来、半導体チップをパッケージ上にマウントするには
、第２図（ａ）、（ｂ）の状態図、Ｂ部拡大図が示すよ
うに、マウントに先立ち、半導体チップ２の裏面には拡
散バリア・メタル［例えば、チタン（Ｔｉｅ］ ３を介
して金（Ａｕｌをスパッタしたバック・メタライズ層６
が予め設けられ、ロー材ｌＡｕ−５ｉ） ５を用いてパ
ッケージ下部部材１上にグイ・ボンディングされる。[Prior Art] Conventionally, in order to mount a semiconductor chip on a package, as shown in the state diagrams and the enlarged view of part B in FIGS. A back metallization layer 6 is formed by sputtering gold (Au1) through a diffusion barrier metal [e.g. titanium (Tie) 3].
is provided in advance and is firmly bonded onto the package lower member 1 using a brazing material lAu-5i) 5.
［発明が解決しようとする課題１
しかしながら、内蔵する回路数が増加するにつれて、半
導体チップ２のサイズが大きくなり、また、パッケージ
も大型化する傾向にある今日では、チップ裏面の金（Ａ
ｕ）層６とロー材（Ａｕ−３ｉ） ５とが充分に共晶化
しない場合が起こる。すなわち、共晶温度に対する温度
不均一または共晶化するための時間不足などが原因して
、第３図（ａ）、（ｂ）および（Ｃ）に示すように、半
導体チップ２の裏面とロー材５との境界には非共晶の領
域Ａ。或いはロー材５の非溶解領域Ｂ。が生じる場合が
起こる。従って、これによる接着不良の発生が半導体チ
ップのｔす離頻度を高めるという不具合を起こしている
。[Problem to be Solved by the Invention 1] However, as the number of built-in circuits increases, the size of the semiconductor chip 2 increases, and the size of the package also tends to increase.
u) There are cases where the layer 6 and the brazing material (Au-3i) 5 are not sufficiently eutecticized. In other words, due to temperature non-uniformity with respect to the eutectic temperature or lack of time for eutectic formation, the back surface of the semiconductor chip 2 and the lower surface may become loose as shown in FIGS. 3(a), (b), and (C). There is a non-eutectic region A at the boundary with material 5. Or the non-dissolved area B of the brazing material 5. Occasionally, this may occur. Therefore, the occurrence of adhesion failure due to this causes a problem of increasing the frequency of separation of semiconductor chips.
本発明の目的は、上記の情況に鑑み、半導体チップの大
型化に伴うグイ・ボンディング不良の発生問題を解決し
た半導体集積回路装置の製造方法を提供することである
。SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device that solves the problem of occurrence of defective bonding due to the increase in the size of semiconductor chips.
［課題を解決するだめの手段〕
本発明によれば、半導体集積回路装置の製造方法は、半
導体チップをリード・フレームのアイランド上に載置し
、ワイヤーボンディングする半導体集積回路装置の製造
方法において、前記チップの基板裏面にあらかじめ形成
するバック・メタライズ層の金属膜材を該半導体チップ
を前記アイランド上に載置する際使用するロー材と同一
材料に設定することを含んで構成される。[Means for Solving the Problem] According to the present invention, a method for manufacturing a semiconductor integrated circuit device includes placing a semiconductor chip on an island of a lead frame and wire bonding the semiconductor chip. The method includes setting the metal film material of the back metallization layer previously formed on the back surface of the substrate of the chip to be the same material as the brazing material used when mounting the semiconductor chip on the island.
［作 用 ］
本発明によれば、半導体チップのバック・メタライズ層
には、使われるロー材と同質の金ｆＡｕ）を含む合金材
が用いられるので、共晶合金化速度を高めることができ
る。従って、短時間の作業で両者の境界面に金（Ａｕｌ
共品共合化合金成することができるので、大型チップの
グイ・ボンディング効率が著しく向上する。[Function] According to the present invention, the back metallization layer of the semiconductor chip uses an alloy material containing gold (fAu), which is the same as the brazing material used, so that the rate of eutectic alloying can be increased. Therefore, in a short time, the interface between the two can be coated with gold (Au).
Since the same conjugate alloy can be formed, the bonding efficiency of large chips is significantly improved.
［実施例１ 次に本発明について図面を参照して詳細に説明する。[Example 1 Next, the present invention will be explained in detail with reference to the drawings.
第１図（ａ）および（ｂ）はそれぞれ本発明の一実施例
を示すグイ・ボンディング工程の最終状態図およびその
Ａ部拡大図である。本実施例によれば、半導体チップ２
の裏面には拡散バリア・メタル３としてチタン（Ｔ旬が
まずスパッタされ、ついでパッケージ下部部材１上の口
材５と同質の（Ａｕ−３ｉｌバツク・メタライズ層４が
スパッタ形成される。マウントに際しては、（Ａｕ−３
ｉ）バック・メタライズ層４と同一材料の（Ａｕ−３ｉ
ｌ ロー材５が使われてパッケージ下部部材１上に接着
される。このように、バック・メタライズ層４とロー材
５とが同一材料である場合、半導体チップ２の裏面とパ
ッケージ下部部材１との境界には均一なＡｕ−３ｉの共
晶状態が作られるので、両者は強固に接着されることに
なる。以上は（Ａｕ−３ｉ）金属の場合を説明したが、
この伯にも（Ａｕ−３ｎｌ或いは（Ａｕ−Ｇｅ）等を使
用することができる。FIGS. 1(a) and 1(b) are a final state diagram and an enlarged view of part A of the Gui bonding process, respectively, showing one embodiment of the present invention. According to this embodiment, the semiconductor chip 2
On the back side of the package, titanium (T) is first sputtered as a diffusion barrier metal 3, and then an Au-3il back metallization layer 4 of the same quality as the opening material 5 on the package lower member 1 is sputtered. , (Au-3
i) (Au-3i) of the same material as the back metallization layer 4
l A brazing material 5 is used to bond onto the package lower part 1. In this way, when the back metallized layer 4 and the brazing material 5 are made of the same material, a uniform Au-3i eutectic state is created at the boundary between the back surface of the semiconductor chip 2 and the lower package member 1. Both will be firmly adhered. The above explained the case of (Au-3i) metal, but
(Au-3nl, (Au-Ge), etc.) can also be used for this material.
［発明の効果］
以上説明したように、本発明によれば、半導体チップの
バック・メタライズ層にパッケージ下部部材上のロー材
と同一の材料が選択され、共晶合金化のための反応スピ
ードが短縮されるので、マウント時間を短縮することが
できる他、従来発生していたグイ・ボンディングの接着
不良を解決することができる。[Effects of the Invention] As explained above, according to the present invention, the same material as the brazing material on the lower package member is selected for the back metallization layer of the semiconductor chip, and the reaction speed for eutectic alloying is increased. Since the mounting time is shortened, it is possible to shorten the mounting time, and also to solve the problem of adhesive bonding that conventionally occurred.
第１図（ａ）および（ｂ）は本発明の一実施例を示すグ
イ・ボンディング工程の最終状態図およびそのＡ部拡大
図、第２図（ａ）および（ｂ）はそれぞれ従来のグイ・
ボンディング工程の最終状態図およびそのＢ部拡大図、
第３図（ａ）、（ｂ）および（ｃ）は従来のグイ・ボン
ディング技術による半導体チップの接着不良要因を示す
図である。
ｌ・・・パッケージ下部部材、
２・・・半導体チップ、
３・・・拡散バリア・メタル（Ｔｉｌ、４・・−（Ａｕ
−３ｉ）バック・メタライズ層、５−・・ロー材（Ａｕ
−３ｉ１
６・・−金（Ａｕｌバック・メタライズ層。FIGS. 1(a) and (b) are a final state diagram and an enlarged view of part A of the Gui bonding process showing one embodiment of the present invention, and FIGS. 2(a) and (b) are respectively the conventional Gui bonding process.
A final state diagram of the bonding process and an enlarged view of part B thereof,
FIGS. 3(a), 3(b), and 3(c) are diagrams showing causes of failure in adhesion of semiconductor chips by conventional Gui bonding technology. l...Package lower member, 2...Semiconductor chip, 3...Diffusion barrier metal (Til, 4...-(Au)
-3i) Back metallized layer, 5-... Raw material (Au
-3i1 6...-Gold (Aul back metallization layer).
Claims (1)
置し、ワイヤーボンディングする半導体集積回路装置の
製造方法において、前記半導体チップの基板裏面にあら
かじめ形成するバック・メタライズ層の金属膜材を該半
導体チップを前記アイランド上に載置する際使用するロ
ー材と同一材料に設定することを特徴とする半導体集積
回路装置の製造方法。In a method of manufacturing a semiconductor integrated circuit device in which a semiconductor chip is mounted on an island of a lead frame and wire bonded, a metal film material of a back metallization layer formed in advance on the back surface of a substrate of the semiconductor chip is attached to the semiconductor chip. A method for manufacturing a semiconductor integrated circuit device, characterized in that the brazing material is the same as the brazing material used when placing the device on the island.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2061398A JPH03262137A (en) | 1990-03-12 | 1990-03-12 | Manufacture of semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2061398A JPH03262137A (en) | 1990-03-12 | 1990-03-12 | Manufacture of semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03262137A true JPH03262137A (en) | 1991-11-21 |
Family
ID=13170008
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2061398A Pending JPH03262137A (en) | 1990-03-12 | 1990-03-12 | Manufacture of semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03262137A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103646882A (en) * | 2013-11-27 | 2014-03-19 | 江苏艾特曼电子科技有限公司 | Eutectic bonding material-series structure used for wafer-level encapsulation |
| CN113327862A (en) * | 2021-02-07 | 2021-08-31 | 上海先进半导体制造有限公司 | Eutectic welding method without welding flux and electronic product |
-
1990
- 1990-03-12 JP JP2061398A patent/JPH03262137A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103646882A (en) * | 2013-11-27 | 2014-03-19 | 江苏艾特曼电子科技有限公司 | Eutectic bonding material-series structure used for wafer-level encapsulation |
| CN113327862A (en) * | 2021-02-07 | 2021-08-31 | 上海先进半导体制造有限公司 | Eutectic welding method without welding flux and electronic product |
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