JPS6079732A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6079732A
JPS6079732A JP58186714A JP18671483A JPS6079732A JP S6079732 A JPS6079732 A JP S6079732A JP 58186714 A JP58186714 A JP 58186714A JP 18671483 A JP18671483 A JP 18671483A JP S6079732 A JPS6079732 A JP S6079732A
Authority
JP
Japan
Prior art keywords
pellet
layer
tin
aluminum
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58186714A
Other languages
Japanese (ja)
Inventor
Keiji Miyamoto
宮本　圭二
Toru Kawanobe
川野辺　徹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58186714A priority Critical patent/JPS6079732A/en
Publication of JPS6079732A publication Critical patent/JPS6079732A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To diebond a pellet firmly by means of fixing the pellet through the intermediary of a metal layer comprising two layers i.e. an aluminum layer and a tin layer. CONSTITUTION:A silicon-made pellet 3 is diebonded on a tub 2 coated with a metal layer 9 with its surface excellently adhesive to tin through the intermediary of an aluminum layer 7 coatingly formed on the backside of the pellet 3 and a tin layer 8 further coatingly formed on the backside of the aluminum layer 7. The pellet 3 may be firmly diebonded on the tub 2 since aluminum is excellently adhesive to silicon as the pellet material which is also excellently adhesive to the material metal of pellet fixing surface.

Description

【発明の詳細な説明】 ［技術分野］ 本発明は、信頼性の高い半導体装置を低コストで提供す
る技術、特に樹脂封止型半導体装置に通用して有効な技
術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique for providing a highly reliable semiconductor device at low cost, and particularly to a technique that is applicable and effective for resin-sealed semiconductor devices.

［背景技術］ 材質がコバールまたは４２−アロイ等であるリードフレ
ームのタブ上にペレットをグイボンディングする方法と
しては、予め部分めっき法等で金（Ａｕ）を被着したタ
ブの上面に金（Ａｕ）とシリコン（Ｓｔ）との共晶合金
（以下、Ａｕ−３ｔ共晶という。）でペレ・７トを接着
する方法、予め部分めっき法等で銀（Ａｇ）を被着した
タブの上面にいわゆる銀ペーストでペレットを接着する
方法、または半田で取り付ける方法等が考えられる。[Background Art] A method for bonding pellets onto the tab of a lead frame made of Kovar or 42-alloy is to bond gold (Au) onto the top surface of the tab, which has been previously coated with gold (Au) using a selective plating method or the like. ) and silicon (St) (hereinafter referred to as Au-3T eutectic). Possible methods include bonding the pellets with so-called silver paste or attaching them with solder.

ところが、八ｕ−３Ｌ共晶でダイボンディングする場合
は、多量の金を使用しなければならないため、卵重にコ
ストが高いものとなる。一方、銀ペーストによる場合は
、コストが高いことに加えて、銀のマイグレーションに
よる電気的不良の問題があることが本発明者によって明
らかにされた。However, when die bonding is performed using the 8U-3L eutectic, a large amount of gold must be used, resulting in a high egg weight and cost. On the other hand, the inventors have revealed that when using silver paste, in addition to high cost, there is a problem of electrical failure due to silver migration.

また、半田で取り付ける場合には、半田付は性を付与す
るために、予めペレット裏面に例えばヂタン（Ｔｉ）−
ニッケル（Ｎｉ）−銀または金の３層からなる金属層を
設けておくことが考えられるが、チタンおよびニッケル
は融点が高いため蒸着しにくく、その上、内部応力が大
きいという問題があり、さらにニッケル表面の酸化防止
のための保護層を銀または金で形成することはコストが
高くなるという問題にもなる。In addition, when attaching by soldering, in order to impart properties to the soldering process, for example, Ti--
It is conceivable to provide a metal layer consisting of three layers of nickel (Ni) - silver or gold, but titanium and nickel have a high melting point and are therefore difficult to evaporate, and also have the problem of high internal stress. Forming a protective layer of silver or gold to prevent oxidation on the nickel surface also poses the problem of increased costs.

［発明の目的］ 本発明の目的は、信頼性が高い半導体装置を低コストで
製造する技術を提供することにある。[Object of the Invention] An object of the present invention is to provide a technique for manufacturing a highly reliable semiconductor device at low cost.

本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

［発明の概要］ 本願において開示される発明のうち代表的なものの概要
を簡単にｉ−明すれば、次の通りである。[Summary of the Invention] A brief outline of typical inventions disclosed in this application is as follows.

すなわち、ペレットと付着性が良い金属であるアルミニ
ウムを該ペレット裏面に被着し、該アルミニウム層の表
面にアルミニウムおよびペレット取り付は部の金属の両
者と付着性が良い金属である錫を被着して形成したアル
ミニウムおよび錫の２層からなる金属を介してグイボン
ディングすることにより、半導体装置の信頼性向上とコ
スト低減を達成するものである。That is, aluminum, which is a metal that has good adhesion to pellets, is applied to the back side of the pellet, and tin, which is a metal that has good adhesion to both aluminum and the metal on which the pellet is attached, is applied to the surface of the aluminum layer. By performing bonding through the two-layered metal layer of aluminum and tin, the reliability of the semiconductor device can be improved and the cost can be reduced.

［実施例］ 図は、本発明の一実施例である半導体装置をその断面図
で示したものである。[Example] The figure shows a cross-sectional view of a semiconductor device that is an example of the present invention.

本実施例の半導体装置は、コバールまたは４２−アロイ
等の材料からなるリードフレーム１のペレット取り付は
部であるタブ２にグイボンディングされたペレット３、
該ペレットのポンディングパッド４とリードのボンディ
ング部とを電気的に接続しているワイヤ５等を樹脂６で
モールドして封止したものである。The semiconductor device of this embodiment includes a pellet 3, which is firmly bonded to a tab 2, which is a pellet attachment part of a lead frame 1 made of a material such as Kovar or 42-alloy.
The wire 5 and the like electrically connecting the bonding pad 4 of the pellet and the bonding part of the lead are molded and sealed with resin 6.

本実施例においては、シリコン（Ｓｉ）よりなるペレッ
ト３は、該ペレット３の裏面に被着形成されたアルミニ
ウム層７および該アルミニウム層７の下面に被着形成さ
れた錫層８の２層からなる金属層を介して、上面が錫と
付着性の良い金属層９で被着されたタブ２にグイボンデ
ィングされている。In this embodiment, the pellet 3 made of silicon (Si) is made of two layers: an aluminum layer 7 deposited on the back surface of the pellet 3 and a tin layer 8 deposited on the bottom surface of the aluminum layer 7. The upper surface of the tab 2 is bonded to the tab 2, which is coated with a metal layer 9 that has good adhesion to tin, through a metal layer.

ここで、アルミニウムはペレソ１−３の材料であるシリ
コン（ＳＬ）および錫と付着性が良いので、前記２１Ｗ
の金属層を介してグイボンディングすることにより、ペ
レット３をペレット取り付は面上に強固に取り付けるこ
とができるものである。また、前記のグイボンディング
に使用する金属がともに廉価なので、本実施例の半導体
装置を低価格で提供できる。Here, since aluminum has good adhesion to silicon (SL) and tin, which are the materials of Pereso 1-3,
By bonding through the metal layer, the pellet 3 can be firmly attached to the surface. Furthermore, since the metals used for the above-mentioned bonding are both inexpensive, the semiconductor device of this embodiment can be provided at a low price.

本実施例の半導体装置の製造方法について、その−例を
次に示す。まず、ペレット３の表面にアルミニウムを蒸
着し、アルミニウム層７を形成し、次いで同じく蒸着法
にてアルミニウム層７に重ねて錫層８を形成する。なお
、この金属層を形成する方法としては、アルミニウムと
錫の合金を原料として１工程で行うこともできる。すな
わち、たとえば１０　’　Ｔｏｒｒで蒸着する場合であ
っても、前記合金を加熱昇温しでゆくと、蒸発（沸騰）
温度が低いアルミニウムの方が優先的に蒸発付着し、ア
ルミニウムの蒸発が終わった後、さらに昇温しでやるこ
とにより既に蒸着しているアルミニウム層７に錫を重ね
て蒸発付着させることができ、結果として一定減圧条件
下で合金を昇温するという１工程でアルミニウムおよび
錫の２ｍからなる金属層を形成することができる。An example of the method for manufacturing the semiconductor device of this embodiment will be shown below. First, aluminum is vapor-deposited on the surface of the pellet 3 to form an aluminum layer 7, and then a tin layer 8 is formed over the aluminum layer 7 by the same vapor deposition method. Note that this metal layer can also be formed in one step using an alloy of aluminum and tin as a raw material. That is, even when depositing at 10' Torr, for example, if the alloy is heated to a high temperature, it will evaporate (boil).
Aluminum at a lower temperature is preferentially evaporated and deposited, and by further raising the temperature after the aluminum has finished evaporating, tin can be superimposed on the already deposited aluminum layer 7 and evaporated and deposited. As a result, a 2 m thick metal layer of aluminum and tin can be formed in one step of heating the alloy under constant reduced pressure conditions.

次に、前記のいずれかの方法で調整したペレット３を、
予め銀と付着性の良い金属、たとえば錫、金または銀等
で上面が被着されたタブ２に熱融着にてグイボンディン
グする。Next, the pellets 3 prepared by any of the above methods are
The tab 2 is bonded by thermal fusion to the tab 2 whose upper surface has been previously coated with a metal that has good adhesion to silver, such as tin, gold, or silver.

その後のワイヤボンディング、樹脂モールド等の工程は
通常の方法を適用することにより、本実施例の半導体装
置を得ることができる。The semiconductor device of this example can be obtained by applying conventional methods to subsequent steps such as wire bonding and resin molding.

［効果］ （１）、半導体装置におけるペレットを該ペレソＩ・の
裏面に形成したアルミニウム層および該アルミニウム層
に重ねて形成したｇＪ層の２Ｎからなる金属層を介し、
てペレット取り付は面にグイボンディングすることによ
り、アルミニウムがペレソｌ−４４料であるシリコンお
よび錫と付着性が良く、該錫がペレット取り（【１り面
の材料金属と何着性が良いため、ペレットを強固にグイ
ボンディングすることができるので、半導体装置の信頼
性を向上することができる。[Effects] (1) A pellet in a semiconductor device is passed through a metal layer made of 2N of an aluminum layer formed on the back surface of the Pelleso I and a gJ layer formed over the aluminum layer,
By bonding the pellets to the surface, the aluminum has good adhesion to silicon and tin, which are Pellesol I-44 materials, and the tin has good adhesion to the material metal on the surface. Therefore, the pellets can be strongly bonded, and the reliability of the semiconductor device can be improved.

（２）、前記ｉｌ＋に示す金属層が、アルミニウムおよ
び錫の廉価な金属で形成されるので、低コストの半導体
装置を得ることができる。(2) Since the metal layer shown in il+ is formed of inexpensive metals such as aluminum and tin, a low-cost semiconductor device can be obtained.

（３）、前記（１１に示す金属層の被着法として蒸着法
を採用することにより、容易に被着形成することができ
る。(3) By employing the vapor deposition method as the method for depositing the metal layer shown in (11) above, the metal layer can be easily deposited.

（４）、前記（１１の金属層は、アルミニウムおよび錫
の合金を原料に用いることにより、蒸着条件下における
両金属の蒸気圧の差を利用して、■工程で形成すること
ができる。(4) The metal layer in (11) above can be formed in step (1) by using an alloy of aluminum and tin as raw materials and utilizing the difference in vapor pressure between the two metals under vapor deposition conditions.

（５）、錫と付着し易い金属を予め被着したベレット取
り付は面に、前記（１１に示すペレットをボンディング
することにより、ペレットの取り付は強度を増すことが
できるので、一段と信頼性を向上させることができる。(5) By bonding the pellet shown in (11) above to the surface of the pellet, which is pre-coated with a metal that easily adheres to tin, the strength of the pellet attachment can be increased, making it even more reliable. can be improved.

以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor.

たとえば、ペレット裏面の金属層は蒸着法で形成する場
合に限るものでなく、めっき等の他の方法によって形成
してもよいことはいうまでもない。For example, the metal layer on the back surface of the pellet is not limited to the case where it is formed by a vapor deposition method, and it goes without saying that it may be formed by other methods such as plating.

また、実施例では、錫と付着性の良い金属を被着したタ
ブを使用した場合について説明したが、裏面にアルミニ
ウムと錫の２層の金属を形成したペレットを、その金属
層を介してタブに直接ボンディングすることもできる。In addition, in the example, a case was explained in which a tab coated with a metal that has good adhesion to tin was used, but a pellet with two metal layers of aluminum and tin formed on the back side was attached to the tab through the metal layer. It is also possible to bond directly to.

さらに、錫と付着し易い金属として錫、金および銀につ
いて説明したが、これらに限定するものでないことはい
うまでもない。Furthermore, although tin, gold, and silver have been described as metals that easily adhere to tin, it goes without saying that the present invention is not limited to these.

［利用分野］ 以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である樹脂封止型半導体装
置に適用した場合について説明したが、それに限定され
るものではなく、たとえば、金−シリコン共晶または銀
ペースト等でグイボンディングを行っている高価な半導
体装置に代わる低コストの半導体装置として、セラミソ
クバ、ケージ型半導体装置等、あらゆるものに適用して
有効である。[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to a resin-sealed semiconductor device, which is the field of application that formed the background of the invention, but the invention is not limited to this, and for example, It is effective when applied to all kinds of semiconductor devices, such as ceramic plates and cage-type semiconductor devices, as a low-cost semiconductor device that can replace expensive semiconductor devices in which bonding is performed using gold-silicon eutectic or silver paste.

【図面の簡単な説明】[Brief explanation of drawings]

図は、本発明の一実施例である樹脂封止型半導体装置の
断面図である。 ■・・・リードフレーム、２・・・タブ、３・・・ペレ
ット、４・・・ポンディングパッド、５・・・ワイヤ、
６・・・樹脂、７・・・アルミニウム層、８・・・錫層
、９・・・金属層。The figure is a sectional view of a resin-sealed semiconductor device that is an embodiment of the present invention. ■...Lead frame, 2...Tab, 3...Pellet, 4...Ponding pad, 5...Wire,
6...Resin, 7...Aluminum layer, 8...Tin layer, 9...Metal layer.

Claims (1)

【特許請求の範囲】 １、ペレット取り付は面上に、金属層を介してペレット
をボンディングしてなる半導体装置において、金属層が
、ペレット裏面に被着されたアルミニウム層および該ア
ルミニウム層の下面に被着された錫層の２層からなるこ
とを特徴とする半導体装置。 ２、アルミニウム層および錫層が蒸着法で被着されてな
ることを特徴とする特許請求の範囲第１項記載の半導体
装置。 ３、ペレット取り付は面が錫との付着性の良い金属で被
着されていることを特徴とする特許請求の範囲第１項ま
たは第２項記載の半導体装置。[Claims] 1. In a semiconductor device in which a pellet is bonded onto a surface via a metal layer, the metal layer is attached to an aluminum layer adhered to the back surface of the pellet and the lower surface of the aluminum layer. A semiconductor device characterized in that it consists of two layers: a tin layer deposited on a tin layer. 2. The semiconductor device according to claim 1, wherein the aluminum layer and the tin layer are deposited by a vapor deposition method. 3. The semiconductor device according to claim 1 or 2, wherein the pellet mounting surface is coated with a metal that has good adhesion to tin.
JP58186714A 1983-10-07 1983-10-07 Semiconductor device Pending JPS6079732A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58186714A JPS6079732A (en) 1983-10-07 1983-10-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58186714A JPS6079732A (en) 1983-10-07 1983-10-07 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6079732A true JPS6079732A (en) 1985-05-07

Family

ID=16193351

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58186714A Pending JPS6079732A (en) 1983-10-07 1983-10-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6079732A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01152633A (en) * 1987-12-09 1989-06-15 Nec Kagoshima Ltd Manufacture of semiconductor device
WO2002027789A1 (en) * 2000-09-29 2002-04-04 Infineon Technologies Ag Connecting device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01152633A (en) * 1987-12-09 1989-06-15 Nec Kagoshima Ltd Manufacture of semiconductor device
WO2002027789A1 (en) * 2000-09-29 2002-04-04 Infineon Technologies Ag Connecting device

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