JPS63142640A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enhance the bonding strength by a method wherein, during a grinding process, the rear of a semiconductor chip is finished in such a way that the surface roughness RMAX is a prescribed value. CONSTITUTION:The rear of a GaAs layer situated under a chip 3 is shaped to be rough, and a metallized layer 5 is formed on this rear by evaporation of Ti. In addition, an Au layer 6 is formed on the surface of this Ti layer 5 so that the layer becomes adaptable to an adhesive agent, and is glued to a substrate 1 through an adhesive-agent layer 7 of AuSn. The rear of the semiconductor chip 3 is shaped to be rough by a grinding process at the stage of a wafer. If the 'roughness' is expressed by the difference RMAX between the highest and the deepest parts on the rear of the semiconductor chip 3, the RMAX is to range from 0.2 to 0.5 (mum). This value is an especially effective value when a soldering process is applied to the GaAs chip and a metallizing process is executed by evaporation of the Ti film.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a method for manufacturing a semiconductor chip.

More specifically, the present invention relates to a novel method for processing the bonding surface of a semiconductor chip in a so-called die bonding process in which the chip is fixed on a lead frame or pancage prior to the wire bonding process of the semiconductor chip.

BACKGROUND ART Die bonding is a technique for fixing semiconductor chips, which are manufactured by dividing a semiconductor wafer mounted with a circuit, to a predetermined position on a support pad such as a ceramic package or a lead frame. This mechanically and electrically connects the semiconductor chip to the package.

Die bonding methods can be broadly classified into Au-3i eutectic alloy method, solder bonding method, and resin bonding method.

The Au-3i eutectic alloy method takes advantage of the fact that the melting point of the Au-3i eutectic alloy is relatively low at 370°C. This is a method of bonding the two by heating to around ℃. This method is currently the most widely used method because it provides a good adhesion state both mechanically and electrically.

On the other hand, the solder bonding method uses PB-3 as the adhesive.
This is a method using a brazing material such as nSAu-Ge, Au-3i, and Heu-3n. In this case, the working temperature is in the range 200-400°C. This method requires an additional operation in which the back surface of the semiconductor chip is previously metallized with Ni-Au5Ti-Ni-Au or the like to improve compatibility with the brazing material. However, the advantage of this method is that the thermal strain caused by the difference in thermal expansion coefficient between the substrate and the semiconductor chip is absorbed by the solder layer, so chip damage is less likely to occur even if the area of the semiconductor chip increases. . Therefore, with the recent increase in the scale of integrated circuits and the rise in the price of Au, its practical application is attracting attention.

The resin bonding method is a method of fixing a semiconductor chip using a resin containing metal powder such as Ag as an adhesive.
Although this method is more novel than the previous method, it has problems such as the time it takes for the adhesive to harden, so future research is awaited.

The challenges in these die bonding techniques are to obtain a physically and chemically stable bond and to have good electrical and thermal conductivity. That is, in die bonding, semiconductor chips and lumps are firmly fixed on a substrate, and
It is desirable that the semiconductor chip and the substrate maintain good electrical conductivity, and that heat generated within the semiconductor chip be efficiently conducted and dissipated to the substrate.

Problems to be Solved by the Invention Needless to say, if a semiconductor chip peels off from a substrate due to insufficient adhesive strength, it is a completely defective semiconductor device. Even if a gap is created between the two, the electrical resistance or thermal resistance from the semiconductor chip to the substrate increases, leading to malfunction and shortened life of the semiconductor device.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a novel method that can achieve stronger adhesive strength during die bonding of semiconductor chips.

Means for solving the problem, that is, according to the present invention, a step of grinding the back surface of a semiconductor chip having a circuit mounted on a semiconductor substrate;
a die bonding process including at least a step of forming a metal coating on the back surface of the semiconductor chip subjected to the grinding process, wherein in the grinding process, the back surface of the semiconductor chip is roughened to a surface roughness Rff1al.
There is provided a method for manufacturing a semiconductor device, characterized in that finishing is performed so that l is within a range of 0.2 to 0.5.

Prior to the psychological bonding process or the metallizing process therefor, the semiconductor chip is subjected to a grinding process. This process is a process of polishing the back surface of a semiconductor wafer in order to smooth the back surface of the semiconductor wafer.

Conventionally, this treatment was intended only to make the surface smooth. However, as a result of detailed studies on this point, the inventors of the present invention have found that the adhesive strength is rather increased when the back surface of the chip is appropriately rough.

Therefore, the main feature of the method of the present invention is to perform a grinding process so that the back surface of the chip has appropriate roughness.

That is, according to the method of the present invention, when the surface roughness of a chip is expressed as the height difference R□8 between the top and the deepest part of the surface undulations, R□8 is 0.2 to 0.5 ( It has been found that it is preferable to be in the range of .mu.m). This value is particularly effective when a solder bonding method is applied to the GaAs chip and a metallizing process is performed by vapor deposition of a Ti film.

That is, when the surface roughness of a semiconductor chip is 0.2 μm or less, the adhesiveness decreases mainly due to a decrease in surface area, whereas when the surface roughness of a semiconductor chip exceeds 0.5 μm, the deep part of the undulations decreases. Adhesiveness actually deteriorates due to insufficient wraparound of the adhesive.

Note that the optimum value for the surface roughness of the semiconductor chip varies somewhat depending on the material of the semiconductor chip, the material of the back metallizing layer of the semiconductor chip, the type of die bonding method, etc., but the above-mentioned values are generally applicable.

EXAMPLES The method of the present invention will be described in more detail below with reference to the drawings, but what is shown below is only one example of the present invention, and does not limit the technical scope of the present invention in the same way. isn't it.

FIG. 2 is a schematic diagram generally showing the form of a die-bonded semiconductor chip.

As shown in FIG. 2, a semiconductor chip 3 is fixed onto a substrate 1 with a conductive adhesive 2 interposed therebetween.

FIG. 1 is an enlarged view of the mounting portion 4 of the semiconductor chip 3 in FIG. 2. As shown in FIG.

The back surface of the GaAs layer, which is the bottom surface of the chip 3 shown in FIG. 1, has rough undulations, and a metallizing layer 5 formed by Ti vapor deposition is formed on this back surface.

Furthermore, an Au layer 6 is formed on the surface of this Ti layer 5 in order to improve compatibility with the adhesive described later.
It is bonded to the substrate 1 via an adhesive layer 7 of Sn.

The back surface of the semiconductor chip 3 is subjected to a grinding process at the wafer stage to form a rough surface as shown in FIG. As shown in FIG. 1, "roughness" is expressed by the difference in height between the topmost part a and the deepest part a of the back surface of the semiconductor chip 3.

Further, the adhesive strength of the semiconductor chip 3 to the substrate 1 is expressed by Guisia strength. That is, die shear strength means the magnitude of the force required to push and peel off a chip fixed to a substrate by die bonding from the side.

Figure 3 shows the roughness of the back surface of the GaAs chip 3.
It is a graph showing the relationship between and die shear strength.

As shown in Figure 3, the die shear strength is R□8 (μm)
Effective strength is shown when is 0.2 to 0.5.

Furthermore, the adhesive for mekrise is not limited to Au-3n.

In this example, a GaAs chip was described, but
It goes without saying that when roughening the back surface of chips made of other semiconductor materials, die bonding strength can be improved if an appropriate roughness is determined in advance.

Effects of the Invention Until now, grinding of the back surface of a semiconductor chip has been carried out with the sole aim of increasing smoothness for the purpose of improving heat dissipation, shortening bonding wires, and improving chip handling. The invention is further based on a novel technical idea of providing a rough surface to improve die bonding strength.

That is, in the conventional die bonding process, the relationship between roughness and die shear strength has been ignored in the backside treatment of chips, so that satisfactory die bonding strength cannot be obtained. Accordingly, die bonding strength can be improved.

The method according to the invention is particularly suitable for GaA, which is difficult to mecurize.
Although it is advantageous in the die bonding process of semiconductor chips such as S, its application is not limited thereto.

[Brief explanation of the drawing]

FIG. 1 is an enlarged view of the bonded portion between the substrate and the semiconductor chip, FIG. 2 is a view showing the form of a die-bonded semiconductor chip, and FIG. 3 is a view of the back side of the chip. It is a graph showing the relationship between roughness R□X) and die shear strength. (Main reference numbers) 1...Substrate, 2...Conductor, 3...Semiconductor chip, 4...Mount part, 5...T1 layer, 6...Au layer, 7...Au-3n layer

Claims (2)

[Claims] (1) A method for manufacturing a semiconductor device including at least the steps of: grinding the back side of a semiconductor chip with a circuit mounted on a semiconductor substrate; and die bonding the semiconductor chip, the method comprising: , the back surface of the semiconductor chip has a surface roughness R_
A method for manufacturing a semiconductor device, characterized in that finishing is performed so that m_a_x is within a range of 0.2 to 0.5 μm. (2) Claim 1, wherein the semiconductor chip is a compound semiconductor chip with a circuit mounted on a GaAs substrate, and the metal coating is Ti deposited on the back surface of the semiconductor chip. A method for manufacturing a semiconductor device.