JPS63142640A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63142640A JPS63142640A JP28990486A JP28990486A JPS63142640A JP S63142640 A JPS63142640 A JP S63142640A JP 28990486 A JP28990486 A JP 28990486A JP 28990486 A JP28990486 A JP 28990486A JP S63142640 A JPS63142640 A JP S63142640A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- layer
- chip
- semiconductor
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 57
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000000034 method Methods 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 7
- 230000003746 surface roughness Effects 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 150000001875 compounds Chemical class 0.000 claims 1
- 239000000853 adhesive Substances 0.000 abstract description 13
- 230000008020 evaporation Effects 0.000 abstract 2
- 238000001704 evaporation Methods 0.000 abstract 2
- 238000005476 soldering Methods 0.000 abstract 1
- 230000001070 adhesive effect Effects 0.000 description 11
- 239000010410 layer Substances 0.000 description 9
- 239000000463 material Substances 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 239000006023 eutectic alloy Substances 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000005219 brazing Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、半導体チップの製造方法に関する。[Detailed description of the invention] Industrial applications The present invention relates to a method for manufacturing a semiconductor chip.
より詳細には、半導体チップのワイヤボンディング工程
に先立ってチップをリードフレームあるいはパンケージ
上に固定する所謂ダイボンディング工程にけるチップの
ボンディング面の新規な処理方法に関するものである。More specifically, the present invention relates to a novel method for processing the bonding surface of a semiconductor chip in a so-called die bonding process in which the chip is fixed on a lead frame or pancage prior to the wire bonding process of the semiconductor chip.
従来の技術
ダイボンディングとは、回路を搭載した半導体ウェハを
分割して作製した半導体チップを、セラミックパッケー
ジやリードフレーム等のグイパッド上の所定の位置に固
定する技術をいう。これによって、半導体チップはパッ
ケージと機械的および電気的に接続される。BACKGROUND ART Die bonding is a technique for fixing semiconductor chips, which are manufactured by dividing a semiconductor wafer mounted with a circuit, to a predetermined position on a support pad such as a ceramic package or a lead frame. This mechanically and electrically connects the semiconductor chip to the package.
ダイボンディングの手法としては、Ａｕ−３ｉ共晶合金
法、はんだ接着法、樹脂接着法に大別できる。Die bonding methods can be broadly classified into Au-3i eutectic alloy method, solder bonding method, and resin bonding method.
Ａｕ−３ｉ共晶合金法は、Ａｕ−３ｉ共晶合金の融点が
３７０℃と比較的低いことを利用しており、Ａｕめっき
したグイパッド上にチップの裏面を押し付けながら不活
性３囲気中で４００℃前後に加熱して両者を接着する方
法である。この方法は、機械的にも、また電気的にも良
好な接着状態が得られるので、現在最も広く利用されて
いる方法である。The Au-3i eutectic alloy method takes advantage of the fact that the melting point of the Au-3i eutectic alloy is relatively low at 370°C. This is a method of bonding the two by heating to around ℃. This method is currently the most widely used method because it provides a good adhesion state both mechanically and electrically.
これに対して、はんだ接着法は、接着剤としてｐｂ−３
ｎＳＡｕ −Ｇｅ、 Ａｕ−３ｉ、へｕ−３ｎ等のろう
材を用いる方法である。この場合、作業温度は２００乃
至４００℃の範囲にある。この方法では、半導体チップ
の裏面を予めＮｉ−Ａｕ５Ｔｉ −Ｎｉ−Ａｕ等でメタ
ライズしてろう材との馴染みをよくする付加的な操作が
必要である。しかしながら、この方法の長所は、基板と
半導体チップとの熱膨張率の違いにより生じる熱歪がは
んだ層に吸収されるので、半導体チップの面積が増大し
てもチップの破損が生じにくいことにある。従って、近
年の集積回路の大規模化、並びにＡｕの値段の高騰等に
伴って、その実用化が注目されている。On the other hand, the solder bonding method uses PB-3 as the adhesive.
This is a method using a brazing material such as nSAu-Ge, Au-3i, and Heu-3n. In this case, the working temperature is in the range 200-400°C. This method requires an additional operation in which the back surface of the semiconductor chip is previously metallized with Ni-Au5Ti-Ni-Au or the like to improve compatibility with the brazing material. However, the advantage of this method is that the thermal strain caused by the difference in thermal expansion coefficient between the substrate and the semiconductor chip is absorbed by the solder layer, so chip damage is less likely to occur even if the area of the semiconductor chip increases. . Therefore, with the recent increase in the scale of integrated circuits and the rise in the price of Au, its practical application is attracting attention.
樹脂接着法は、Ａｇ等の金属粉末を含有する樹脂を接着
剤として半導体チップを固定する方法であり、上述の２
つの方法よりも更に新規なものであるが、接着剤の硬化
に時間がかかる等の問題を含んでおり、今後の研究が待
たれている。The resin bonding method is a method of fixing a semiconductor chip using a resin containing metal powder such as Ag as an adhesive.
Although this method is more novel than the previous method, it has problems such as the time it takes for the adhesive to harden, so future research is awaited.
これらダイボンディング技術における課題は、物理的並
びに化学的に安定した結合が得られることと、電気並び
に熱の良好な伝導性である。即ち、ダイボンディングは
、半導体チ、ツブが基板上に強固に固定されると共に、
半導体チップと基板とが良好な導電性を保ち、更に、半
導体チップ内で発生した熱が効率良く基板に伝導−放散
されるようになされることが望ましい。The challenges in these die bonding techniques are to obtain a physically and chemically stable bond and to have good electrical and thermal conductivity. That is, in die bonding, semiconductor chips and lumps are firmly fixed on a substrate, and
It is desirable that the semiconductor chip and the substrate maintain good electrical conductivity, and that heat generated within the semiconductor chip be efficiently conducted and dissipated to the substrate.
発明が解決しようとする問題点
半導体チップの接着強度が不足したために、半導体チッ
プが基板から剥がれることが半導体装置として全く不良
品であることはいうまでもなく、また、単に半導体チッ
プと基板との間に間隙が生じた場合でも、半導体チップ
から基板への電気抵抗あるいは熱抵抗が高くなり、半導
体装置の誤動作、短寿命化を招くことになる。Problems to be Solved by the Invention Needless to say, if a semiconductor chip peels off from a substrate due to insufficient adhesive strength, it is a completely defective semiconductor device. Even if a gap is created between the two, the electrical resistance or thermal resistance from the semiconductor chip to the substrate increases, leading to malfunction and shortened life of the semiconductor device.
そこで、本発明の目的は、半導体チップのダイボンディ
ングに際し、より強固な接着強度を実現することのでき
る新規な方法を提供することにある。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a novel method that can achieve stronger adhesive strength during die bonding of semiconductor chips.
問題点を解決するための手段
即ち、本発明に従い、半導体基板上に回路を搭載した半
導体チップの裏面をグラインディング処理する工程と、
該グラインディング処理した前記半導体チップの裏面に
金属被膜を形成する工程とを少なくとも含むダイボンデ
ィング工程であって、前記グラインディング工程におい
て、前記半導体チップの裏面を、表面粗さＲｆｆ１ａｌ
ｌが０．２〜０．５の範囲内となるように仕上げること
を特徴とする半導体装置の製造方法が提供される。Means for solving the problem, that is, according to the present invention, a step of grinding the back surface of a semiconductor chip having a circuit mounted on a semiconductor substrate;
a die bonding process including at least a step of forming a metal coating on the back surface of the semiconductor chip subjected to the grinding process, wherein in the grinding process, the back surface of the semiconductor chip is roughened to a surface roughness Rff1al.
There is provided a method for manufacturing a semiconductor device, characterized in that finishing is performed so that l is within a range of 0.2 to 0.5.
心理
ボンディング処理あるいはそのためのメタライジング処
理に先立って、半導体チップにはグラインディング処理
が施される。この処理は、半導体ウェハの裏面の性状を
平滑にするために、半導体ウェハの裏面を研摩する処理
である。Prior to the psychological bonding process or the metallizing process therefor, the semiconductor chip is subjected to a grinding process. This process is a process of polishing the back surface of a semiconductor wafer in order to smooth the back surface of the semiconductor wafer.
従来、この処理については、表面をひたすら平滑にする
ことのみが意図されていた。しかしながら、本発明者等
はこの点について詳細な検討を行った結果、チップ裏面
が適度に粗い場合に、むしろ接着強度が高まることを見
出した。Conventionally, this treatment was intended only to make the surface smooth. However, as a result of detailed studies on this point, the inventors of the present invention have found that the adhesive strength is rather increased when the back surface of the chip is appropriately rough.
従って、本発明の方法は、チップ裏面が適度な粗さを有
するようにグラインディング処理を行うことをその主要
な特徴としている。Therefore, the main feature of the method of the present invention is to perform a grinding process so that the back surface of the chip has appropriate roughness.
即ち、本発明の方法に従えば、チップの表面粗さを、表
面の起伏の最頂部と最深部との落差Ｒ□８で表したとき
に、Ｒ□８が０．２〜０．５（μｍ）の範囲にあること
が好ましいことを見出した。この値は、ＧａＡｓチップ
にはんだ接着法を適用し、Ｔｉ膜の蒸着によるメタライ
ジング処理を施した場合に特に有効な値である。That is, according to the method of the present invention, when the surface roughness of a chip is expressed as the height difference R□8 between the top and the deepest part of the surface undulations, R□8 is 0.2 to 0.5 ( It has been found that it is preferable to be in the range of .mu.m). This value is particularly effective when a solder bonding method is applied to the GaAs chip and a metallizing process is performed by vapor deposition of a Ti film.
即ち、半導体チップの表面粗さが、０．２μｍ以下にな
ると、主に表面積の減少のために接着性が低下し、一方
、半導体チップの表面粗さが０．５μｍを越えると、起
伏の深部への接着剤の回り込み不良のために、却って接
着性が低下する。That is, when the surface roughness of a semiconductor chip is 0.2 μm or less, the adhesiveness decreases mainly due to a decrease in surface area, whereas when the surface roughness of a semiconductor chip exceeds 0.5 μm, the deep part of the undulations decreases. Adhesiveness actually deteriorates due to insufficient wraparound of the adhesive.
尚、この半導体チップ表面粗さの最適値は、半導体チッ
プの材質、半導体チップのバックメタライジング層の材
質、ダイボンディング方法の種類等によって多少変化す
るが、上述の値が概ね適用できる。Note that the optimum value for the surface roughness of the semiconductor chip varies somewhat depending on the material of the semiconductor chip, the material of the back metallizing layer of the semiconductor chip, the type of die bonding method, etc., but the above-mentioned values are generally applicable.
実施例
以下に、図面を参照して本発明の方法をより具体的に詳
述するが、以下に示すものは本発明の一実施例に過ぎず
、本発明の技術的範囲を同等制限するものではない。EXAMPLES The method of the present invention will be described in more detail below with reference to the drawings, but what is shown below is only one example of the present invention, and does not limit the technical scope of the present invention in the same way. isn't it.
第２図は、ダイボンディングされた半導体チップの形態
を一般的に示す概略図である。FIG. 2 is a schematic diagram generally showing the form of a die-bonded semiconductor chip.
第２図に示すように、基板１上に導電性の接着剤２を介
して半導体チップ３が固定されている。As shown in FIG. 2, a semiconductor chip 3 is fixed onto a substrate 1 with a conductive adhesive 2 interposed therebetween.
第１図は、第２図における半導体チップ３のマウント部
４を拡大して示した図である。FIG. 1 is an enlarged view of the mounting portion 4 of the semiconductor chip 3 in FIG. 2. As shown in FIG.
第１図に示す、チップ３の下面であるＧａＡｓ層の裏面
は粗い起伏を有しており、この裏面にはＴｉ蒸着による
メタライジング層５が形成されている。The back surface of the GaAs layer, which is the bottom surface of the chip 3 shown in FIG. 1, has rough undulations, and a metallizing layer 5 formed by Ti vapor deposition is formed on this back surface.
更に、このＴｉ層５の表面には後述する接着剤との馴染
みをよくするために、Ａｕ層６が形成されており、Ａｕ
Ｓｎの接着剤層７を介して基板１と接着されている。Furthermore, an Au layer 6 is formed on the surface of this Ti layer 5 in order to improve compatibility with the adhesive described later.
It is bonded to the substrate 1 via an adhesive layer 7 of Sn.
半導体チップ３の裏面は、ウェハ段階でグラインディン
グ処理し、第２図のような粗面を形成している。第１図
中に示すように、゛粗さ′″は、半導体チップ３の裏面
の最頂部ａと最深部すとの落差を以って表される。The back surface of the semiconductor chip 3 is subjected to a grinding process at the wafer stage to form a rough surface as shown in FIG. As shown in FIG. 1, "roughness" is expressed by the difference in height between the topmost part a and the deepest part a of the back surface of the semiconductor chip 3.
また、半導体チップ３の基板１に対する接着強度は、グ
イシア強度を以って表される。即ち、ダイシア強度とは
、ダイボンディングにより基板に固定されたチップを側
面から押して、剥離するのに要すた力の大きさを意味す
る。Further, the adhesive strength of the semiconductor chip 3 to the substrate 1 is expressed by Guisia strength. That is, die shear strength means the magnitude of the force required to push and peel off a chip fixed to a substrate by die bonding from the side.
第３図は、ＧａＡｓチップ３の裏面の粗さくＲ，、、）
とダイシア強度との関係を表すグラフである。Figure 3 shows the roughness of the back surface of the GaAs chip 3.
It is a graph showing the relationship between and die shear strength.
第３図に示すように、ダイシア強度は、Ｒ□８（μｍ）
が０．２〜０．５の時に有効な強度を示している。As shown in Figure 3, the die shear strength is R□8 (μm)
Effective strength is shown when is 0.2 to 0.5.
また、メクライズのための接着剤はＡｕ−３ｎには限定
されない。Furthermore, the adhesive for mekrise is not limited to Au-3n.
本実施例においてはＧａＡｓチップについて述べたが、
他の半導体材料から成るチップについても、裏面に粗面
を施す場合、あらかじめ適度な粗さを定めて行えば、ダ
イボンディング強度が向上することは言うまでもない。In this example, a GaAs chip was described, but
It goes without saying that when roughening the back surface of chips made of other semiconductor materials, die bonding strength can be improved if an appropriate roughness is determined in advance.
発明の効果
半導体チップ裏面のグラインディングは、これまで熱放
散性向上、ボンディングワイヤの短縮化、チップのハン
ドリング性向上等を目的として、平滑性を高めることの
みを目指して行われてきたが、本発明はさらに、ダイボ
ンディング強度向上のために粗面を施すという新規な技
術的思想に基づくものである。Effects of the Invention Until now, grinding of the back surface of a semiconductor chip has been carried out with the sole aim of increasing smoothness for the purpose of improving heat dissipation, shortening bonding wires, and improving chip handling. The invention is further based on a novel technical idea of providing a rough surface to improve die bonding strength.
即ち、これまでのダイボンディング工程におけるチップ
裏面処理はこの粗さとダイシア強度の関係が無視されて
きたために、満足なダイボンディング強度が得られなか
ったが、本発明に従って適切な粗さを持たせることによ
って、ダイボンディング強度を向上させることができる
。That is, in the conventional die bonding process, the relationship between roughness and die shear strength has been ignored in the backside treatment of chips, so that satisfactory die bonding strength cannot be obtained. Accordingly, die bonding strength can be improved.
本発明による方法は特に、メクライズの施し難いＧａＡ
ｓ等の半導体チップのダイボンディング工程において有
利であるが、その適用はこれに限定されるものではない
。The method according to the invention is particularly suitable for GaA, which is difficult to mecurize.
Although it is advantageous in the die bonding process of semiconductor chips such as S, its application is not limited thereto.
第１図は、基板と半導体チップとの接着部を拡大して示
した図であり、
第２図は、ダイボンディングされた半導体チップの形態
を示す図であり、
第３図は、チップ裏面の粗さくＲ□Ｘ）とダイシア強度
との関係を表すグラフである。
（主な参照番号）
１・・基板、
２・・導体、
３・・半導体チップ、
４・・マウント部、
５・・Ｔ１層、
６・・Ａｕ層、
７・・Ａｕ −３ｎ層FIG. 1 is an enlarged view of the bonded portion between the substrate and the semiconductor chip, FIG. 2 is a view showing the form of a die-bonded semiconductor chip, and FIG. 3 is a view of the back side of the chip. It is a graph showing the relationship between roughness R□X) and die shear strength. (Main reference numbers) 1...Substrate, 2...Conductor, 3...Semiconductor chip, 4...Mount part, 5...T1 layer, 6...Au layer, 7...Au-3n layer
Claims (2)
面をグラインディング処理する工程と、該半導体チップ
をダイボンディング処理する工程とを少なくとも含む半
導体装置の製造方法であって、前記グラインディング工
程において、前記半導体チップの裏面を、表面粗さＲ＿
ｍ＿ａ＿ｘが０．２〜０．５μｍの範囲内となるように
仕上げることを特徴とする半導体装置の製造方法。(1) A method for manufacturing a semiconductor device including at least the steps of: grinding the back side of a semiconductor chip with a circuit mounted on a semiconductor substrate; and die bonding the semiconductor chip, the method comprising: , the back surface of the semiconductor chip has a surface roughness R_
A method for manufacturing a semiconductor device, characterized in that finishing is performed so that m_a_x is within a range of 0.2 to 0.5 μm.
した化合物半導体チップであり、前記金属被膜が前記半
導体チップの裏面に蒸着したＴｉであることを特徴とす
る特許請求の範囲第１項に記載の半導体装置の製造方法
。(2) Claim 1, wherein the semiconductor chip is a compound semiconductor chip with a circuit mounted on a GaAs substrate, and the metal coating is Ti deposited on the back surface of the semiconductor chip. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28990486A JPS63142640A (en) | 1986-12-05 | 1986-12-05 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28990486A JPS63142640A (en) | 1986-12-05 | 1986-12-05 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63142640A true JPS63142640A (en) | 1988-06-15 |
Family
ID=17749273
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28990486A Pending JPS63142640A (en) | 1986-12-05 | 1986-12-05 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63142640A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003110064A (en) * | 2001-07-26 | 2003-04-11 | Denso Corp | Semiconductor device |
| JP2005109526A (en) * | 2001-07-26 | 2005-04-21 | Denso Corp | Semiconductor device |
| US7145254B2 (en) | 2001-07-26 | 2006-12-05 | Denso Corporation | Transfer-molded power device and method for manufacturing transfer-molded power device |
| JP2008078679A (en) * | 2001-07-26 | 2008-04-03 | Denso Corp | Semiconductor device |
| JP2018101768A (en) * | 2016-12-16 | 2018-06-28 | 東洋インキＳｃホールディングス株式会社 | Composite member |
| US10163829B2 (en) | 2017-02-20 | 2018-12-25 | Murata Manufacturing Co., Ltd. | Compound semiconductor substrate and power amplifier module |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4948264A (en) * | 1972-09-14 | 1974-05-10 | ||
| JPS5484476A (en) * | 1977-12-19 | 1979-07-05 | Toshiba Corp | Semiconductor pellet with improved juncture |
| JPS5521106A (en) * | 1978-07-31 | 1980-02-15 | Nec Home Electronics Ltd | Method of forming ohmic electrode |
| JPS58218129A (en) * | 1982-06-11 | 1983-12-19 | Nec Corp | Semiconductor device |
-
1986
- 1986-12-05 JP JP28990486A patent/JPS63142640A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4948264A (en) * | 1972-09-14 | 1974-05-10 | ||
| JPS5484476A (en) * | 1977-12-19 | 1979-07-05 | Toshiba Corp | Semiconductor pellet with improved juncture |
| JPS5521106A (en) * | 1978-07-31 | 1980-02-15 | Nec Home Electronics Ltd | Method of forming ohmic electrode |
| JPS58218129A (en) * | 1982-06-11 | 1983-12-19 | Nec Corp | Semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003110064A (en) * | 2001-07-26 | 2003-04-11 | Denso Corp | Semiconductor device |
| JP2005109526A (en) * | 2001-07-26 | 2005-04-21 | Denso Corp | Semiconductor device |
| US7145254B2 (en) | 2001-07-26 | 2006-12-05 | Denso Corporation | Transfer-molded power device and method for manufacturing transfer-molded power device |
| JP2008078679A (en) * | 2001-07-26 | 2008-04-03 | Denso Corp | Semiconductor device |
| JP2018101768A (en) * | 2016-12-16 | 2018-06-28 | 東洋インキＳｃホールディングス株式会社 | Composite member |
| US10163829B2 (en) | 2017-02-20 | 2018-12-25 | Murata Manufacturing Co., Ltd. | Compound semiconductor substrate and power amplifier module |
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