JPH0555635A - Flip chip connection structure of electronic part - Google Patents
Flip chip connection structure of electronic partInfo
- Publication number
- JPH0555635A JPH0555635A JP23732391A JP23732391A JPH0555635A JP H0555635 A JPH0555635 A JP H0555635A JP 23732391 A JP23732391 A JP 23732391A JP 23732391 A JP23732391 A JP 23732391A JP H0555635 A JPH0555635 A JP H0555635A
- Authority
- JP
- Japan
- Prior art keywords
- gold
- tin
- bump
- bumps
- glass substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 66
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 58
- 229910052737 gold Inorganic materials 0.000 claims abstract description 58
- 239000010931 gold Substances 0.000 claims abstract description 58
- 229910052718 tin Inorganic materials 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 229910052709 silver Inorganic materials 0.000 claims abstract description 19
- 239000004332 silver Substances 0.000 claims abstract description 19
- 239000011521 glass Substances 0.000 abstract description 34
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 abstract description 18
- 238000000034 method Methods 0.000 abstract description 15
- 230000015572 biosynthetic process Effects 0.000 abstract description 13
- 230000005496 eutectics Effects 0.000 abstract description 12
- 229910052751 metal Inorganic materials 0.000 abstract description 6
- 239000002184 metal Substances 0.000 abstract description 6
- 150000001875 compounds Chemical class 0.000 abstract description 3
- 230000010355 oscillation Effects 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 19
- 238000005755 formation reaction Methods 0.000 description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 238000011109 contamination Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 239000011135 tin Substances 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011133 lead Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
- Led Device Packages (AREA)
- Led Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の利用分野】この発明は電子部品のフリップチッ
プ接続構造に関し、電子部品を基板にフリップチップ接
続する際に用いるものである。この発明は特に、ＬＥＤ
アレイ等の受発光素子アレイをガラス等の透明基板にフ
リップチップ接続する際に用いる。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip chip connection structure for electronic parts, which is used for flip chip connecting electronic parts to a substrate. The invention is particularly applicable to LEDs
It is used when flip-chip connecting an array of light emitting / receiving elements such as an array to a transparent substrate such as glass.
【０００２】[0002]
【従来技術】従来のフリップチップ接続構造では、電子
部品と基板とにバンプを形成した後、収縮性の接着剤で
電子部品を基板に結合し、接着剤の収縮力でバンプを接
続するものが知れらている（特開平２−１５５，２５７
号）。またバンプ材料の組合せを半田と金、あるいは半
田と半田とし、リフロー炉でバンプとバンプとを接続す
るものも周知である（例えば特公平２−２６，７８０
号）。更に日経マイクロデバイス，１９９０年１２月
号，１５頁は、ワイヤボンディングに類似の手法で金バ
ンプを形成することを提案している。この手法では、金
の細線をワイヤボンディングして金ボールを形成した
後、ボールの上部で金線を切断し、金バンプとする。こ
の提案では他方のバンプには半田バンプを用い、リフロ
ー炉で熱処理して金バンプと半田バンプとを接続する。2. Description of the Related Art In a conventional flip-chip connection structure, bumps are formed on an electronic component and a substrate, then the electronic component is bonded to the substrate by a shrinkable adhesive, and the bumps are connected by the shrinking force of the adhesive. Known (Japanese Patent Laid-Open No. 2-155,257)
issue). It is also well known that the combination of bump materials is solder and gold, or solder and solder, and the bumps are connected in a reflow furnace (for example, Japanese Patent Publication No. 2-26,780).
issue). Furthermore, Nikkei Microdevices, December 1990, page 15, proposes to form gold bumps by a method similar to wire bonding. In this method, a gold thin wire is wire-bonded to form a gold ball, and then the gold wire is cut at the upper part of the ball to form a gold bump. In this proposal, a solder bump is used for the other bump, and heat treatment is performed in a reflow furnace to connect the gold bump and the solder bump.
【０００３】半田バンプの形成では、特公平２−２６，
７８０号に示されているように、最初に基板や電子部品
にクロムやモリブデン等のバリア皮膜を形成し、バリア
皮膜上に金、ニッケル、銅等の導電性金属膜を形成す
る。次いでレジストでバンプの形成部以外をマスクし、
半田メッキによってバンプを形成する。バンプの形成後
には、レジストを除去し、導電性金属膜やバリア皮膜を
エッチングする工程が必要である。このことから明かな
ように、バンプの形成工程は長く、かつバリア皮膜や導
電性金属膜による汚染や、レジストでマスクした部分へ
の半田の拡散による汚染が問題となる。半田バンプの他
の問題として、半田がバンプの下地の電極の金メッキを
食べるため、接続が失敗し易いことが有る。結局半田バ
ンプは形成工程が複雑で、ＩＣ等を汚染する可能性が有
り、接続時に電極の金メッキと反応し易い。これらのた
め半田バンプを用いないフリップチップ接続構造が必要
である。In forming solder bumps, Japanese Patent Publication No. 26-26,
As shown in Japanese Patent No. 780, first, a barrier film such as chromium or molybdenum is formed on a substrate or an electronic component, and a conductive metal film such as gold, nickel or copper is formed on the barrier film. Next, mask the area other than the bump formation area with a resist,
Bumps are formed by solder plating. After forming the bumps, a step of removing the resist and etching the conductive metal film or the barrier film is required. As is clear from this, the bump forming process is long, and there is a problem of contamination due to the barrier film or the conductive metal film and contamination due to diffusion of solder to the portion masked with the resist. Another problem with solder bumps is that the solder eats the gold plating of the electrodes underlying the bumps, which can easily lead to connection failures. After all, the solder bump has a complicated forming process and may contaminate the IC or the like, and easily reacts with the gold plating of the electrode at the time of connection. Therefore, a flip chip connection structure that does not use solder bumps is required.
【０００４】[0004]
【発明の課題】この発明の課題は、半田バンプを用いな
いフリップチップ接続構造を提供し、(1) バンプの形
成を容易にすると共に、(2) バンプ相互の接続を容易
にし、(3) バンプ形成工程での電子部品の汚染を防止
する、ことにある。An object of the present invention is to provide a flip-chip connection structure that does not use solder bumps, and (1) facilitates the formation of bumps, and (2) facilitates the mutual connection of bumps, and (3) The purpose is to prevent contamination of electronic components in the bump forming process.
【０００５】[0005]
【発明の構成】この発明は、電子部品に設けたバンプと
基板に設けたバンプとを接続した電子部品のフリップチ
ップ接続構造において、一方のバンプを錫を主成分とす
るバンプとし、他方のバンプを金もしくは銀を主成分と
するバンプとしたことを特徴とする、電子部品のフリッ
プチップ接続構造に有る。According to the present invention, in a flip chip connection structure of an electronic component in which a bump provided on an electronic component and a bump provided on a substrate are connected, one bump is a bump whose main component is tin and the other bump is a bump. Is a bump having gold or silver as a main component, and is in a flip-chip connection structure for electronic parts.
【０００６】[0006]
【発明の作用】この発明では、バンプの材料を一方を金
もしくは銀を主成分とするものとし、他方を錫を主成分
とするものとする。錫は金や銀と低温で共晶化合物を形
成し、容易にバンプ相互の接続ができる。例えば金と錫
との共融温度は２１７℃、銀と錫では２２７℃である。
次に金や銀は細い線に線引きすることが容易で、ワイヤ
ボンディングに類似の手法で容易にバンプを形成でき
る。同様に錫も細い錫線を得るのが容易で、バンプの形
成が容易である。錫線は更に金線や銀線に比べ軟らか
く、ボール形成後の切断が容易でバンプの形成が特に容
易である。In the present invention, one of the bump materials has gold or silver as a main component and the other has tin as a main component. Tin forms a eutectic compound with gold or silver at low temperature, and bumps can be easily connected to each other. For example, the eutectic temperature of gold and tin is 217 ° C, and that of silver and tin is 227 ° C.
Next, gold or silver can be easily drawn into a thin wire, and a bump can be easily formed by a method similar to wire bonding. Similarly, with tin, it is easy to obtain a thin tin wire, and it is easy to form bumps. The tin wire is softer than the gold wire and the silver wire, and is easy to cut after the ball is formed and the bump is particularly easy to form.
【０００７】これらのため、バンプの一方を金や銀、他
方を錫とすると、これらの細線を基板や電子部品にボン
ディングしてボールを形成した後、ボールの上部で線を
切断することでバンプを形成できる。金や銀と錫は２０
０℃程度で共晶化合物を形成するので、熱圧着や超音波
圧着等で容易にバンプ相互を接続できる。Therefore, if one of the bumps is made of gold or silver and the other is made of tin, these fine wires are bonded to a substrate or an electronic component to form a ball, and then the wire is cut at the upper part of the ball to form the bump. Can be formed. 20 for gold, silver and tin
Since the eutectic compound is formed at about 0 ° C., bumps can be easily connected to each other by thermocompression bonding or ultrasonic pressure bonding.
【０００８】[0008]
【実施例】ガラス基板への受発光素子アレイのフリップ
チップ接続を例に実施例を説明するが、一般のＩＣチッ
プのフリップチップ接続も同様に実施できる。ガラス基
板を例としたのは、ガラスは熱衝撃に弱く、表面が平滑
なためバンプの下地の電極の付着強度が低く、フリップ
チップ接続が特に困難な基板だからである。またガラス
基板を用いた他の理由は、受発光素子アレイの受発光面
をガラス基板に向き合わせ、ガラス基板を通じて受発光
を行い、受発光素子アレイの表面高さをガラス基板を基
準に揃え、受発光素子アレイの表面高さのばらつきによ
る焦点精度の低下を防止するためである。このような点
を除けば、アルミナ基板等へのＩＣチップのフリップチ
ップ接続でも、同様に実施できる。EXAMPLE An example will be described by taking a flip chip connection of a light emitting and receiving element array to a glass substrate as an example, but a flip chip connection of a general IC chip can be similarly performed. The glass substrate is taken as an example because glass is vulnerable to thermal shock, and the surface is smooth, so that the adhesion strength of electrodes under the bumps is low and flip-chip connection is particularly difficult. Another reason for using the glass substrate is to align the light receiving and emitting surface of the light emitting and receiving element array with the glass substrate, perform light reception and emission through the glass substrate, and align the surface height of the light receiving and emitting element array with the glass substrate as a reference. This is to prevent a decrease in focus accuracy due to a variation in surface height of the light emitting / receiving element array. Except for such a point, flip-chip connection of an IC chip to an alumina substrate or the like can be similarly performed.
【０００９】図１において、２はガラス等の透明基板、
４はＧａＡｓＬＥＤアレイである。ＧａＡｓＬＥＤアレ
イ４に変え、ＣＣＤや光電池アレイ等の受光素子アレイ
を用いても同様である。６はＧａＡｓにＺｎ等の不純物
を注入した発光体で、発光体６の底部と基板のＧａＡｓ
層との界面が発光面となる。８はＬＥＤアレイ４に接続
した共通リードで、例えばリードフレームをＬＥＤアレ
イ４の裏面の共通電極に熱圧着した後、リードフレーム
の基部を切断したものとする。１０はガラス基板２上の
ポリイミド樹脂等の絶縁層、１２はガラス基板２上の共
通電極である。１４はＬＥＤアレイ４に設けた電極で、
例えばＡｌ電極とし、１６はガラス基板２上に設けた電
極で、例えばＡｌ電極上に金をメッキ、あるいは金を蒸
着やスパッタリングで積層したものとするが、金被覆は
設けなくても良い。金被覆を設ける場合、バンプ形成部
にのみ設ければ良い。In FIG. 1, 2 is a transparent substrate such as glass,
4 is a GaAs LED array. The same applies when a light receiving element array such as a CCD or a photocell array is used instead of the GaAs LED array 4. Reference numeral 6 denotes a light-emitting body in which impurities such as Zn are injected into GaAs, and the bottom of the light-emitting body 6 and the GaAs of the substrate.
The interface with the layer serves as a light emitting surface. Reference numeral 8 denotes a common lead connected to the LED array 4, and for example, the lead frame is thermocompression-bonded to the common electrode on the back surface of the LED array 4, and then the base portion of the lead frame is cut. Reference numeral 10 is an insulating layer such as a polyimide resin on the glass substrate 2, and 12 is a common electrode on the glass substrate 2. 14 is an electrode provided on the LED array 4,
For example, an Al electrode is provided, and 16 is an electrode provided on the glass substrate 2. For example, gold is plated on the Al electrode or gold is laminated by vapor deposition or sputtering, but the gold coating may not be provided. When the gold coating is provided, it may be provided only on the bump forming portion.
【００１０】１８は金バンプで、金を主成分とするもの
であれば良く、例えば１０重量％以下の範囲で銀やパラ
ディウム、ニッケル、錫等を含有させても良い。金バン
プ１８に変えて、銀バンプを用いても良く、その場合に
も例えば１０重量％以下の範囲で、銀を金やパラディウ
ム、錫等で置換しても良い。２０は錫バンプで、錫を主
成分とするものであれば良く、例えば１０重量％以下の
範囲でニッケルや鉛、金、銀等を含有させても良い。錫
バンプ２０や金バンプ１８に対する置換の範囲は、細線
への線引きを困難にせず、金や銀と錫との共晶形成を妨
げない範囲である。ＬＥＤアレイ４に金バンプ１８を設
け、ガラス基板２に錫バンプ２０を設けたのは、錫バン
プ２０の形成に用いる錫線が軟らかく、バンプ形成時の
錫のボール形成が容易で、かつボール形成後の錫線の切
断が容易だからである。これは脆弱で電極１６の付着強
度が低い、ガラス基板２に特に適している。またガラス
基板２側の電極１６の表面を金で被覆したのは、錫と金
との合金形成反応を利用し、バンプ２０の形成時のボー
ル形成を容易にするためである。これらの点を除けば、
ガラス基板２側に金バンプを設け、ＬＥＤアレイ４側に
錫バンプを設けても良い。Reference numeral 18 denotes a gold bump which has gold as a main component, and may contain silver, palladium, nickel, tin or the like in a range of, for example, 10% by weight or less. Instead of the gold bumps 18, silver bumps may be used, and in that case, silver may be replaced with gold, palladium, tin or the like in a range of, for example, 10% by weight or less. Reference numeral 20 denotes a tin bump as long as it has tin as a main component, and may contain nickel, lead, gold, silver or the like in a range of 10% by weight or less. The substitution range for the tin bumps 20 and the gold bumps 18 is a range that does not make drawing a fine wire difficult and does not hinder the formation of a eutectic crystal of gold or silver and tin. The gold bumps 18 are provided on the LED array 4 and the tin bumps 20 are provided on the glass substrate 2 because the tin wire used for forming the tin bumps 20 is soft, and the tin balls can be easily formed during the bump formation. This is because it is easy to cut the tin wire later. This is particularly suitable for the glass substrate 2 which is fragile and has low adhesion strength of the electrode 16. Further, the reason why the surface of the electrode 16 on the glass substrate 2 side is coated with gold is to facilitate the ball formation during the formation of the bump 20 by utilizing the alloy formation reaction of tin and gold. Apart from these points,
Gold bumps may be provided on the glass substrate 2 side and tin bumps may be provided on the LED array 4 side.
【００１１】図２に、ＬＥＤアレイ４上の金バンプ１８
の配置を示す。電極１４は発光体６を縦断するように形
成し、発光体６の両側に金バンプ１８を設けた。図３
に、ガラス基板２上の錫バンプ２０の配置を示す。ガラ
ス基板２には例えば４０アレイ程度、ＬＥＤアレイ４を
直線状に配置し、電極１６はＬＥＤアレイ４毎にじぐざ
ぐに折り返して配置する。電極１６は、ＬＥＤアレイ４
からの発光を妨げないように、発光体６の部分には設け
ず、この部分をＬＥＤアレイ４の電極１４でバイパスす
る。このため発光体６毎に、図の上下２カ所で金バンプ
１８と錫バンプ２０を用いてフリップチップ接続する。In FIG. 2, gold bumps 18 on the LED array 4 are shown.
Shows the arrangement of. The electrode 14 was formed so as to vertically cut the light emitting body 6, and gold bumps 18 were provided on both sides of the light emitting body 6. Figure 3
The arrangement of the tin bumps 20 on the glass substrate 2 is shown in FIG. For example, about 40 arrays of LED arrays 4 are linearly arranged on the glass substrate 2, and the electrodes 16 are arranged so that each LED array 4 is folded back. The electrode 16 is the LED array 4
In order not to interfere with the light emission from, the light emitting body 6 is not provided in the portion, and this portion is bypassed by the electrode 14 of the LED array 4. For this reason, each light emitting body 6 is flip-chip connected using the gold bumps 18 and the tin bumps 20 at the two upper and lower positions in the drawing.
【００１２】図４により、フリップチップ接続の工程を
説明する。ガラス基板２に電極１６を形成し、ＬＥＤア
レイ４に電極１４を形成する。ＬＥＤアレイ４には金バ
ンプ１８を形成し、ガラス基板２には錫バンプ２０を形
成する。これらのバンプの形成は、金や錫の細線をキャ
ピラリーから供給し、ＬＥＤアレイ４やガラス基板２を
加熱した状態で、例えば超音波振動を金や錫の細線とＬ
ＥＤアレイ４やガラス基板２の間に加えて、金や錫の細
線をＬＥＤアレイ４やガラス基板２に押し付ける。この
時の熱と超音波振動による摩擦熱、加圧力で、金線や錫
線はＬＥＤアレイ４やガラス基板２にボンディングされ
る。ボンディングは、熱のみを用いたものや超音波振動
のみを用いたものでも良い。ボンディングにより、金線
や錫線の先端のＬＥＤアレイ４やガラス基板２へのボン
ディング部はボール状となり、ボンディング直後にボー
ルの上部で金線や錫線を切断すると、バンプ１８，２０
が得られる。金線や錫線の切断は、例えば超音波を加え
ながらキャピラリーを移動させて超音波振動で切断す
る、あるいはキャピラリーの先端を局所的に発熱させ
る、またレーザー等で切断するようにすれば良い。これ
らのバンプ形成方法自体は日経マイクロデバイスに記載
のものと変わらないが、錫線は軟質で、脆弱なガラス基
板２上の電極１６に対してもボール形成が容易で、かつ
ボール形成後の切断が容易である。また半田と異なり錫
は細線に線引きするのが容易で、かつ金線に比べ安価
で、軟質なため、ボール形成時の温度を低くし、超音波
振動を弱くし、かつ加圧力を小さくできる。例えば金と
錫との共融点は２１７℃で、電極１６の表面の金と錫線
とは超音波や熱で接触面を２００℃程度に加熱すれば、
共晶を形成してボールを形成できる。The process of flip-chip connection will be described with reference to FIG. The electrodes 16 are formed on the glass substrate 2 and the electrodes 14 are formed on the LED array 4. Gold bumps 18 are formed on the LED array 4, and tin bumps 20 are formed on the glass substrate 2. These bumps are formed by supplying fine wires of gold or tin from the capillary and heating the LED array 4 or the glass substrate 2 with ultrasonic vibration, for example, by applying ultrasonic vibration to the fine wires of gold or tin.
In addition to the space between the ED array 4 and the glass substrate 2, a thin wire of gold or tin is pressed against the LED array 4 and the glass substrate 2. The gold wire and the tin wire are bonded to the LED array 4 and the glass substrate 2 by the heat at this time and the frictional heat and the applied pressure due to the ultrasonic vibration. The bonding may use only heat or only ultrasonic vibration. By bonding, the tip of the gold wire or tin wire is bonded to the LED array 4 or the glass substrate 2 into a ball shape, and if the gold wire or tin wire is cut above the ball immediately after bonding, the bumps 18, 20
Is obtained. The gold wire or the tin wire may be cut, for example, by moving the capillary while applying ultrasonic waves to cut by ultrasonic vibration, or by locally heating the tip of the capillary, or cutting with a laser or the like. Although the bump forming method itself is the same as that described in Nikkei Microdevice, the tin wire is soft, and the ball 16 can be easily formed even on the electrode 16 on the fragile glass substrate 2, and the cutting after the ball is formed. Is easy. Further, unlike solder, tin is easy to draw into a fine wire, cheaper than gold wire, and soft, so that the temperature during ball formation can be lowered, ultrasonic vibrations can be weakened, and pressure can be reduced. For example, the eutectic point of gold and tin is 217 ° C., and the contact surface between the gold and tin wire on the surface of the electrode 16 is heated to about 200 ° C. by ultrasonic waves or heat.
A eutectic can be formed to form a ball.
【００１３】このようにワイヤボンディングと類似の手
法で金バンプ１８と錫バンプ２０を形成すると、金バン
プ１８や錫バンプ２０の大きさを一定にできる。これは
金線や錫線の線径で、バンプ１８，２０の大きさが定ま
るからである。次にバンプの形成工程はワイヤボンディ
ングと類似で、半田バンプの形成に比べ工程数が少な
い。更にバリア皮膜や導電性金属膜の形成、半田メッキ
等に伴う、ＬＥＤアレイ４やガラス基板２上の電極１６
の汚染がないため、バンプ形成時のＬＥＤアレイ４の無
駄が無い。By thus forming the gold bumps 18 and the tin bumps 20 by a method similar to wire bonding, the sizes of the gold bumps 18 and the tin bumps 20 can be made constant. This is because the diameter of the gold wire or the tin wire determines the size of the bumps 18 and 20. Next, the bump formation process is similar to wire bonding, and the number of processes is smaller than that of solder bump formation. Further, the electrodes 16 on the LED array 4 and the glass substrate 2 due to formation of a barrier film or a conductive metal film, solder plating, etc.
Therefore, the LED array 4 is not wasted when bumps are formed.
【００１４】バンプ１８，２０の形成後、例えばコレッ
ト２２でＬＥＤアレイ４をピックアップし、ダイマウン
ターで金バンプ１８を錫バンプ２０に熱圧着する。この
ため例えば図示しないダイマウンターでガラス基板２を
２００℃程度に加熱し、コレット２２でＬＥＤアレイ４
を接続位置に降下させれば良い。このようにすれば、コ
レット２２からの加圧とダイマウンターによる加熱で、
金バンプ１８は錫バンプ２０と共晶を形成し、相互に接
続できる。共晶の形成はバンプ１８，２０の奥まで進行
させる必要はなく、表面部だけで良い。また加熱温度は
共融点の２１７℃よりも低くても良く、ダイマウンター
で均一に加熱する変わりに超音波振動で金バンプ１８と
錫バンプ２０の接触面を加熱しても良い。銀と錫との共
融点は２２７℃で金と錫との共融の場合と同様に低く、
金バンプ１８に変えて銀バンプを用いても良い。After the bumps 18 and 20 are formed, the LED array 4 is picked up by, for example, a collet 22, and the gold bump 18 is thermocompression bonded to the tin bump 20 by a die mounter. Therefore, for example, the glass substrate 2 is heated to about 200 ° C. by a die mounter (not shown), and the collet 22 is used to drive the LED array 4
Should be lowered to the connection position. By doing this, the pressure from the collet 22 and the heating by the die mounter
The gold bump 18 forms a eutectic crystal with the tin bump 20 and can be connected to each other. The formation of the eutectic does not have to proceed to the depths of the bumps 18 and 20, but only the surface portion. The heating temperature may be lower than the eutectic point of 217 ° C., and the contact surface between the gold bump 18 and the tin bump 20 may be heated by ultrasonic vibration instead of being uniformly heated by the die mounter. The eutectic point of silver and tin is 227 ° C, which is as low as that of the eutectic of gold and tin.
Silver bumps may be used instead of the gold bumps 18.
【００１５】金バンプ１８と錫バンプ２０は低温で接続
できるため、ＬＥＤアレイ４やガラス基板２に負荷が加
わらない。また半田バンプの場合と異なりリフロー炉で
の処理を要しないため、半田の拡散により電極１６表面
の金層が侵されたり、あるいは半田が拡散して発光体６
が汚染されたりすることが無い。そして１回のダイマウ
ンターによる熱圧着で、１個のＬＥＤアレイ４全体をフ
リップチップ接続でき、単純な工程でバンプを形成でき
る。これらのためバンプ相互の接続時の収率が高く、高
価なＬＥＤアレイ４の損失が少ない。Since the gold bump 18 and the tin bump 20 can be connected at a low temperature, no load is applied to the LED array 4 and the glass substrate 2. Further, unlike the case of the solder bump, since the treatment in the reflow furnace is not required, the gold layer on the surface of the electrode 16 is attacked by the diffusion of the solder, or the solder is diffused and the light emitting member 6 is emitted.
Is never contaminated. Then, one LED array 4 as a whole can be flip-chip connected by thermocompression bonding by a die mounter, and bumps can be formed by a simple process. Therefore, the yield when connecting the bumps to each other is high, and the loss of the expensive LED array 4 is small.
【００１６】[0016]
【発明の効果】以上に述べたように、この発明では以下
の効果が得られる。 (1) 錫線や金線、あるいは銀線を用いてバンプを形成
するため、バンプの形成が容易で均質なバンプが得られ
る。 (2) バンプの形成工程が単純で、バンプ形成時の電子
部品や基板の汚染・無駄がない。 (3) 金バンプや銀バンプは２００℃程度で錫バンプと
接続できるため、バンプ相互の接続が容易で、接続不良
や接続時の歩止まりの低下が無い。 (4) 用いる錫バンプは極めて安価である。As described above, the present invention has the following advantages. (1) Since the bumps are formed using tin wires, gold wires, or silver wires, the bumps can be easily formed and uniform bumps can be obtained. (2) The bump forming process is simple, and there is no contamination or waste of electronic components or substrates during bump formation. (3) Since gold bumps and silver bumps can be connected to tin bumps at about 200 ° C, the bumps can be easily connected to each other, and there is no connection failure or reduction in yield at the time of connection. (4) The tin bumps used are extremely inexpensive.
【図１】 実施例の側面図FIG. 1 is a side view of an embodiment.
【図２】 実施例で用いたＬＥＤアレイ上の金バンプ
を示す平面図FIG. 2 is a plan view showing a gold bump on an LED array used in an example.
【図３】 実施例で用いたガラス基板上の錫バンプを
示す平面図FIG. 3 is a plan view showing tin bumps on a glass substrate used in Examples.
【図４】 実施例での熱圧着工程を示す側面図FIG. 4 is a side view showing a thermocompression bonding process in an example.
２ ガラス基板 ４ ＬＥＤアレイ ６ 発光体 １４ 電極 １６ 電極 １８ 金バンプ ２０ 錫バンプ ２２ コレット 2 glass substrate 4 LED array 6 light emitter 14 electrode 16 electrode 18 gold bump 20 tin bump 22 collet
Claims (1)
バンプとを接続した電子部品のフリップチップ接続構造
において、 一方のバンプを錫を主成分とするバンプとし、他方のバ
ンプを金もしくは銀を主成分とするバンプとしたことを
特徴とする、電子部品のフリップチップ接続構造。1. In a flip-chip connection structure of an electronic component in which a bump provided on an electronic component and a bump provided on a substrate are connected, one bump is a bump containing tin as a main component and the other bump is gold or silver. A flip-chip connection structure for electronic parts, characterized in that it is a bump whose main component is.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23732391A JP2888385B2 (en) | 1991-08-22 | 1991-08-22 | Flip-chip connection structure of light receiving / emitting element array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23732391A JP2888385B2 (en) | 1991-08-22 | 1991-08-22 | Flip-chip connection structure of light receiving / emitting element array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0555635A true JPH0555635A (en) | 1993-03-05 |
| JP2888385B2 JP2888385B2 (en) | 1999-05-10 |
Family
ID=17013672
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23732391A Expired - Fee Related JP2888385B2 (en) | 1991-08-22 | 1991-08-22 | Flip-chip connection structure of light receiving / emitting element array |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2888385B2 (en) |
Cited By (9)
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|---|---|---|---|---|
| JP2003298167A (en) * | 2002-03-29 | 2003-10-17 | Toshiba Corp | Optical semiconductor device |
| WO2004001863A1 (en) * | 2002-06-20 | 2003-12-31 | Rohm Co., Ltd. | Led chip mounting structure and image reader having same |
| US6764938B2 (en) | 1994-07-20 | 2004-07-20 | Fujitsu Limited | Integrated electronic device having flip-chip connection with circuit board and fabrication method thereof |
| JP2007035881A (en) * | 2005-07-26 | 2007-02-08 | Matsushita Electric Works Ltd | Mounting structure of surface-mounting electronic component and illumination instrument |
| US7854365B2 (en) * | 2008-10-27 | 2010-12-21 | Asm Assembly Automation Ltd | Direct die attach utilizing heated bond head |
| JP2013504187A (en) * | 2009-09-03 | 2013-02-04 | オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング | Optoelectronic device comprising a semiconductor body, an isolation layer, and a planar conductor structure, and a method of manufacturing the optoelectronic device |
| US8474810B2 (en) | 2011-06-28 | 2013-07-02 | Ricoh Company, Ltd. | Reflective photosensor and image forming device incorporating the same |
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1991
- 1991-08-22 JP JP23732391A patent/JP2888385B2/en not_active Expired - Fee Related
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|---|---|---|---|---|
| US6764938B2 (en) | 1994-07-20 | 2004-07-20 | Fujitsu Limited | Integrated electronic device having flip-chip connection with circuit board and fabrication method thereof |
| JP2003298167A (en) * | 2002-03-29 | 2003-10-17 | Toshiba Corp | Optical semiconductor device |
| WO2004001863A1 (en) * | 2002-06-20 | 2003-12-31 | Rohm Co., Ltd. | Led chip mounting structure and image reader having same |
| US7551329B2 (en) | 2002-06-20 | 2009-06-23 | Rohm Co., Ltd. | Led chip mounting structure and image reader having same |
| JP2007035881A (en) * | 2005-07-26 | 2007-02-08 | Matsushita Electric Works Ltd | Mounting structure of surface-mounting electronic component and illumination instrument |
| US7854365B2 (en) * | 2008-10-27 | 2010-12-21 | Asm Assembly Automation Ltd | Direct die attach utilizing heated bond head |
| JP2013504187A (en) * | 2009-09-03 | 2013-02-04 | オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング | Optoelectronic device comprising a semiconductor body, an isolation layer, and a planar conductor structure, and a method of manufacturing the optoelectronic device |
| US8474810B2 (en) | 2011-06-28 | 2013-07-02 | Ricoh Company, Ltd. | Reflective photosensor and image forming device incorporating the same |
| JP2013145838A (en) * | 2012-01-16 | 2013-07-25 | Kyocera Corp | Photoelectric conversion element mounting member and photoelectric conversion device |
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| JP2888385B2 (en) | 1999-05-10 |
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