JP2000260927A - Semiconductor element structure and semiconductor device - Google Patents
Semiconductor element structure and semiconductor deviceInfo
- Publication number
- JP2000260927A JP2000260927A JP11063368A JP6336899A JP2000260927A JP 2000260927 A JP2000260927 A JP 2000260927A JP 11063368 A JP11063368 A JP 11063368A JP 6336899 A JP6336899 A JP 6336899A JP 2000260927 A JP2000260927 A JP 2000260927A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- semiconductor device
- metal lead
- lead
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Led Device Packages (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子構造
体、およびこの半導体素子構造体が配線基板に搭載・実
装された半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device structure and a semiconductor device having the semiconductor device structure mounted and mounted on a wiring board.
【０００２】[0002]
【従来の技術】従来から半導体装置の分野では、小型化
および薄型化の要求に応じるために、半導体チップ（ベ
アチップ）のフリップチップ接続がなされている。フリ
ップチップ接続は、半導体チップを配線基板に対してフ
ェースダウンに（電極端子形成面を下向きにして）搭載
し、半導体チップの電極端子上に形成された金、はんだ
等の突起電極（以下、バンプという。）を、配線基板の
接続端子に押し付けて加熱し、必要に応じて、接続端子
上に形成されたはんだ層を溶融（はんだリフロー）させ
て接続する方法である。2. Description of the Related Art Conventionally, in the field of semiconductor devices, semiconductor chips (bare chips) have been flip-chip connected to meet demands for miniaturization and thinning. In flip-chip connection, a semiconductor chip is mounted face down on a wiring board (electrode terminal formation surface facing down), and bumps made of gold, solder or the like (hereinafter referred to as bumps) formed on the electrode terminals of the semiconductor chip. Is pressed against the connection terminal of the wiring board and heated, and if necessary, the solder layer formed on the connection terminal is melted (solder reflow) to connect.
【０００３】このようなフリップチップ接続がなされた
半導体装置では、シリコン等の半導体チップと配線基板
（例えば、エポキシ樹脂含浸ガラスクロス配線基板）と
の熱膨張率が大きく異なるため、熱膨張率の違いに起因
する熱応力が、半導体チップと配線基板とを接合するは
んだ等のバンプに加わり、接合部が劣化するという問題
がある。In such a flip-chip connected semiconductor device, since the coefficient of thermal expansion between a semiconductor chip such as silicon and a wiring board (for example, an epoxy resin impregnated glass cloth wiring board) is greatly different, the difference in the coefficient of thermal expansion is large. Is applied to a bump made of solder or the like that joins the semiconductor chip and the wiring board, thereby deteriorating the joint.
【０００４】したがって従来の半導体装置では、前記し
た熱応力を緩和するため、図６に示すように、半導体チ
ップ１１と配線基板１２との間の間隙部に、エポキシ樹
脂のような液状の樹脂を注入・充填し、アンダーフィル
と呼ばれる樹脂充填層１３を形成することが行なわれて
いる。なお、図中符号１４は、金、はんだ等のバンプを
示している。Therefore, in a conventional semiconductor device, a liquid resin such as an epoxy resin is filled in a gap between the semiconductor chip 11 and the wiring board 12 as shown in FIG. Injection and filling are performed to form a resin filling layer 13 called an underfill. Reference numeral 14 in the figure indicates a bump made of gold, solder, or the like.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、このよ
うな従来からの半導体装置においては、樹脂を充填する
ための専用装置を必要とするばかりでなく、樹脂を毛細
管現象を利用して充填するため、多大なプロセス時間を
要し、製造コストが高くなるという問題があった。However, such a conventional semiconductor device not only requires a dedicated device for filling the resin, but also fills the resin by utilizing a capillary phenomenon. There has been a problem that a great deal of processing time is required and the manufacturing cost is high.
【０００６】本発明は、このような問題を解決するため
になされたもので、配線基板との信頼性の高い接続が可
能であり、低コスト化を実現することができる半導体素
子構造体、およびそのような半導体素子構造体が配線基
板に実装された半導体装置を提供することを目的とす
る。The present invention has been made in order to solve such a problem, and a semiconductor element structure capable of being connected to a wiring board with high reliability and realizing low cost is provided. It is an object of the present invention to provide a semiconductor device in which such a semiconductor element structure is mounted on a wiring board.
【０００７】[0007]
【課題を解決するための手段】本発明の半導体素子構造
体は、半導体素子と、第１の端部と第２の端部とを有
し、前記第１の端部が前記半導体素子の電極端子に接合
された金属リードとを備え、前記金属リードが、前記半
導体素子の電極端子形成面と反対側に凸形状となる屈曲
部を有することを特徴とする。A semiconductor device structure according to the present invention has a semiconductor device, a first end and a second end, and the first end is an electrode of the semiconductor device. And a metal lead bonded to the terminal, wherein the metal lead has a bent portion having a convex shape on the side opposite to the electrode terminal forming surface of the semiconductor element.
【０００８】本発明において、金属リードとしては、
銅、銅系合金、42アロイのようなニッケル系合金、金等
のリードが挙げられ、特に銅リードまたは金リードの使
用が望ましい。リードを形成するには、例えば、ＴＡＢ
（Tape Automated Bonding）方式でのフィルムキャリア
テープ（ＴＡＢテープ）と同様の製造方法を用いて、こ
れらの金属から構成される箔を所定のパターンにフォト
エッチングする方法が採られる。[0008] In the present invention, as the metal lead,
Leads such as copper, copper-based alloys, nickel-based alloys such as 42 alloys, and gold are cited, and use of copper leads or gold leads is particularly desirable. To form a lead, for example, TAB
A method of photoetching a foil made of these metals into a predetermined pattern using the same manufacturing method as a film carrier tape (TAB tape) in a (Tape Automated Bonding) system is adopted.
【０００９】このような金属リードの第１の端部は、半
導体素子の電極端子に、加熱・加圧により接合されてい
る。ここで、接合強度を高めるために、銅リードの端部
（表面）に、錫（Ｓｎ）層、錫−銀（Ｓｎ−Ａｇ）層、
ニッケル／金（Ｎｉ／Ａｕ）層、あるいはニッケル／バ
ナジウム（Ｎｉ／Ｐｄ）層を、メッキ等により被覆して
おくことができる。金リードにおいては、このような被
覆は特に必要とされない。また、半導体素子の電極端子
と銅リードとの接合は、電極端子上に形成された金バン
プを介して行なうが、金リードとの接合の場合は、必ず
しも金バンプを介して行なわなくても良い。A first end of such a metal lead is joined to an electrode terminal of a semiconductor element by heating and pressing. Here, in order to increase the bonding strength, a tin (Sn) layer, a tin-silver (Sn-Ag) layer,
A nickel / gold (Ni / Au) layer or a nickel / vanadium (Ni / Pd) layer can be covered by plating or the like. Such a coating is not particularly required for gold leads. In addition, the bonding between the electrode terminal of the semiconductor element and the copper lead is performed via the gold bump formed on the electrode terminal, but the bonding with the gold lead is not necessarily performed via the gold bump. .
【００１０】また、本発明においては、このように半導
体素子の電極端子に接合された金属リードの第２の端部
を、電極端子との接合部である第１の端部、または半導
体素子面上に、直接あるいは絶縁樹脂フィルムを介して
当接させ、接着剤等により接着することができる。ここ
で、絶縁樹脂フィルムとしては、例えば、前記したＴＡ
Ｂテープとして使用されているポリイミド樹脂等のフィ
ルムを使用することができる。このように、金属リード
の第２の端部を第１の端部に接着した構造では、金属リ
ードの屈曲部の整形が容易であり、かつ屈曲部の形状が
安定して保持されるという利点がある。Further, in the present invention, the second end of the metal lead thus joined to the electrode terminal of the semiconductor element is connected to the first end which is the joint with the electrode terminal, or the surface of the semiconductor element. It can be contacted directly or via an insulating resin film and adhered with an adhesive or the like. Here, as the insulating resin film, for example, the above-described TA
A film such as a polyimide resin used as the B tape can be used. As described above, in the structure in which the second end of the metal lead is bonded to the first end, it is easy to shape the bent portion of the metal lead, and the shape of the bent portion is stably held. There is.
【００１１】さらに、本発明の半導体素子構造体は、リ
ードを屈曲させる前までは、従来のＴＡＢテープと全く
同様のプロセスで製造可能であり、屈曲前のＴＡＢテー
プの状態で容易にバーンインテストを実施することが可
能である。したがって、低コストで信頼性が高く、かつ
高密度実装が可能な半導体素子構造体を得ることができ
る。Further, the semiconductor element structure of the present invention can be manufactured by the same process as that of the conventional TAB tape before bending the lead, and the burn-in test can be easily performed in the state of the TAB tape before bending. It is possible to implement. Therefore, it is possible to obtain a semiconductor element structure that is low in cost, highly reliable, and capable of high-density mounting.
【００１２】また、金属リードの屈曲部の曲率半径は、
リードの厚さの 2倍以上の大きさとすることが望まし
い。屈曲部の曲率半径がリードの厚さの 2倍未満では、
屈曲部の整形が難しいばかりでなく、屈曲部が、半導体
チップと配線基板との間の熱膨脹係数の違いに起因する
熱応力を、十分に吸収・緩和することが難しい。The radius of curvature of the bent portion of the metal lead is
It is desirable that the thickness be at least twice the thickness of the lead. If the radius of curvature of the bend is less than twice the lead thickness,
Not only is it difficult to shape the bent portion, but also it is difficult for the bent portion to sufficiently absorb and reduce the thermal stress caused by the difference in the coefficient of thermal expansion between the semiconductor chip and the wiring board.
【００１３】さらに本発明においては、半導体素子の電
極端子形成面に、エポキシ樹脂等からなる被覆層を設
け、この樹脂被覆層により、半導体素子の電極端子形成
面および電極端子と金属リードとの接合部を封止するこ
とができる。Further, in the present invention, a coating layer made of epoxy resin or the like is provided on the electrode terminal forming surface of the semiconductor element, and the resin coating layer is used to bond the electrode terminal forming surface of the semiconductor element and the electrode terminal to the metal lead. The part can be sealed.
【００１４】そして、このような半導体素子構造体を配
線基板上に搭載し、金属リードの屈曲部を配線基板の接
続端子に接合することにより、接合部の熱劣化が少な
く、信頼性の高い半導体装置が得られる。By mounting such a semiconductor element structure on a wiring board and joining the bent portion of the metal lead to the connection terminal of the wiring board, a highly reliable semiconductor with less thermal deterioration of the joined portion is provided. A device is obtained.
【００１５】すなわち、本発明の半導体装置は、前記し
た半導体素子構造体と、絶縁基板の少なくとも一主面に
配線層および接続端子が配設された配線基板とを備え、
前記配線基板の接続端子形成面に前記半導体素子構造体
が搭載され、前記金属リードの屈曲部が前記配線基板の
接続端子に接合されていることを特徴とする。金属リー
ドの屈曲部と配線基板の接続端子との接合は、はんだ層
を介して行なうことが望ましい。That is, a semiconductor device of the present invention includes the above-described semiconductor element structure, and a wiring board having a wiring layer and connection terminals disposed on at least one main surface of an insulating substrate,
The semiconductor element structure is mounted on a connection terminal forming surface of the wiring board, and a bent portion of the metal lead is joined to a connection terminal of the wiring board. It is desirable that the connection between the bent portion of the metal lead and the connection terminal of the wiring board be performed via a solder layer.
【００１６】本発明の半導体素子構造体および半導体装
置においては、一端が半導体素子の電極端子に接合され
た金属リードが、半導体素子の電極端子形成面と反対側
に凸形状となる屈曲部を有しており、この屈曲部が配線
基板の接続端子に接合されるので、このように屈曲成形
された金属リードから成る接合部によって、半導体素子
と配線基板との間の熱膨脹係数の違いに起因する熱応力
を、十分に緩和することができる。そして、熱応力が繰
り返し負荷されても、前記接合部には疲労・劣化が生じ
にくいので、長期に亘って信頼性の高い接続が達成され
る。In the semiconductor element structure and the semiconductor device according to the present invention, the metal lead having one end joined to the electrode terminal of the semiconductor element has a bent portion having a convex shape on the side opposite to the electrode terminal forming surface of the semiconductor element. Since the bent portion is bonded to the connection terminal of the wiring board, the bonding portion formed of the bent metal lead is caused by a difference in thermal expansion coefficient between the semiconductor element and the wiring board. Thermal stress can be sufficiently reduced. Then, even if thermal stress is repeatedly applied, fatigue and deterioration do not easily occur in the joint portion, so that a highly reliable connection can be achieved for a long period of time.
【００１７】また、半導体素子構造体が配線基板にはん
だ層を介して接合された半導体装置では、金属リードの
屈曲部へのはんだ層の這い上がりが生じ、この這い上が
りの結果生じたはんだフィレットにより、配線基板の反
りが吸収・緩和されるので、高い実装歩留りが得られ
る。In a semiconductor device in which a semiconductor element structure is joined to a wiring board via a solder layer, the solder layer creeps up to the bent portion of the metal lead, and the solder fillet generated as a result of the creep up occurs. Since the warpage of the wiring board is absorbed and reduced, a high mounting yield can be obtained.
【００１８】さらに、本発明における半導体素子構造体
の接続・実装は、従来からの表面実装部品と同様に行な
うことができ、作業が容易であるうえに、実装後に半導
体素子と配線基板との間隙部に樹脂を注入・充填するな
どの方法で、アンダーフィルを形成する必要がない。し
たがって、低コスト化が可能であるうえに、半導体素子
構造体の実装後のリペアが容易である。Furthermore, the connection and mounting of the semiconductor element structure according to the present invention can be performed in the same manner as a conventional surface mount component, so that the operation is easy and the gap between the semiconductor element and the wiring board after mounting is reduced. There is no need to form an underfill by a method such as injecting and filling a resin into the portion. Therefore, the cost can be reduced, and the repair after mounting the semiconductor element structure is easy.
【００１９】[0019]
【発明の実施の形態】以下、本発明の実施例を図面に基
づいて説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００２０】図１は、本発明の半導体素子構造体の第１
の実施例を概略的に示す断面図である。この図におい
て、符号１は半導体チップを示し、この半導体チップ１
の各電極端子（図示を省略。）に、銅リード２の一端
が、金バンプ３を介して接合されている。そして、この
銅リード２の他端部は、半導体チップ１の電極端子に接
合された前記端部に、接着剤４により接着されており、
中間部に、半導体チップ１の電極端子形成面と反対側に
凸形状となる屈曲部２ａが形成されている。また、半導
体チップ１の電極端子形成面には、エポキシ樹脂等から
なる被覆層５が形成され、この樹脂被覆層５により、半
導体チップ１の電極端子と銅リード２との接合部が封止
されている。FIG. 1 shows a first example of a semiconductor device structure according to the present invention.
FIG. 3 is a cross-sectional view schematically showing the embodiment of FIG. In this figure, reference numeral 1 denotes a semiconductor chip.
One end of a copper lead 2 is joined to each of the electrode terminals (not shown) via a gold bump 3. The other end of the copper lead 2 is bonded to the end joined to the electrode terminal of the semiconductor chip 1 with an adhesive 4.
In an intermediate portion, a bent portion 2a having a convex shape is formed on the side opposite to the electrode terminal forming surface of the semiconductor chip 1. A coating layer 5 made of epoxy resin or the like is formed on the electrode terminal forming surface of the semiconductor chip 1, and the resin coating layer 5 seals a joint between the electrode terminal of the semiconductor chip 1 and the copper lead 2. ing.
【００２１】次に、本発明の半導体素子構造体の別の実
施例について説明する。Next, another embodiment of the semiconductor device structure of the present invention will be described.
【００２２】図２は、本発明の半導体素子構造体の第２
の実施例を概略的に示す断面図であり、図３はその要部
を拡大して示したものである。FIG. 2 shows a second example of the semiconductor device structure of the present invention.
FIG. 3 is a cross-sectional view schematically showing the embodiment, and FIG. 3 is an enlarged view of a main part thereof.
【００２３】第２の実施例では、図２および図３にそれ
ぞれ示すように、一端が半導体チップ１の電極端子に接
合された銅リード２の他端部が、電極端子との接合側の
端部にポリイミド樹脂フィルム６を介して当接され、こ
のフィルム６と銅リード２の両端部とが、例えば接着剤
４により接着されている。そして、銅リード２の中間部
には、半導体チップ１の電極端子形成面と反対側に凸形
状となる屈曲部２ａが形成されている。また、半導体チ
ップ１の電極端子形成面には、エポキシ樹脂等からなる
被覆層５が形成され、この樹脂被覆層５により、半導体
チップ１の電極端子と銅リード２との接合部が封止され
ている。In the second embodiment, as shown in FIGS. 2 and 3, the other end of the copper lead 2 having one end joined to the electrode terminal of the semiconductor chip 1 is connected to the end on the joining side with the electrode terminal. This portion is in contact with a polyimide resin film 6 via a polyimide resin film 6, and the film 6 and both end portions of the copper lead 2 are bonded by, for example, an adhesive 4. In the middle part of the copper lead 2, there is formed a bent part 2a having a convex shape on the side opposite to the electrode terminal forming surface of the semiconductor chip 1. A coating layer 5 made of epoxy resin or the like is formed on the electrode terminal forming surface of the semiconductor chip 1, and the resin coating layer 5 seals a joint between the electrode terminal of the semiconductor chip 1 and the copper lead 2. ing.
【００２４】第２の実施例の半導体素子構造体は、以下
に示すように、例えばＴＡＢテープを使用して、簡略化
された工程で製造することができる。すなわち、図４に
示すように、中央部にホール（デバイスホール）７ａを
有し、このホールに突出するように形成された複数本の
銅リード２を有するポリイミド樹脂配線フィルム７を使
用し、このような配線フィルム７のデバイスホール７ａ
内に、半導体チップ１をフェースダウンに配置し、銅リ
ード２の先端部を半導体チップ１の電極端子に加熱・加
圧接合した後、矢印で示すように、銅リード２のフィル
ム側端部をポリイミド樹脂フィルム６ごと切断・折り曲
げ、ポリイミド樹脂フィルム６のリード形成面と反対側
の面を、銅リード２の電極端子との接合側端部に接着剤
４等により接着する。しかる後、半導体チップ１の電極
端子形成面に、エポキシ樹脂等の被覆層５をポッティン
グ等により形成する。The semiconductor device structure of the second embodiment can be manufactured by a simplified process using, for example, a TAB tape as shown below. That is, as shown in FIG. 4, a polyimide resin wiring film 7 having a hole (device hole) 7a at the center and having a plurality of copper leads 2 formed so as to protrude into the hole is used. Hole 7a of such wiring film 7
After the semiconductor chip 1 is placed face down and the tip of the copper lead 2 is heated and pressed to the electrode terminal of the semiconductor chip 1, the film-side end of the copper lead 2 is connected as shown by the arrow. The polyimide resin film 6 is cut and bent together, and the surface of the polyimide resin film 6 opposite to the lead forming surface is bonded to the end of the copper lead 2 on the joining side with the electrode terminal with an adhesive 4 or the like. Thereafter, a coating layer 5 such as an epoxy resin is formed on the electrode terminal forming surface of the semiconductor chip 1 by potting or the like.
【００２５】次に、本発明の半導体装置の実施例につい
て説明する。Next, an embodiment of the semiconductor device of the present invention will be described.
【００２６】図５に示す半導体装置は、第２の実施例の
半導体素子構造を配線基板に搭載・実装した構造を有し
ている。The semiconductor device shown in FIG. 5 has a structure in which the semiconductor element structure of the second embodiment is mounted and mounted on a wiring board.
【００２７】図において、符号８は、エポキシ樹脂含浸
ガラスクロス基板のような絶縁基板を示し、この絶縁基
板８の少なくとも一方の主面に、銅の蒸着・パターニン
グや銅箔のフォトエッチング等の方法で、接続パッド９
および配線層（図示を省略。）が形成されている。そし
て、このような配線基板の接続パッド９形成面上に、第
２の実施例の半導体素子構造体が、銅リード２の屈曲部
２ａを下に向けて搭載され、屈曲部２ａが接続パッド９
にはんだ層１０を介して接合されている。In the figure, reference numeral 8 denotes an insulating substrate such as an epoxy resin impregnated glass cloth substrate. At least one principal surface of the insulating substrate 8 is formed by a method such as vapor deposition and patterning of copper and photo etching of copper foil. And connection pad 9
And a wiring layer (not shown) are formed. The semiconductor element structure of the second embodiment is mounted on the connection pad 9 forming surface of such a wiring board with the bent portion 2a of the copper lead 2 facing downward, and the bent portion 2a is
Through a solder layer 10.
【００２８】このように構成される半導体装置において
は、半導体チップ１の電極端子に接合された銅リード２
が、半導体チップ１の電極端子形成面と反対側に凸形状
となる屈曲部２ａを有しており、この屈曲部２ａが配線
基板の接続パッド９にはんだ層１０を介して接合されて
いるので、このような銅リード２の接合部により、半導
体チップ１と配線基板との熱膨脹係数の違いに起因する
熱応力を、良好に緩和することができる。そして、この
ような接合部には、熱応力が繰り返し負荷されても疲労
・劣化が生じにくいので、長期に亘って信頼性の高い接
続が得られる。In the semiconductor device thus constructed, the copper lead 2 joined to the electrode terminal of the semiconductor chip 1
Has a bent portion 2a having a convex shape on the side opposite to the electrode terminal forming surface of the semiconductor chip 1, and the bent portion 2a is joined to the connection pad 9 of the wiring board via the solder layer 10. With such a joint portion of the copper lead 2, thermal stress caused by a difference in thermal expansion coefficient between the semiconductor chip 1 and the wiring board can be favorably reduced. Further, since fatigue and deterioration hardly occur in such a joint portion even when thermal stress is repeatedly applied, a highly reliable connection can be obtained for a long period of time.
【００２９】また、銅リード２と配線基板の接続パッド
９とを接合するはんだ層１０において、屈曲部２ａへの
はんだの這い上がりにより、フィレット状のはんだ層１
０が形成されるので、配線基板の反りが吸収・緩和さ
れ、高い実装歩留りが得られる。Further, in the solder layer 10 for joining the copper lead 2 and the connection pad 9 of the wiring board, the fillet-shaped solder layer 1
Since 0 is formed, the warpage of the wiring board is absorbed and reduced, and a high mounting yield can be obtained.
【００３０】さらに、半導体素子構造体の搭載・実装
を、従来からの表面実装部品と同様に行なうことがで
き、実装作業が容易であるうえに、実装後に半導体チッ
プと配線基板との間隙部に樹脂を注入・充填するなどの
方法で、アンダーフィルを形成する必要がなく、低コス
トで高密度実装が可能である。また、実装後のリペアも
容易である。Further, the mounting and mounting of the semiconductor element structure can be carried out in the same manner as a conventional surface mount component, so that the mounting operation is easy, and after mounting, the semiconductor element structure is mounted in the gap between the semiconductor chip and the wiring board. There is no need to form an underfill by a method such as resin injection or filling, and high-density mounting is possible at low cost. Repair after mounting is also easy.
【００３１】[0031]
【発明の効果】以上の説明から明らかなように、本発明
の半導体素子構造体によれば、配線基板との信頼性の高
い接続が可能であり、低コスト化を実現することができ
る。また、そのような半導体素子構造体が配線基板に実
装された半導体装置によれば、周期的な熱負荷等に起因
する接合部の疲労・劣化が生じず、長期に亘って信頼性
の高い接続が達成される。As is apparent from the above description, according to the semiconductor element structure of the present invention, highly reliable connection with the wiring board is possible, and cost reduction can be realized. Further, according to the semiconductor device in which such a semiconductor element structure is mounted on a wiring board, fatigue and deterioration of a joint caused by a periodic thermal load or the like do not occur, and a highly reliable connection for a long period of time. Is achieved.
【図１】本発明の半導体素子構造体の第１の実施例を概
略的に示す断面図。FIG. 1 is a sectional view schematically showing a first embodiment of a semiconductor element structure of the present invention.
【図２】本発明の半導体素子構造体の第２の実施例を概
略的に示す断面図。FIG. 2 is a sectional view schematically showing a second embodiment of the semiconductor device structure of the present invention.
【図３】第２の実施例の要部を拡大して示す断面図。FIG. 3 is an enlarged sectional view showing a main part of a second embodiment.
【図４】第２の実施例の半導体素子構造体の製造方法を
説明するための図。FIG. 4 is a view for explaining a method for manufacturing the semiconductor element structure according to the second embodiment.
【図５】本発明の半導体装置の実施例を概略的に示す断
面図。FIG. 5 is a sectional view schematically showing an embodiment of the semiconductor device of the present invention.
【図６】従来の半導体装置の一例を示す断面図。FIG. 6 is a cross-sectional view illustrating an example of a conventional semiconductor device.
１………半導体チップ ２………銅リード ２ａ………屈曲部 ３………金バンプ ５………樹脂被覆層 ６………ポリイミド樹脂フィルム ８………絶縁基板 ９………接続パッド １０………はんだ層 DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip 2 ... Copper lead 2a ... Bending part 3 ... Gold bump 5 ... Resin coating layer 6 ... Polyimide resin film 8 ... Insulating substrate 9 ... Connection pad 10 solder layer
Claims (12)
とを有し、前記第１の端部が前記半導体素子の電極端子
に接合された金属リードとを備え、前記金属リードが、
前記半導体素子の電極端子形成面と反対側に凸形状とな
る屈曲部を有することを特徴とする半導体素子構造体。1. A semiconductor device comprising: a semiconductor element; and a metal lead having a first end and a second end, wherein the first end is joined to an electrode terminal of the semiconductor element. The lead
A semiconductor element structure having a bent portion having a convex shape on a side opposite to an electrode terminal forming surface of the semiconductor element.
を特徴とする請求項１記載の半導体素子構造体。2. The semiconductor device structure according to claim 1, wherein said metal lead is a copper lead.
ッケル／金、ニッケル／バナジウムにより被覆されてい
ることを特徴とする請求項２記載の半導体素子構造体。3. The semiconductor device structure according to claim 2, wherein said metal lead surface is covered with tin, tin-silver, nickel / gold, nickel / vanadium.
を特徴とする請求項１記載の半導体素子構造体。4. The semiconductor device structure according to claim 1, wherein said metal lead is a gold lead.
導体素子の電極端子に接合された第１の端部に接着され
ていることを特徴とする請求項１または２記載の半導体
素子構造体。5. The semiconductor device according to claim 1, wherein a second end of the metal lead is adhered to a first end joined to an electrode terminal of the semiconductor device. Structure.
導体素子面上に接着されていることを特徴とする請求項
５記載の半導体素子構造体。6. The semiconductor device structure according to claim 5, wherein a second end of said metal lead is adhered on said semiconductor device surface.
１の端部に絶縁樹脂フィルムを介して接着されているこ
とを特徴とする請求項５記載の半導体素子構造体。7. The semiconductor element structure according to claim 5, wherein a second end of the metal lead is bonded to the first end via an insulating resin film.
導体素子面上に絶縁樹脂フィルムを介して接着されてい
ることを特徴とする請求項５記載の半導体素子構造体。8. The semiconductor element structure according to claim 5, wherein a second end of said metal lead is bonded to said semiconductor element surface via an insulating resin film.
厚さの 2倍以上の曲率半径を有することを特徴とする請
求項１乃至８のいずれか１項記載の半導体素子構造体。9. The semiconductor device structure according to claim 1, wherein the bent portion of the metal lead has a radius of curvature that is at least twice the thickness of the lead.
樹脂層により被覆・封止されていることを特徴とする請
求項１乃至９のいずれか１項記載の半導体素子構造体。10. An electrode terminal forming surface of the semiconductor element,
The semiconductor element structure according to any one of claims 1 to 9, wherein the semiconductor element structure is covered and sealed with a resin layer.
の半導体素子構造体と、絶縁基板の少なくとも一主面に
配線層および接続端子が配設された配線基板とを備え、 前記配線基板の接続端子形成面に前記半導体素子構造体
が搭載され、前記金属リードの屈曲部が前記配線基板の
接続端子に接合されていることを特徴とする半導体装
置。11. A wiring board comprising: the semiconductor element structure according to claim 1; and a wiring board having a wiring layer and connection terminals provided on at least one main surface of an insulating substrate. Wherein the semiconductor element structure is mounted on the connection terminal forming surface, and the bent portion of the metal lead is joined to the connection terminal of the wiring board.
ドの屈曲部が、前記配線基板の接続端子に、はんだ層を
介して接合されていることを特徴とする請求項１１記載
の半導体装置。12. The semiconductor device according to claim 11, wherein a bent portion of said metal lead of said semiconductor element structure is joined to a connection terminal of said wiring board via a solder layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11063368A JP2000260927A (en) | 1999-03-10 | 1999-03-10 | Semiconductor element structure and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11063368A JP2000260927A (en) | 1999-03-10 | 1999-03-10 | Semiconductor element structure and semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000260927A true JP2000260927A (en) | 2000-09-22 |
Family
ID=13227280
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11063368A Withdrawn JP2000260927A (en) | 1999-03-10 | 1999-03-10 | Semiconductor element structure and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000260927A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003209213A (en) * | 2002-01-17 | 2003-07-25 | Fuji Electric Co Ltd | Method for manufacturing lead frame and semiconductor device |
| JP2007294847A (en) * | 2006-03-27 | 2007-11-08 | Matsushita Electric Works Ltd | Surface-mounting light emitting device |
-
1999
- 1999-03-10 JP JP11063368A patent/JP2000260927A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003209213A (en) * | 2002-01-17 | 2003-07-25 | Fuji Electric Co Ltd | Method for manufacturing lead frame and semiconductor device |
| JP2007294847A (en) * | 2006-03-27 | 2007-11-08 | Matsushita Electric Works Ltd | Surface-mounting light emitting device |
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