JPS6153851B2 - - Google Patents

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Publication number
JPS6153851B2
JPS6153851B2 JP54013354A JP1335479A JPS6153851B2 JP S6153851 B2 JPS6153851 B2 JP S6153851B2 JP 54013354 A JP54013354 A JP 54013354A JP 1335479 A JP1335479 A JP 1335479A JP S6153851 B2 JPS6153851 B2 JP S6153851B2
Authority
JP
Japan
Prior art keywords
film
bonding
frame
semiconductor
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54013354A
Other languages
Japanese (ja)
Other versions
JPS55107238A (en
Inventor
Hiroshi Kato
Masamichi Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1335479A priority Critical patent/JPS55107238A/en
Publication of JPS55107238A publication Critical patent/JPS55107238A/en
Publication of JPS6153851B2 publication Critical patent/JPS6153851B2/ja
Granted legal-status Critical Current

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    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
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    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Die Bonding (AREA)

Description

【発明の詳細な説明】 この発明は半導体装置の製造法、特に比較的大
型の半導体チツプの銅基板への接合技術に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a technique for bonding a relatively large semiconductor chip to a copper substrate.

トランジスタ、IC、LSI等の製造の際に、第１
図ａを参照しシリコン（Si）半導体チツプ１とリ
ードフレーム２またはステム等の銅（Cu）部材
との接合を行なう手段として従来より(1)これらの
間に金・シリコン（Au−Si）共晶ろうを介挿す
るか、又はシリコン面に予めAu、Si共晶層３を
形成し、一方Cuフレーム又はステムのCu面にAu
又は銀（Ag）膜４を形成しておき、これらを370
℃〜450℃程度の高温において接触させてAu−
Si、Ag−Siろう接合５を実現していた。又(2)他
の接合手段としてシリコンチツプ側にチタン・ニ
ツケル・金（Ti−Ni−Au）もしくはチタン・ニ
ツケル・銀（Ti−Ni−Ag）層を形成する一方、
フレーム側にAgめつき層もしくはAuめつき層を
形成し、これらの間に鉛・すず（Pb−Sn）系は
んだ層を介挿してろう接合していた。 When manufacturing transistors, ICs, LSIs, etc.,
Referring to Figure a, as a conventional means for bonding a silicon (Si) semiconductor chip 1 and a copper (Cu) member such as a lead frame 2 or a stem, (1) gold-silicon (Au-Si) is also used between them. Either a crystal solder is inserted or an Au and Si eutectic layer 3 is formed on the silicon surface in advance, while an Au and Si eutectic layer 3 is formed on the Cu frame or stem.
Alternatively, a silver (Ag) film 4 is formed and these are
Au-
Si, Ag-Si brazing joints5 were realized. (2) As another bonding method, a titanium-nickel-gold (Ti-Ni-Au) or titanium-nickel-silver (Ti-Ni-Ag) layer is formed on the silicon chip side;
An Ag plating layer or an Au plating layer was formed on the frame side, and a lead-tin (Pb-Sn) solder layer was inserted between these layers for soldering.

上記(1)の方法によれば接合温度が高いことで
Au−Siろう材の固化の際に生じるSiチツプの残
留応力が大きく、又Au−Siろう中にAuが溶解す
ると固着温度が高くなり残留応力が大層大きくな
り、特に３mm角以上のSiチツプをCu製のフレー
ムやステムに接合するときチツプの割れや素子の
ピエゾ抵抗効果による特性変化があつた。又上記
(2)の方法においてもPb−Snはんだ層の残留応力
が大きくはんだがパワーサイクルによつて疲労破
壊しやすいという欠点があつた。 According to method (1) above, the high bonding temperature
The residual stress in the Si chip that occurs when the Au-Si filler metal solidifies is large, and when Au dissolves in the Au-Si filler material, the fixation temperature increases and the residual stress increases significantly. When bonded to a Cu frame or stem, there were cracks in the chip and changes in characteristics due to the piezoresistance effect of the element. Also above
Method (2) also had the disadvantage that the residual stress in the Pb-Sn solder layer was large and the solder was susceptible to fatigue failure due to power cycling.

本発明は上記した従来技術の欠点を解消するべ
く成されたものであり、その目的はSiチツプと
Cu部材との接合を比較的低い温度で実現し、残
留熱応力を小さくし、Siチツプの割れや接合部の
疲労による破壊を防止し、高信頼性の半導体装置
を提供することにある。 The present invention has been made to solve the above-mentioned drawbacks of the prior art, and its purpose is to
The purpose is to provide a highly reliable semiconductor device by realizing bonding with Cu components at a relatively low temperature, reducing residual thermal stress, and preventing cracking of Si chips and failure due to fatigue of the bonded parts.

上記目的を達成するための本発明の具体的構成
は、銅基板上にSi半導体チツプを接合するにあた
つて、半導体チツプ表面にTi−Ni−Cuの積層膜
を形成する一方、Cu基板上にSn膜を形成してこ
の、Snと上記積層膜のCuとを比較的低い温度例
えば220〜320℃で接触融着させ、その後このSn
−Sn融着温度よりさらに低い200℃程度でシンタ
処理することからなるものである。 A specific configuration of the present invention for achieving the above object is that when bonding a Si semiconductor chip onto a copper substrate, a Ti-Ni-Cu laminated film is formed on the surface of the semiconductor chip, while a stacked film of Ti-Ni-Cu is formed on the surface of the semiconductor chip. A Sn film is formed on the film, and this Sn and the Cu of the laminated film are contacted and fused at a relatively low temperature, e.g. 220 to 320°C, and then this Sn film is
-It consists of sintering at a temperature of about 200°C, which is lower than the Sn fusion temperature.

第２図は本発明によるパワートランジスタ用Si
半導体チツプ１をCuフレーム２上に接合する一
実施形態を示す。予めSi半導体の76mm径のウエハ
段階で素子を形成し、そのコレクタ側主面にSiと
接着性のよいチタン（Ti）膜６を0.1〜0.15μ
ｍ、バリアメタルとしてニツケル（Ni）膜７を
0.3〜0.5μｍ、その上に銅（Cu）膜８を0.5〜0.8
μｍそれぞれ蒸着により形成する。一方、Cuフ
レーム２上にはすず（Su）膜９をソルダーによ
り３〜６μｍの厚さに形成する。次に上記Si半導
体ウエハをスライシングして５mm角のチツプと
し、第２図に示すようにCuフレーム上にチツプ
を載置し、220℃〜320℃の不活性ガス（N2＋
H2）炉中でCu−Sn接合をつくるため両者間を融
着する。この後、200℃の不活性ガス（N2＋H2）
炉中で約60分シンタ処理し、第３図に示すような
SiとCuフレームの間に接合部に青銅合金層１０
を存在させた半導体装置を得る。 Figure 2 shows Si for power transistors according to the present invention.
An embodiment in which a semiconductor chip 1 is bonded onto a Cu frame 2 is shown. A device is formed in advance on a 76 mm diameter Si semiconductor wafer, and a titanium (Ti) film 6 with good adhesion to Si is coated with 0.1 to 0.15 μm on the main surface on the collector side.
m, nickel (Ni) film 7 as barrier metal
0.3~0.5μm, copper (Cu) film 8 on top of it 0.5~0.8μm
Each micrometer is formed by vapor deposition. On the other hand, a tin (Su) film 9 with a thickness of 3 to 6 μm is formed on the Cu frame 2 by soldering. Next, the Si semiconductor wafer was sliced into 5 mm square chips, and the chips were placed on a Cu frame as shown in Figure 2, and heated with an inert gas (N 2 +
H 2 ) The two are fused together in a furnace to create a Cu-Sn bond. After this, inert gas (N 2 + H 2 ) at 200℃
After sintering in the furnace for about 60 minutes, it becomes as shown in Figure 3.
Bronze alloy layer 10 at the joint between Si and Cu frame
A semiconductor device is obtained in which .

上記実施例で説明した本発明によれば下記の効
果がもたらされる。 According to the present invention explained in the above embodiments, the following effects are brought about.

(1) 接合部の主体がCu−Snであるため接合温度
を従来のAu−Snの場合450℃から250℃程度に
低くすることができ、残留応力を250/370即ち
75％程度に低減できる。又従来のPb−Sn系半
田接合（融着温度320℃）の場合に比しても残
留応力は250/320）78％程度に低減できる。こ
のためパワーサイクルに対する累積不良率は第
４図に示すように著しく改善され寿命も延長さ
れた。(1) Since the main body of the bond is Cu-Sn, the bonding temperature can be lowered from 450℃ for conventional Au-Sn to about 250℃, and the residual stress can be reduced to 250/370, i.e.
It can be reduced to about 75%. Furthermore, the residual stress can be reduced to about 250/320) 78% compared to conventional Pb-Sn solder joints (fusion temperature 320°C). As a result, the cumulative failure rate with respect to power cycles was significantly improved as shown in FIG. 4, and the life span was extended.

(2) 200℃でシンタ処理することにより、Cu−Sn
接合部が青銅合金化し、融点が接合温度250℃
よりも200〜300℃高くなることから配線側のネ
イルヘツド金線ボンデイングが可能となつた。(2) By sintering at 200℃, Cu−Sn
The joint part is made of bronze alloy, and the melting point is 250℃
Since the temperature is 200 to 300 degrees Celsius higher than the current temperature, nail head gold wire bonding on the wiring side has become possible.

(3) 残留応力を低減させることで３mm角以上の大
型のシリコンチツプをCu製のフレーム又はス
テムに接合することが可能となつた。従来は大
型チツプの場合、熱整合を考慮してヤング率が
大きく熱膨張率がシリコンのそれに近いモリブ
デン（Mo）板を緩衝材として使用していたが
Moは高価でありコスト高になつた。本発明に
よれば大型チツプの場合でもMo板の挿入の必
要がなく、CuフレームへSnめつきした上にチ
ツプを接合するため低コストであり、さらにレ
ジン化することにより全体のコスト低減が実現
できる。(3) By reducing residual stress, it has become possible to bond large silicon chips of 3 mm square or more to Cu frames or stems. Conventionally, in the case of large chips, molybdenum (Mo) plates, which have a large Young's modulus and a coefficient of thermal expansion close to that of silicon, were used as a buffer material in consideration of thermal matching.
Mo is expensive and costs have increased. According to the present invention, there is no need to insert a Mo plate even in the case of large chips, and the cost is low because the chip is bonded to the Cu frame with Sn plating, and the overall cost is reduced by using resin. can.

(4) ５mm角以上の大型チツプのアルミニウム
（Al）配線品をCuフレーム（ステム）に固着
し、低温ボンデイングが可能であり、高信頼化
できる。(4) A large-chip aluminum (Al) wiring product with a size of 5 mm square or more is fixed to a Cu frame (stem), enabling low-temperature bonding and achieving high reliability.

(5) Cu−Sn接合を連続ペレツト付け方式に採用
した場合、従来のNi−はんだ品に使用するよ
うなベルトコンベア大型炉が不要である。(5) When a continuous pellet attachment method is adopted for Cu-Sn bonding, there is no need for a large furnace with a belt conveyor, which is used for conventional Ni-solder products.

本発明は前記実施例に限定されず、これ以外に
多くの変形例、応用例を有する。 The present invention is not limited to the embodiments described above, and has many other variations and applications.

(1) Siとの接合性の良い金属としてTiの代りに
Cr、Ta、Ｖ、Zr等を使用することができる。(1) Substitute for Ti as a metal with good bonding properties with Si
Cr, Ta, V, Zr, etc. can be used.

(2) バリア金属としてNi−Cuの代りにCuのみを
使用してもよい。但し、Sn−Cuは相互拡散が
進行しSnがTiに達するような悪影響を生じな
い程度の厚さのものを使用する。又Niの代り
にCr−Cu合金、Pd−Ptを使用することもでき
る。(2) Only Cu may be used as the barrier metal instead of Ni-Cu. However, the thickness of Sn-Cu is such that interdiffusion will not proceed and Sn will reach Ti, which will not cause an adverse effect. Moreover, Cr--Cu alloy or Pd--Pt can also be used instead of Ni.

(3) SnめつきしたCuフレームへのSiチツプ接合
においてフラツクスを使用すればさらに接合が
容易となる。(3) If flux is used to bond the Si chip to the Sn-plated Cu frame, bonding will become even easier.

(4) 不活性雰囲気はN2＋H2以外にアルゴン
（Ar）ガスを使用してもよい。(4) In addition to N 2 + H 2 , argon (Ar) gas may be used as the inert atmosphere.

(5) フレーム、ステム側はFeを母材とし表面の
みがCuであつてもよい。(5) The frame and stem sides may be made of Fe as the base material and only the surface may be made of Cu.

(6) ペレツト付は連続炉を使用し自動化すること
ができる。(6) Pelleting can be automated using a continuous furnace.

本発明はSiチツプの寸法が３mm平方を超す程度
の半導体装置（トランジスタ、IC、LSI）の全て
において適用できる。 The present invention can be applied to all semiconductor devices (transistors, ICs, LSIs) in which the Si chip size exceeds 3 mm square.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ａ，ｂは従来の半導体チツプを基板へ取
付ける例を示す工程図である。第２図及び第３図
は本発明による半導体チツプを基板へ取付ける実
施例を示す各工程の断面図、第４図はパワーサイ
クルに対する累積不良率における本発明の効果を
示す曲線図である。 １……半導体チツプ、２……リードフレーム
（Cu基板）、３……Au−Si共晶層、４……Au
（Ag）膜、５……Au−Si接合、６……Ti膜、７
……Ni膜、８……Cu膜、９……Sn膜、１０……
青銅合金層。 FIGS. 1a and 1b are process diagrams showing an example of attaching a conventional semiconductor chip to a substrate. FIGS. 2 and 3 are cross-sectional views of each process showing an embodiment of attaching a semiconductor chip to a substrate according to the present invention, and FIG. 4 is a curve diagram showing the effect of the present invention on cumulative failure rate with respect to power cycles. 1...Semiconductor chip, 2...Lead frame (Cu substrate), 3...Au-Si eutectic layer, 4...Au
(Ag) film, 5...Au-Si junction, 6...Ti film, 7
...Ni film, 8...Cu film, 9...Sn film, 10...
Bronze alloy layer.

Claims (1)

【特許請求の範囲】[Claims] １ 半導体と少なくとも表面が銅からなる支持基
板とを接合するにあたつて、その半導体表面上に
銅膜を形成し、一方支持基板表面上にすず膜を形
成し、上記銅膜と上記すず膜とを接触、融着させ
た後、その融着温度より低い温度でシンタ処理す
ることを特徴とする半導体装置の製造法。1. When bonding a semiconductor and a supporting substrate at least the surface of which is made of copper, a copper film is formed on the surface of the semiconductor, a tin film is formed on the surface of the supporting substrate, and the copper film and the tin film are bonded together. 1. A method for manufacturing a semiconductor device, which comprises contacting and fusion bonding the semiconductor devices, and then sintering at a temperature lower than the fusion temperature.
JP1335479A 1979-02-09 1979-02-09 Semiconductor device and method of manufacturing the same Granted JPS55107238A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1335479A JPS55107238A (en) 1979-02-09 1979-02-09 Semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1335479A JPS55107238A (en) 1979-02-09 1979-02-09 Semiconductor device and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPS55107238A JPS55107238A (en) 1980-08-16
JPS6153851B2 true JPS6153851B2 (en) 1986-11-19

Family

ID=11830759

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1335479A Granted JPS55107238A (en) 1979-02-09 1979-02-09 Semiconductor device and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JPS55107238A (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5768040A (en) * 1980-10-15 1982-04-26 Hitachi Ltd Electrode structure for semiconductor device
JPS57210637A (en) * 1981-06-18 1982-12-24 Mitsubishi Electric Corp Semiconductor device
JPS59193036A (en) * 1983-04-16 1984-11-01 Toshiba Corp Semiconductor device
US5288456A (en) * 1993-02-23 1994-02-22 International Business Machines Corporation Compound with room temperature electrical resistivity comparable to that of elemental copper
JP2007109829A (en) * 2005-10-12 2007-04-26 Dowa Holdings Co Ltd Solder joint forming method
US9214442B2 (en) * 2007-03-19 2015-12-15 Infineon Technologies Ag Power semiconductor module, method for producing a power semiconductor module, and semiconductor chip
JP6046010B2 (en) * 2013-09-09 2016-12-14 株式会社東芝 Semiconductor device and manufacturing method thereof
JP6477517B2 (en) * 2016-01-20 2019-03-06 トヨタ自動車株式会社 Manufacturing method of semiconductor device
JP6507120B2 (en) * 2016-03-31 2019-04-24 Ｊｘ金属株式会社 Semiconductor in which the bonding surface with a substrate is surface-treated, and bonding method using copper powder paste

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS527675A (en) * 1975-07-09 1977-01-20 Hitachi Ltd Semiconductor device
JPS5353256A (en) * 1976-10-25 1978-05-15 Mitsubishi Electric Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS527675A (en) * 1975-07-09 1977-01-20 Hitachi Ltd Semiconductor device
JPS5353256A (en) * 1976-10-25 1978-05-15 Mitsubishi Electric Corp Semiconductor device

Also Published As

Publication number Publication date
JPS55107238A (en) 1980-08-16

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