KR20010039787A - Semiconductor device and a method for assembling the same - Google Patents
Semiconductor device and a method for assembling the same Download PDFInfo
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- KR20010039787A KR20010039787A KR1020000045206A KR20000045206A KR20010039787A KR 20010039787 A KR20010039787 A KR 20010039787A KR 1020000045206 A KR1020000045206 A KR 1020000045206A KR 20000045206 A KR20000045206 A KR 20000045206A KR 20010039787 A KR20010039787 A KR 20010039787A
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- tape
- semiconductor chip
- oxidation
- wafer
- dicing
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 title abstract description 22
- 230000003064 anti-oxidating effect Effects 0.000 claims abstract description 34
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910052802 copper Inorganic materials 0.000 claims abstract description 25
- 239000010949 copper Substances 0.000 claims abstract description 25
- 229910000881 Cu alloy Inorganic materials 0.000 claims abstract description 11
- 239000003963 antioxidant agent Substances 0.000 claims description 11
- 230000003078 antioxidant effect Effects 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 description 11
- 238000007254 oxidation reaction Methods 0.000 description 11
- 239000007789 gas Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Dicing (AREA)
Abstract
Description
(발명이 속하는 기술분야)(Technical field to which the invention belongs)
본 발명은 구리 또는 구리합금으로 이루어지는 패드를 갖는 반도체장치의 조립방법 및 반도체장치에 관한 것이다.The present invention relates to a method for assembling a semiconductor device having a pad made of copper or a copper alloy and to a semiconductor device.
(종래의 기술)(Conventional technology)
반도체칩의 배선 및 패드의 재질은 일반적으로 알루미늄이 사용되고 있다. 그러나, 최근, 배선지연을 삭감시키기 위하여 저저항으로 미세하게 할 수 있는 구리배선 및 구리패드가 사용되게 되어 있다. 예를 들면, NIKKEI MICRO DEVICES 1999년 7월호 제 52면∼제 56면 참조.Aluminum is generally used for wiring and pads of semiconductor chips. In recent years, however, copper wiring and copper pads that can be made fine with low resistance have been used to reduce wiring delay. See, eg, NIKKEI MICRO DEVICES, July 1999, pages 52 to 56.
(발명이 해결하려고 하는 과제)(Problem that invention tries to solve)
반도체칩은 웨이퍼를 다이싱하여 얻어진다. 그러나, 웨이퍼의 표면의 패드가 구리의 경우, 구리패드가 노출한 채로 다이싱, 다이본딩을 행하면 산화막이 형성되고, 와이어본딩시에 와이어가 붙지 않는 등의 좋지 않는 경우가 생긴다.A semiconductor chip is obtained by dicing a wafer. However, when the pad on the surface of the wafer is copper, when dicing and die bonding are performed while the copper pad is exposed, an oxide film is formed, which may not be good such as a wire not sticking at the time of wire bonding.
본 발명의 제 1 과제는, 웨이퍼로부터 다이본딩후까지에 있어서 구리패드의 산화를 방지할 수 있는 반도체장치의 조립방법 및 반도체장치를 제공하는 것에 있다.A first object of the present invention is to provide a method for assembling a semiconductor device and a semiconductor device which can prevent oxidation of a copper pad from the wafer to after the die bonding.
본 발명의 제 2 과제는, 상기 제 1 과제 외에, 더욱더 와이어본딩공정까지에 있어서 구리패드의 산화를 방지할 수 있는 반도체장치의 조립방법 및 반도체장치를 제공하는 것에 있다.The 2nd subject of this invention is providing the semiconductor device assembly method and semiconductor device which can prevent the oxidation of a copper pad further up to a wire bonding process besides the said 1st subject.
더우기, 구리패드의 경우에 적용한 것은 아니지만, 웨이퍼의 표면에 표면보호시트를 첩부(貼付)하여 다이싱을 행하는 것으로서, 예를 들면 일본특개평 5-315445호 공보를 들 수 있다. 이 방법에 있어서 표면보호시트는 웨이퍼의 표면을 보호하기 위한 것이고, 구리패드의 산화를 방지하는 것은 아니다. 또 표면보호시트를 제거한 후에 반도체칩을 리드프레임 등(패키지)에 다이본딩하므로, 이 방법을 구리패드에 적용한 경우, 표면보호시트의 제거공정과 다이본딩공정사이, 다이본딩시, 다이본딩후의 산화는 방지할 수 없다.Moreover, although not applied to the case of a copper pad, Japanese Unexamined-Japanese-Patent No. 5-315445 is mentioned as a dicing which affixes a surface protection sheet on the surface of a wafer. In this method, the surface protection sheet is for protecting the surface of the wafer and does not prevent oxidation of the copper pad. In addition, since the semiconductor chip is die-bonded to a lead frame or the like after the surface protection sheet is removed, when this method is applied to a copper pad, the oxidation after the die bonding is performed between the removal and die bonding process of the surface protection sheet. Cannot be prevented.
(과제를 해결하기 위한 수단)(Means to solve the task)
상기 과제를 해결하기 위한 본 발명의 제 1 반도체장치의 조립방법은 패드가 구리 또는 구리합금으로 이루어지는 웨이퍼의 표면에 산화방지용 테이프를 첩부하는 산화방지용 테이프 첩부공정과, 다이싱용 테이프상에 상기 웨이퍼의 이면을 첩부하여 다이싱을 행하고, 산화방지용 테이프가 붙은 반도체칩으로 하는 다이싱공정과, 이 산화방지용 테이프가 붙은 반도체칩을 리드프레임 등에 본딩하는 다이공정으로 이루어지는 것을 특징으로 한다.An assembly method of the first semiconductor device of the present invention for solving the above problems is an antioxidant tape applying step of attaching an anti-oxidation tape to a surface of a wafer whose pad is made of copper or a copper alloy; It comprises a dicing step which affixes a back surface and makes a semiconductor chip with an antioxidant tape, and the die process which bonds this semiconductor chip with an antioxidant tape to a lead frame etc., It is characterized by the above-mentioned.
상기 과제를 해결하기 위한 본 발명의 제 2 반도체장치의 조립방법은, 패드가 구리 또는 구리합금으로 이루어지는 웨이퍼의 표면에 산화방지용 테이프를 첩부하는 산화방지용 테이프 첩부공정과, 다이싱용 테이프상에 상기 웨이퍼의 이면을 첩부하여 다이싱을 행하고, 산화방지용 테이프가 붙은 반도체칩으로 하는 다이싱공정과, 이 산화방지용 테이프가 붙은 반도체칩을 리드프레임 등에 본딩하는 다이본딩공정과, 반도체칩상의 산화방지용 테이프를 제거하는 산화방지용 테이프 제거공정과, 이 공정의 직후에 반도체칩의 패드와 리드프레임 등의 리드에 와이어를 접속하는 와이어본딩공정으로 이루어지는 것을 특징으로 한다.An assembly method of a second semiconductor device of the present invention for solving the above problems includes an anti-oxidation tape sticking step of attaching an anti-oxidation tape to a surface of a wafer whose pad is made of copper or a copper alloy, and the wafer on a dicing tape. The dicing process is carried out by affixing the back surface of the substrate to form a semiconductor chip with an anti-oxidation tape, a die bonding step of bonding the semiconductor chip with an anti-oxidation tape to a lead frame or the like, and an anti-oxidation tape on the semiconductor chip. And a wire bonding step of connecting a wire to a lead such as a pad of the semiconductor chip and a lead frame immediately after the step.
상기 과제를 해결하기 위한 본 발명의 제 1 반도체장치는 패드가 구리 또는 구리합금으로 이루어지는 웨이퍼의 표면에 산화방지용 테이프를 첩부하여 다이싱용 테이프상에 상기 웨이퍼의 이면을 첩부하여 다이싱을 행하여 산화방지용 테이프가 붙은 반도체칩으로 하고, 이 산화방지용 테이프가 붙은 반도체칩을 리드프레임 등에 본딩하여 이루어지는 것을 특징으로 한다.In the first semiconductor device of the present invention for solving the above problems, an anti-oxidation tape is attached to a surface of a wafer of which a pad is made of copper or a copper alloy, and the back side of the wafer is attached to a dicing tape to perform dicing to prevent oxidation. A semiconductor chip with a tape is used, and the semiconductor chip with an antioxidant tape is bonded to a lead frame or the like.
상기 과제를 해결하기 위한 본 발명의 제 2 반도체장치는 패드가 구리 또는 구리합금으로 이루어지는 웨이퍼의 표면에 산화방지용 테이프를 첩부하여, 다이싱용 테이프상에 상기 웨이퍼의 이면을 첩부하여 다이싱을 행하여 산화방지용 테이프가 붙은 반도체칩으로 하고, 이 산화방지용 테이프가 붙은 반도체칩을 리드프레임 등에 본딩하고, 반도체칩상의 산화방지용 테이프를 제거하고, 반도체칩의 패드와 리드프레임 등의 리드에 와이어를 접속하여 이루어지는 것을 특징으로 한다.In the second semiconductor device of the present invention for solving the above problems, an anti-oxidation tape is affixed on a surface of a wafer whose pad is made of copper or a copper alloy, and the back surface of the wafer is affixed on a dicing tape to perform oxidation by dicing. A semiconductor chip with an anti-tape tape is formed by bonding the semiconductor chip with an anti-oxidation tape to a lead frame or the like, removing the anti-oxidation tape on the semiconductor chip, and connecting a wire to a pad of the semiconductor chip and a lead such as a lead frame. It is characterized by.
도 1은 본 발명의 반도체장치의 조립방법의 일 실시형태를 도시하는 공정설명도,1 is a process explanatory diagram showing one embodiment of a method for assembling the semiconductor device of the present invention;
도 2는 도 1의 계속 공정설명도.Figure 2 is a continuation process diagram of Figure 1;
(도면의 주요부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
1: 웨이퍼 2: 산화방지용 테이프1: wafer 2: anti-oxidation tape
3: 다이싱용 테이프 4: 홈3: tape for dicing 4: groove
5: 반도체 칩 6: 리드프레임 등5: semiconductor chip 6: leadframe etc.
7: 리드 8: 접착제7: lead 8: glue
9: 와이어9: wire
(발명의 실시형태)Embodiment of the Invention
본 발명의 일 실시형태를 도 1 및 도 2에 의하여 설명한다. 우선 도 1a에 도시하는 바와 같이, 구리 또는 구리합금으로 이루어지는 패드(도시하지 않음)가 형성된 웨이퍼(1)의 표면에 산화 및 물을 방지하는 산화방지용 테이프(2)를 첩부한다. 다음에 도 1b에 도시하는 바와 같이 웨이퍼(1)의 이면에 다이싱용 테이프(3)를 첩부한다. 그 후 도 1c에 도시하는 바와 같이, 웨이퍼(1)의 표면측에서 보아 종횡으로 등간격으로 다이싱을 행하여 홈(4)을 형성하고, 산화방지용 테이프(2)가 붙어 있는 개개의 반도체칩(5)으로 한다. 그리고, 다이싱용 테이프(3)를 도시하지 않는 인신(引伸)장치로 잡아 늘리고, 산화방지용 테이프(2)가 붙은 반도체칩(5)의 간격을 넓힌다.An embodiment of the present invention will be described with reference to FIGS. 1 and 2. First, as shown in FIG. 1A, the antioxidant tape 2 which prevents oxidation and water is affixed on the surface of the wafer 1 in which the pad (not shown) which consists of copper or a copper alloy was formed. Next, as shown in FIG. 1B, the dicing tape 3 is stuck to the back surface of the wafer 1. After that, as shown in FIG. 1C, the dicing is carried out at equal intervals in the vertical and horizontal directions as viewed from the surface side of the wafer 1 to form the grooves 4, and the individual semiconductor chips having the anti-oxidation tape 2 ( 5). Then, the dicing tape 3 is stretched by a human device not shown, and the interval between the semiconductor chips 5 with the anti-oxidation tape 2 is widened.
이와 같이 잡아 늘린 반도체칩(5)이 붙은 다이싱용 테이프(3)를 다이본딩장치의 반도체칩 픽업부에 설치한다. 도시하지 않는 다이본딩장치에 있어서는, 도 1d에 도시하는 바와 같이 리드프레임 또는 기판 등(이하, 리드프레임 등이라 함)(6)에 도포된 접착제(8)상에 산화방지용 테이프(2)가 붙은 반도체칩(5)을 다이본딩한다.The dicing tape 3 with the semiconductor chip 5 stretched in this manner is attached to the semiconductor chip pickup portion of the die bonding apparatus. In the die-bonding apparatus (not shown), as shown in FIG. 1D, an anti-oxidation tape 2 is adhered on the adhesive 8 applied to the lead frame or the substrate (hereinafter referred to as lead frame or the like) 6. The semiconductor chip 5 is die bonded.
그 후, 반도체칩(5)이 다이본딩된 리드프레임 등(6)을 도시하지 않는 와이어본딩장치에 공급한다. 이 와이어본딩장치로 와이어본딩을 행하기 직전에, 표면으로부터 자외선을 조사하여 산화방지용 테이프(2)의 접착력을 저하시킨후, 콜릿 등으로 산화방지용 테이프(2)를 진공흡착하고, 도 1e에 도시하는 바와 같이, 산화방지용 테이프(2)를 제거한다. 계속하여 와이어본딩장치에서는 도 2에 도시하는 바와 같이, 반도체칩(5)의 패드(도시하지 않음)와 리드프레임 등(6)의 리드(7)에 와이어(9)를 접속한다. 더우기, 산화방지용 테이프(2)의 제거 및 와이어본딩은 환원성가스 또는 불활성가스, 그렇지 않으면 환원성가스와 불활성가스의 혼합가스의 분위기중에서 행한다.Then, the lead frame etc. 6 with which the semiconductor chip 5 was die-bonded is supplied to the wire bonding apparatus which is not shown in figure. Immediately before wire bonding with this wire bonding apparatus, ultraviolet rays are irradiated from the surface to lower the adhesive force of the antioxidant tape 2, and then the antioxidant tape 2 is vacuum-adsorbed with a collet or the like and shown in Fig. 1E. As described above, the antioxidant tape 2 is removed. Subsequently, in the wire bonding apparatus, as shown in FIG. 2, the wire 9 is connected to the pad (not shown) of the semiconductor chip 5 and the lead 7 of the lead frame or the like 6. In addition, removal and wire bonding of the antioxidant tape 2 are performed in an atmosphere of reducing gas or inert gas, otherwise, a mixed gas of reducing gas and inert gas.
이와 같이, 웨이퍼(1)의 표면에는 산화방지용 테이프(2)가 첩부된 상태에서 도 1c에 도시하는 바와 같이 다이싱을 행하여 홈(4)을 형성하고, 또 다이본딩공정에 있어서, 도 1d에 도시하는 바와 같이 산화방지용 테이프(2)가 붙은 반도체칩(5)을 다이본딩하므로, 다이본딩까지의 공정 및 다이본딩후에 있어서도 반도체칩(5)의 구리패드의 산화는 방지된다. 또 도 1e에 도시하는 산화방지용 테이프(2)를 제거하는 공정후에 도 2에 도시하는 와이어본딩공정을 연속하여 행함으로써 도 1e와 도 2 사이에 있어서 반도체칩(5)의 구리패드의 산화는 방지된다.As described above, the groove 4 is formed by dicing as shown in FIG. 1C with the anti-oxidation tape 2 affixed on the surface of the wafer 1, and in the die bonding step, the groove 4 is shown in FIG. 1D. As shown, since the semiconductor chip 5 with the anti-oxidation tape 2 is die-bonded, oxidation of the copper pad of the semiconductor chip 5 is prevented even after the process up to die bonding and after die bonding. After the step of removing the antioxidant tape 2 shown in FIG. 1E, the wire bonding process shown in FIG. 2 is continuously performed to prevent oxidation of the copper pad of the semiconductor chip 5 between FIGS. 1E and 2. do.
본 발명의 청구항 1 및 3에 의하여, 웨이퍼로부터 다이본딩후까지에 있어서 구리패드의 산화를 방지할 수가 있다. 또 본 발명의 청구항 2 및 4에 의하여, 상기 효과 외에 다시 와이어본딩공정까지에 있어서 구리패드의 산화를 방지할 수가 있다.According to Claims 1 and 3 of the present invention, oxidation of the copper pad can be prevented from the wafer to after the die bonding. In addition, according to Claims 2 and 4 of the present invention, oxidation of the copper pad can be prevented up to the wire bonding step in addition to the above effects.
Claims (4)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP99-229556 | 1999-08-16 | ||
| JP22955699A JP3271762B2 (en) | 1999-08-16 | 1999-08-16 | Semiconductor device assembling method and semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010039787A true KR20010039787A (en) | 2001-05-15 |
| KR100385870B1 KR100385870B1 (en) | 2003-06-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2000-0045206A KR100385870B1 (en) | 1999-08-16 | 2000-08-04 | Semiconductor device and a method for assembling the same |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP3271762B2 (en) |
| KR (1) | KR100385870B1 (en) |
| TW (1) | TW455963B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101128687B1 (en) * | 2004-12-22 | 2012-03-26 | 매그나칩 반도체 유한회사 | Method for manufacturing semiconductor chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100486290B1 (en) * | 2002-12-23 | 2005-04-29 | 삼성전자주식회사 | Assembling method of semiconductor package and removal apparatus of protection tape in semiconductor process |
| CN106132086A (en) * | 2016-07-08 | 2016-11-16 | 广东小天才科技有限公司 | A kind of board structure of circuit and electronic component soldering method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0727905B2 (en) * | 1986-03-04 | 1995-03-29 | 株式会社東芝 | Method of forming solder bumps |
| KR0152364B1 (en) * | 1995-06-30 | 1998-12-01 | 김주용 | Die bonding method and apparatus |
-
1999
- 1999-08-16 JP JP22955699A patent/JP3271762B2/en not_active Expired - Fee Related
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2000
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101128687B1 (en) * | 2004-12-22 | 2012-03-26 | 매그나칩 반도체 유한회사 | Method for manufacturing semiconductor chip |
Also Published As
| Publication number | Publication date |
|---|---|
| TW455963B (en) | 2001-09-21 |
| KR100385870B1 (en) | 2003-06-02 |
| JP3271762B2 (en) | 2002-04-08 |
| JP2001053087A (en) | 2001-02-23 |
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