TW455963B - Semiconductor device and assembly method of the same - Google Patents
Semiconductor device and assembly method of the same Download PDFInfo
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- TW455963B TW455963B TW089113685A TW89113685A TW455963B TW 455963 B TW455963 B TW 455963B TW 089113685 A TW089113685 A TW 089113685A TW 89113685 A TW89113685 A TW 89113685A TW 455963 B TW455963 B TW 455963B
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- tape
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 title claims abstract description 42
- 229910052802 copper Inorganic materials 0.000 claims abstract description 25
- 239000010949 copper Substances 0.000 claims abstract description 25
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910000881 Cu alloy Inorganic materials 0.000 claims abstract description 11
- 235000012431 wafers Nutrition 0.000 claims description 62
- 230000003647 oxidation Effects 0.000 claims description 45
- 238000007254 oxidation reaction Methods 0.000 claims description 45
- 230000002265 prevention Effects 0.000 claims description 27
- 239000002390 adhesive tape Substances 0.000 claims description 17
- 239000013078 crystal Substances 0.000 claims description 2
- 239000008186 active pharmaceutical agent Substances 0.000 claims 1
- 229940098465 tincture Drugs 0.000 claims 1
- 230000003064 anti-oxidating effect Effects 0.000 abstract 4
- 239000000853 adhesive Substances 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 230000002079 cooperative effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Dicing (AREA)
Abstract
Description
455963 A7 B7 五、發明説明（f ) 【發明所屬之技術領域】 本發明，係關於具有由銅或銅合金所構成之接合墊的 半導體裝置之組裝方法及半導體裝置。 【先前技術】 半導體晶片之配線及接合墊之材質，一般使甩鋁。然 而’最近爲降低配線延遲，逐漸使用低電阻而能細加工之 銅配線及銅接合墊。例如，參照NIKKEI MICRO DEVICES 1999年7月號第52頁〜第56頁。 【發明所要解決之課題】 半導體晶片，係切割晶圓而製成。但是在晶圓表面之 接合墊爲銅之情形，若以銅接合墊露出之狀態作切割、晶 粒接合，則會形成氧化膜，造成在引線接合時產生引線不 附著之缺陷。 本發明之第1課題，係提供一從晶圓至晶粒接合後爲 止能防止銅接合墊氧化的半導體裝置之組裝方法及半導體 裝置。 本發明之第2課題，係在前述第1課題外，提供一進 一步至引線接合製程爲止能防止銅接合墊氧化的半導體裝 置之組裝方法及半導體裝置。 又’雖非適用於銅接合墊之情形’但例如日本專利特 開平5 - 315445號公報提示出，在晶圓表面貼上表面保護 片後再進行切割者。該方法之表面保護片係爲保護晶圓表 面而用，並非爲防止銅接合墊之氧化而用。又因在去除表 面保護片後，再將半導體晶片接合在引腳框等〈封裝>， 本紙張尺度適用中國國家標準（CNS ) Μ規格（2! 0 X 297公釐> (請先聞讀背面之注意事項再填寫本ΐκ }455963 A7 B7 V. Description of the invention (f) [Technical field to which the invention belongs] The present invention relates to a method for assembling a semiconductor device having a bonding pad made of copper or a copper alloy, and a semiconductor device. [Previous technology] The wiring of semiconductor wafers and the material of bonding pads are generally made of aluminum. However, recently, in order to reduce wiring delay, copper wiring and copper bonding pads that can be finely processed with low resistance have been gradually used. For example, refer to NIKKEI MICRO DEVICES July 1999, pages 52 to 56. [Problem to be Solved by the Invention] A semiconductor wafer is produced by cutting a wafer. However, when the bonding pads on the wafer surface are copper, if the copper bonding pads are exposed for cutting and crystal bonding, an oxide film will be formed, resulting in the defect of non-adhesion of leads during wire bonding. A first object of the present invention is to provide a semiconductor device assembly method and a semiconductor device capable of preventing oxidation of a copper bonding pad after bonding from a wafer to a die. A second problem of the present invention is to provide a method of assembling a semiconductor device and a semiconductor device capable of preventing oxidation of a copper bonding pad until the wire bonding process is performed in addition to the above-mentioned first problem. "Although it is not applicable to copper bonding pads", for example, Japanese Patent Application Laid-Open No. 5-315445 suggests that a surface protection sheet should be attached to the wafer surface before cutting. The surface protection sheet of this method is used to protect the surface of the wafer, not to prevent oxidation of the copper bonding pad. Since the surface protection sheet is removed, and then the semiconductor wafer is bonded to the lead frame, etc. <Packaging>, this paper size applies the Chinese National Standard (CNS) M specification (2! 0 X 297 mm >) Read the notes on the back and fill out this ΐκ}
、1T 經濟部智慧財產局員工消費合作社印製 4559 6 3 A7 B7 五、發明説明（>) 右應用該方法於銅接合墊時，在表面保護片之去除製程與 晶粒接合製程間、晶粒接合時、晶粒接合後之氧化均無法 防止。 【解決課題之手段】 爲解決上述課題，本發明第1之半導體裝置之組裝方 法’其特徵在於，由下列製程構成：在接合墊由銅或銅合 金所構成之晶圓表面貼上氧化防止用膠布的氧化防止用膠 布貼附製程；將前述晶圓之背面貼在切割用膠布後進行切 割’做成附氧化防止用膠布之半導體晶片的切割製程；以 及’將該附氧化防止用膠布之半導體晶片接合在引腳框等 的晶粒接合製程。 爲解決上述課題’本發明第2之半導體裝置之組裝方 法，其特徵在於，由下列製程構成：在接合墊由銅或銅合 金所構成之晶圓表面貼上氧化防止用膠布的氧化防止用膠 布貼者製程；將則述晶圓之背面貼在切割用膠布後進行切 割，做成附氧化防止用膠布之半導體晶片的切割製程；將 該附氧化防止用膠布之半導體晶片接合在引腳框等的晶粒 接合製程；去除半導體晶片上之氧化防止用膠布的氧化防 止用膠布去除製程；以及，緊接於該製程後之將半導體晶 片的接合墊與引腳框等的引腳用引線連接之引線接合製程 〇 爲解決上述課題，本發明之第1半導體裝置，其特徵 在於：在接合墊由銅或銅合金所構成之晶圓表面貼上氧化 防止用膠布，將前述晶圓之背面貼在切割用膠布後進行切 4 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智M財產局員工消費合作杜印製 A7 455963 B7_ 五、發明説明（>) 割，做成附氧化防止用膠布之半導體晶片，將該附氧化防 止用膠布之半導體晶片接合在引腳框等而成。 爲解決上述課題，本發明之第2半導體裝置，其特徵 在於：在接合墊由銅或銅合金所構成之晶圓表面貼上氧化 防止用膠布，將前述晶圓之裏面貼在切割用膠布後進行切 割、做成附氧化防止用膠布之半導體晶片，將該附氧化防 止用膠布之半導體晶片接合於引腳框等，去除半導體晶片 上之氧化防止用膠布，將半導體晶片之接合墊與引腳框等 的引腳用引線連接而成= 【發明之實施形態】 以圖1及圖2說明本發明之一實施形態。首先，如圖 1 1(a)所示，在形成有銅或銅合金所構成的接合墊(未圖示)之 晶圓丨之表面，貼上防氧化及水之氧化防止用膠布2。其 次，如圖1(b)所示，在晶圓1之背面，貼上切割用膠布3 。之後，如圖1(c)所示，從晶圓1之表面側看，進行縱橫 方向之等間隔切割而形成槽4，以做成附氧化防止用膠布2 之各個半導體晶片5。然後，以未圖示之拉伸裝置拉伸切 割用膠布3，以拉大附氧化防止用膠布2之半導體晶片5 的間隔。 如此，將拉伸後之附半導體晶片5的切割用膠布3， 設置在晶粒接合裝置之半導體晶片拾起部。在未圖示之晶 粒接合裝置中，如圖1(d)所示，在塗佈於引腳框或基板等 (以下稱爲引腳框等）6之接著劑8上，進行附氧化防止用 膠布2之半導體晶片5的晶粒接合。 5 本紙張尺度適用中國圉家標準（CNS ) A4現格（210X297公釐） (請先閎讀背面之注意事項再填寫本頁) 訂Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4559 6 3 A7 B7 V. Description of the invention (>) When the method is applied to copper bonding pads, the process of removing the surface protection sheet and the die bonding process, Oxidation during grain bonding and after grain bonding cannot be prevented. [Means for solving problems] In order to solve the above-mentioned problems, the first method of assembling a semiconductor device according to the present invention is characterized in that it is composed of the following process: The surface of a wafer whose bonding pad is made of copper or a copper alloy is oxidized. A process for attaching an adhesive tape for preventing oxidation of an adhesive tape; attaching a back surface of the aforementioned wafer to a dicing adhesive tape for cutting; and a process of dicing a semiconductor wafer with an adhesive tape for preventing oxidation; and a semiconductor for applying the adhesive tape for preventing oxidation The wafer is bonded to a die bonding process such as a lead frame. In order to solve the above-mentioned problem, the method of assembling the second semiconductor device of the present invention is characterized in that it is composed of the following process: an oxidation prevention tape is affixed to the surface of the wafer with a bonding pad made of copper or a copper alloy. Adhering process; dicing the back of the wafer to a dicing tape and cutting to form a dicing process for a semiconductor wafer with an oxidation prevention tape; bonding the semiconductor wafer with an oxidation prevention tape to a lead frame, etc. A die bonding process; removing the oxidation preventing tape on the semiconductor wafer; and, immediately after the process, connecting the bonding pad of the semiconductor wafer with the lead of a lead frame or the like by a lead. In order to solve the above-mentioned problems, the first semiconductor device of the present invention is characterized in that an oxidation prevention tape is attached to a surface of a wafer made of copper or a copper alloy with a bonding pad, and a back surface of the wafer is attached to Cut with adhesive tape after cutting 4 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the back first Please fill in this page for the matters needing attention) Order the consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs, Du printed A7 455963 B7_ V. Description of the invention (>) Cut and make a semiconductor wafer with an oxidation prevention tape. The semiconductor wafer of the adhesive tape is bonded to a lead frame or the like. In order to solve the above-mentioned problem, a second semiconductor device of the present invention is characterized in that an oxidation prevention tape is attached to a surface of a wafer whose bonding pad is made of copper or a copper alloy, and the inside of the wafer is attached to a dicing tape. Dicing is performed to form a semiconductor wafer with an oxidation prevention tape, the semiconductor wafer with the oxidation prevention tape is bonded to a lead frame, etc., the oxidation prevention tape is removed from the semiconductor wafer, and the bonding pads and pins of the semiconductor wafer are removed. Leads such as frames are connected with leads = [Embodiment of the invention] An embodiment of the present invention will be described with reference to Figs. 1 and 2. First, as shown in FIG. 11 (a), on the surface of a wafer with a bonding pad (not shown) made of copper or a copper alloy, an adhesive 2 for preventing oxidation and water oxidation is attached. Next, as shown in FIG. 1 (b), a dicing tape 3 is attached to the back surface of the wafer 1. Thereafter, as shown in FIG. 1 (c), as viewed from the surface side of the wafer 1, slits 4 are formed at equal intervals in the vertical and horizontal directions to form individual semiconductor wafers 5 with an oxidation prevention tape 2. Then, the dicing tape 3 is stretched by a stretching device (not shown) to increase the gap between the semiconductor wafers 5 with the oxidation prevention tape 2. In this way, the dicing tape 3 with the semiconductor wafer 5 attached after the stretching is set in the semiconductor wafer pick-up portion of the die bonding apparatus. In a die bonding device (not shown), as shown in FIG. 1 (d), an adhesive agent 8 is applied to a bonding agent 8 coated on a lead frame or a substrate (hereinafter referred to as a lead frame, etc.) 6 to prevent oxidation. Die bonding of the semiconductor wafer 5 by the adhesive tape 2. 5 This paper size is in accordance with Chinese Standard (CNS) A4 (210X297mm) (please read the precautions on the back before filling this page) Order
iA 經濟部智慧財產局員工消費合作社印製 455963 A7 I---------B7_ 五、發明説明（ (請先閲讀背面之注意事項再填寫本頁) 其後，將已接合半導體晶片5之引腳框等6供給至未 圖I之引線接合裝置。在該引線接合裝置剛要進行引線接 合前’從表面照射紫外線而降低氧化防止用膠布2之接著 力後’用吸附保持具(c〇Uet)真空吸附住氧化防止用膠布2 ’以如圖1(e)所示般去除氧化防止用膠布2。接著在引線接 合裝置’如圖2所示，在半導體晶片5之接合墊(未圖示) 與引腳框等6之引腳7上連接引線9。又，氧化防止用膠 布2之去除及引線接合，要在還原性氣體 '惰性氣體、或 還原性氣體與惰性氣體之混合氣體的環境氣氛中進行。 如此般’因在將氧化防止用膠布2貼於晶圓1之表面 的狀態下’如圖1(c)所示進行切割來形成溝4，又因在晶粒 接合製程中，如圖1(d)所示將附氧化防止用膠布2之半導 體晶片5實施接合，故至晶粒接合爲止之製程及晶粒接合 後，均能防止半導體晶片5之銅接合墊的氧化。又在圖 1(e)所示之去除氧化防止用膠布2的製程後，藉由連續進行 圖2所示之引線接合製程，將能防止圖1(e)與圖2間之半 導體晶片5之銅接合墊的氧化。 【發明之效果】 經濟部智慧財產局員工消費合作社印說 依據本發明之申請專利範圍第1及第3項，在從晶圓 至晶粒接合後爲止能防止銅接合墊的氧化。又依據本發明 之申請專利範圍第2及第4項，除前述效果外，更能在至 引線接合製程爲止防止銅接合墊的氧化。 【圖式之簡單說明】 圖1係顯示本發明之半導體裝置之組裝方法之一實施 6 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0X 297公爱） 45 59 6 A7 87 五、發明説明（ 形態的製程說明圖。 圖2係圖I的後續製程說明圖。 【符號之說明】 1 2 3 4 5 6 7 8 9 晶圓 氧化防止用膠布 切割用膠布 槽 半導體晶片 引腳框等 引腳 接著劑 引線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 7 本纸張尺度適用中國國家標準（CNS ) A4規格（210X297公釐}Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs of the Ministry of Economic Affairs 455963 A7 I --------- B7_ V. Description of the invention ((Please read the precautions on the back before filling this page) After that, the semiconductor chip will be bonded The lead frame 5 and the like 6 are supplied to a wire bonding device (not shown in Fig. I). Immediately after the wire bonding device is subjected to wire bonding, "after irradiation of ultraviolet rays from the surface to reduce the adhesion force of the oxidation prevention tape 2", an adsorption holder ( c〇et) The oxidation prevention tape 2 'is vacuum-adsorbed to remove the oxidation prevention tape 2 as shown in FIG. 1 (e). Then, in the wire bonding apparatus', as shown in FIG. 2, the bonding pad of the semiconductor wafer 5 ( (Not shown) Connect the lead 9 to the lead 7 of the lead frame 6 etc. In addition, for the removal of the oxidation prevention tape 2 and the wire bonding, a reducing gas, an inert gas, or a mixture of a reducing gas and an inert gas must be used. It is performed in an atmosphere of a gas. In this way, 'due to the state where the oxidation prevention tape 2 is attached to the surface of the wafer 1', the trench 4 is formed by dicing as shown in FIG. 1 (c). During the manufacturing process, as shown in Figure 1 (d), The semiconductor wafer 5 of cloth 2 is bonded, so that the process up to the die bonding and the die bonding can prevent the oxidation of the copper bonding pads of the semiconductor wafer 5. The oxidation prevention removal is shown in FIG. 1 (e). After the production of the adhesive tape 2, by continuously performing the wire bonding process shown in Fig. 2, oxidation of the copper bonding pad of the semiconductor wafer 5 between Fig. 1 (e) and Fig. 2 can be prevented. [Effect of the invention] The wisdom of the Ministry of Economy According to the Consumer Cooperatives of the Property Bureau, according to claims 1 and 3 of the scope of patent application of the present invention, the oxidation of copper bonding pads can be prevented from the wafer to the die bonding. According to the scope of patents 2 and The fourth item, in addition to the aforementioned effects, can prevent the oxidation of the copper bonding pads until the wire bonding process. [Simplified Description of the Drawings] FIG. 1 shows one method of assembling the semiconductor device of the present invention. Applicable to China National Standard (CNS) A4 specification (2 丨 0X 297 public love) 45 59 6 A7 87 V. Description of the invention (Process description of the form. Figure 2 is a follow-up process illustration of Figure I. [Explanation of symbols] 1 2 3 4 5 6 7 8 9 Adhesive grooves for adhesive tape for preventing wafer oxidation. For cutting adhesive tapes for semiconductor wafer lead frames, etc. (Please read the precautions on the back before filling out this page.) 7 copies printed by the Employees ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Paper size applies to China National Standard (CNS) A4 (210X297 mm)
Claims (1)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22955699A JP3271762B2 (en) | 1999-08-16 | 1999-08-16 | Semiconductor device assembling method and semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW455963B true TW455963B (en) | 2001-09-21 |
Family
ID=16894030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW089113685A TW455963B (en) | 1999-08-16 | 2000-07-10 | Semiconductor device and assembly method of the same |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP3271762B2 (en) |
| KR (1) | KR100385870B1 (en) |
| TW (1) | TW455963B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106132086A (en) * | 2016-07-08 | 2016-11-16 | 广东小天才科技有限公司 | Circuit board structure and electronic element welding method |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100486290B1 (en) * | 2002-12-23 | 2005-04-29 | 삼성전자주식회사 | Assembling method of semiconductor package and removal apparatus of protection tape in semiconductor process |
| KR101128687B1 (en) * | 2004-12-22 | 2012-03-26 | 매그나칩 반도체 유한회사 | Method for manufacturing semiconductor chip |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0727905B2 (en) * | 1986-03-04 | 1995-03-29 | 株式会社東芝 | Method of forming solder bumps |
| KR0152364B1 (en) * | 1995-06-30 | 1998-12-01 | 김주용 | Die bonding method and apparatus |
-
1999
- 1999-08-16 JP JP22955699A patent/JP3271762B2/en not_active Expired - Fee Related
-
2000
- 2000-07-10 TW TW089113685A patent/TW455963B/en not_active IP Right Cessation
- 2000-08-04 KR KR10-2000-0045206A patent/KR100385870B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106132086A (en) * | 2016-07-08 | 2016-11-16 | 广东小天才科技有限公司 | Circuit board structure and electronic element welding method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2001053087A (en) | 2001-02-23 |
| KR100385870B1 (en) | 2003-06-02 |
| KR20010039787A (en) | 2001-05-15 |
| JP3271762B2 (en) | 2002-04-08 |
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