JPS59103342A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59103342A JPS59103342A JP21355282A JP21355282A JPS59103342A JP S59103342 A JPS59103342 A JP S59103342A JP 21355282 A JP21355282 A JP 21355282A JP 21355282 A JP21355282 A JP 21355282A JP S59103342 A JPS59103342 A JP S59103342A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- film
- grinding
- tape
- cutting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000000034 method Methods 0.000 claims abstract description 22
- 238000005520 cutting process Methods 0.000 claims abstract description 16
- 230000008569 process Effects 0.000 claims description 7
- 239000004840 adhesive resin Substances 0.000 claims description 5
- 229920006223 adhesive resin Polymers 0.000 claims description 5
- 239000002985 plastic film Substances 0.000 abstract description 2
- 229920006255 plastic film Polymers 0.000 abstract description 2
- 239000007767 bonding agent Substances 0.000 abstract 1
- 239000011347 resin Substances 0.000 abstract 1
- 229920005989 resin Polymers 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 48
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 241000257465 Echinoidea Species 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000008188 pellet Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000001179 sorption measurement Methods 0.000 description 2
- 241000981595 Zoysia japonica Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000000498 cooling water Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- ZZUFCTLCJUWOSV-UHFFFAOYSA-N furosemide Chemical compound C1=C(Cl)C(S(=O)(=O)N)=CC(C(O)=O)=C1NCC1=CC=CO1 ZZUFCTLCJUWOSV-UHFFFAOYSA-N 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法にかかシ、特に半導体ウ
ェハーの裏面研削工程における改良方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to an improved method of back grinding a semiconductor wafer.
半導体装置製造工程には半導体ウエノ・−の裏面を研削
する工程がある。このウエノ・−研削の目的は、■ウェ
ハーの厚さを組立工程に適当な所定厚にするため、■ウ
ェハー裏面の拡散層や酸化膜を除去して電気抵抗を小さ
くし同時にマウント時のアイランド部（ベレット搭載部
）との固着を容易にするため等である。The semiconductor device manufacturing process includes a process of grinding the back surface of the semiconductor wafer. The purpose of this wafer grinding is: - To make the wafer a predetermined thickness suitable for the assembly process, - To reduce the electrical resistance by removing the diffusion layer and oxide film on the backside of the wafer, and at the same time, to reduce the electrical resistance of the island during mounting. This is for the purpose of facilitating fixation with (the pellet mounting part).
従来このウェハー裏面を研削する方法としては第１図に
示すように石英板１１等にワックス１２を介して半導体
ウェハー１３を素子形成部を下側にして接着固定させ研
削を行ない研削が終了すると石英板１１を下側にしてホ
ットプレート上に載置し゛ワックス１２を加熱軟化溶融
せしめてピンセット等でウェハー１３を石英板１１から
剥離する方法が行なわれていた。Conventionally, as shown in FIG. 1, a method for grinding the back side of a wafer is to adhere and fix a semiconductor wafer 13 to a quartz plate 11 or the like through wax 12 with the element forming part facing downward, and then grind the wafer. A method has been used in which the wafer 13 is placed on a hot plate with the plate 11 facing downward, the wax 12 is heated to soften and melt, and the wafer 13 is peeled off from the quartz plate 11 with tweezers or the like.
しかしながら、この方法によると、ウェハー剥離時にウ
ェハーが割れやすく、またワックスを除去するために有
機溶剤を用いかければならない等の欠点がある。このた
め最近は第２図（５）に示すように、ウェハーの素子形
成部に接着剤２１付きの軟質テープ２２を剥離紙２５に
貼シ付け、第２図（ト））の如くウェハーの縁端に沿っ
てテープ２２をカッターナイフ等で切断し、第２図（Ｃ
）のようにテープ面を下側にして中央部が多孔質層２３
からなるステージ２４上に真空吸着させ、研削を行ない
、ブレード３１で研削後テープを剥離する方法が行なわ
れるようになってきた。しかし々からこの方法において
は、■シート切断が自動化できにくい、■割れウェハー
、欠チウエハーの研削ができない、■ウェハーサイズが
変るとステージの大きさを変える必要がある、等の欠点
があった。即ちテープの切断時にウェハーからテープが
はみ出ないように切断する必要があった。テープがウェ
ハー縁端からはみ出ていると第３図に示すように研削時
の冷却水の圧力を受けてテープ２２がウニ・・−の側面
に巻くれ上がるためブレード３１がテープに触ってしま
う。そのためブレードの切れ味が悪くなったシウエハー
割れが起ったシする。そのためカッターナイフでていね
いに切断する必要があ多切断工数がかかった。プレスで
切断することはウェハーの大きさのバラツキがあるため
困難であった。However, this method has drawbacks such as the wafer being easily cracked during wafer peeling and the need to use an organic solvent to remove the wax. For this reason, recently, as shown in FIG. 2 (5), a soft tape 22 with an adhesive 21 is attached to a release paper 25 on the element forming part of the wafer, and the edges of the wafer are pasted as shown in FIG. Cut the tape 22 along the edge with a cutter knife etc.
), the tape surface is facing down and the central part is the porous layer 23.
A method has come to be used in which the tape is vacuum-adsorbed onto a stage 24 consisting of a tape, ground is performed, and the blade 31 is used to peel off the tape after grinding. However, this method has the following drawbacks: 1) It is difficult to automate sheet cutting, 2) It is not possible to grind broken wafers or chipped wafers, and 2) It is necessary to change the size of the stage when the wafer size changes. That is, when cutting the tape, it was necessary to cut the tape so that it would not protrude from the wafer. If the tape protrudes from the edge of the wafer, as shown in FIG. 3, the tape 22 will curl up against the side of the sea urchin due to the pressure of the cooling water during grinding, causing the blade 31 to touch the tape. As a result, the cutting edge of the blade deteriorates and wafer cracking occurs. Therefore, it was necessary to carefully cut with a cutter knife, which required a lot of cutting man-hours. Cutting with a press was difficult due to variations in wafer size.
また割れウェハーや欠はウェハーを研削しようとする時
も、第４図に示すように、割れ、欠けに沿った切断をす
るとステージ中央部の多孔質層２３が露出して吸着力が
不足したシ研削されたシリコンくず３２が多孔質層の中
につまってしまい吸着力の低下をもたらす。そのため実
際には割れ、欠はウェハーの研削は不可能であった。そ
のため拡散工程やＰ／Ｗ工程をパスした良品ペレットヲ
含むウェハーを廃棄せざるをえなかった０又吸着力の安
定と研削後のステージからの脱着の安定のためウェハー
サイズによってステージ２４のサイズが異なっているた
めウェハーサイズによってステージの大きさを変更する
必要があった。ステージ交換の工数はかなりな時間を要
するため、あらかじめステージにウェハーサイズに合わ
せたステージを設けておくことも可能であるがこの場合
は研削能力が著しく低下する。Also, when attempting to grind a cracked or chipped wafer, as shown in Figure 4, if you cut along the crack or chip, the porous layer 23 at the center of the stage will be exposed and the suction force will be insufficient. The ground silicon chips 32 become stuck in the porous layer, resulting in a decrease in adsorption force. Therefore, it was actually impossible to grind the wafer due to cracks and chips. Therefore, wafers containing good pellets that passed the diffusion process and P/W process had to be discarded.Also, the size of the stage 24 differs depending on the wafer size in order to stabilize the adsorption force and stabilize the removal from the stage after grinding. Therefore, it was necessary to change the size of the stage depending on the wafer size. Since replacing the stage requires a considerable amount of time, it is possible to provide a stage that matches the wafer size in advance, but in this case, the grinding ability is significantly reduced.
不発明はかかる問題点を解決するためになされたもので
その目的は、■切断工程の自動化、■割れ、欠はウェハ
ーの研削を可能にすること、■ウェハーサイズが変って
も容易に研削可能にすることである。The invention was made in order to solve these problems, and its purpose is to: 1) automate the cutting process, 2) make it possible to grind wafers to eliminate cracks and chips, and 2) make it possible to easily grind wafers even if the size of the wafer changes. It is to do so.
不発明の特徴は、ウェハーの表面保護テープとして硬質
フィルム上に接着剤が塗布又は貼り合わされたテープ全
使用することによって、■切断工程の自動化、■割れ、
欠はウエノ・−の切断を可能とした、■ウェハーサイズ
が変っても容易に研削可能としたことにある。The unique feature of the invention is that by using a tape made of a hard film coated with adhesive or bonded together as a wafer surface protection tape, ■ Automation of the cutting process, ■ Prevention of cracking,
The drawback lies in the ability to cut wafers and the ability to easily grind them even if the wafer size changes.
本発明の特徴は、半導体ウエノ・−上の素子形成面に接
着性樹脂が塗布又は貼シ合わされたロール状のたとえば
硬質フィルムを貼シ付けする工程と・該フィルムを所定
の大きさにたとえばプレスで切断する工程と、該フィル
ムを研削機のステージ上に吸着させウェハー裏面を研削
する工程とを具備した半導体装置の製造方法にある。The present invention is characterized by the step of pasting a roll-shaped hard film coated or laminated with an adhesive resin on the element formation surface of a semiconductor wafer; and pressing the film into a predetermined size. The method of manufacturing a semiconductor device includes a step of cutting the film with a wafer, and a step of sucking the film onto a stage of a grinding machine and grinding the back surface of the wafer.
以下不発明の実施例を図面を用いて説明する。Embodiments of the invention will be described below with reference to the drawings.
第５図（８）は半導体ウェハー１３をテープに貼シ付け
した状態を示す。テープは硬質フィルム５に接着性樹脂
５２が塗布又は貼シ合わされた構造をしておシ、離型紙
２５を介してロール状に巻かれている。貼シ付は機にて
ウニ”−１３の素子形成部全テープ側にして離型紙２５
との間に挟みローラー等で圧着して貼シ付けする。貼シ
付けられたウェハーはプレス機にて研削ステージに最適
な大きさに切断され（第５図（［３））、フィルム面を
ステージ２４側にして真空吸着させブレード３１にて所
定厚まで研削する（第５図（Ｃ））。FIG. 5(8) shows a state in which the semiconductor wafer 13 is attached to the tape. The tape has a structure in which an adhesive resin 52 is applied or bonded to a hard film 5, and the tape is wound into a roll with a release paper 25 interposed therebetween. To attach the sticker, place all the element forming parts of the sea urchin "-13 on the tape side and place the release paper 25 on the machine.
Press the adhesive with a roller or the like between the two. The pasted wafer is cut to the optimal size for the grinding stage using a press machine (Fig. 5 ([3)), and vacuum suction is performed with the film surface facing the stage 24, and the blade 31 is used to grind the wafer to a predetermined thickness. (Figure 5(C)).
不方法によれば、フィルムの腰がしっかシしているため
研削中の水圧によって第３図（Ｂ）のようなテープの巻
くれ上がシがないため切断時にプレスで研削ステージに
最適な大きさに切断できるため貼シ付は工程、切断工程
の自動化が可能とな多切断工数を下げることが可能とな
る。また割れウェハーや欠はウェハーでも第４図（ト）
）のように中央の多孔質層が露出することもなく、硬質
フィルムが完全に多孔質層をおおっているので問題なく
研削できるようになる。またウェハーサイズの違うもの
でもあらかじめ大きなウェハー丈イズに合わせて切断し
ておけば小さなウェハーサイズのものでも研削可能とな
シ、ステージ交換の工数も削減される。According to the non-method, since the film is stiff, the water pressure during grinding does not cause the tape to roll up as shown in Figure 3 (B), so when cutting, the press is used to cut the tape to the optimal size for the grinding stage. Since it can be cut at the same time, it is possible to automate the pasting process and the cutting process, thereby reducing the number of man-hours required for multiple cutting. Also, if the wafer is cracked or chipped, see Figure 4 (G).
), the central porous layer is not exposed, and the hard film completely covers the porous layer, making it possible to grind without any problems. Furthermore, if wafers of different sizes are cut in advance to match the larger wafer length, even smaller wafers can be ground, and the man-hours required for stage replacement can be reduced.
以上述べたように本発明によって切断工数の低減つェハ
ー歩留シの向上、研削工数の低減が実現された。As described above, the present invention achieves reduction in cutting man-hours, improvement in wafer yield, and reduction in grinding man-hours.
第１図は従来の研削方法でのウェハー固定方法を示す断
面図である。第２図は従来の研削方法を示す断面図であ
り、（イ）は貼り付けされた状態、ＣＢ）は切断された
状態、（Ｃ）は研削中の状態を示す。第３図、第４図は
従来方法の場合の欠陥を示す断面図であり、第３図はテ
ープがウェハーからはみ出した場合、第４図は割れ欠は
ウェハーの研削の場合を示す。第５図は本発明の実施例
による研削方法を示す断面図で、（５）は貼シ付けされ
た状態、（Ｂ）は切断された状態、（Ｃ）は研削中の状
態を示す。
図中、１１・・・・・石英板、１２・・・・・・ワック
ス、１３・・・・・・ウェハー、２１・・・・・・接着
性樹脂、２２・・・・・・軟質フィルム、２３・・・・
多孔質層、２４・・・・・・ステージ、２５・・・・・
剥離紙、３１・・・・・・ブレード、３２・・・・シリ
コンぐず、５１・・・・・・硬質フィルム、５２・・・
・・・接着性樹脂である。
〃
Ｆ！′）／ 図
？、５ Ｂ 、３／４
后 ？ 図
手続補正書輸発）
特許庁長官 殿
１、事件の表示 昭和５７年特 許願第２１３５５
２号２、発明の名称 半導体装置の製造方法３、補正
をする者
事件との関係 出 願 人東京都港区芝五
丁１」３３番１号
（４２３） 日本電気株式会社
代表者 関本忠弘
４、代理人
〒１０８ 東京都港区芝五丁目３７番８号 住人三田
ビル５、補正の対象 明細書の発明の詳細な説明の欄
６、補正の内容
（１）明細書第５頁、９行目の「硬質フィルム」を「硬
質プラスチックフィルム」と訂正いたします０FIG. 1 is a cross-sectional view showing a wafer fixing method using a conventional grinding method. FIG. 2 is a cross-sectional view showing a conventional grinding method, in which (A) shows the attached state, CB) shows the cut state, and (C) shows the state during grinding. 3 and 4 are cross-sectional views showing defects in the conventional method. FIG. 3 shows the case where the tape protrudes from the wafer, and FIG. 4 shows the case where the crack is caused by grinding the wafer. FIG. 5 is a cross-sectional view showing a grinding method according to an embodiment of the present invention, in which (5) shows a stuck state, (B) shows a cut state, and (C) shows a state during grinding. In the figure, 11...Quartz plate, 12...Wax, 13...Wafer, 21...Adhesive resin, 22...Soft film , 23...
Porous layer, 24... Stage, 25...
Release paper, 31...Blade, 32...Silicon waste, 51...Hard film, 52...
...Adhesive resin. 〃F! ')/ figure? , 5 B , after 3/4 ? (Import of figure procedure amendment) Director General of the Patent Office 1, Indication of the case 1982 Patent Application No. 21355
No. 2, No. 2, Title of the invention: Method for manufacturing semiconductor devices 3, Relationship to the amended person's case Applicant: No. 33-1 (423) 1, Shiba-go-cho, Minato-ku, Tokyo NEC Corporation Representative: Tadahiro Sekimoto 4 , Agent Address: 5-37-8 Shiba, Minato-ku, Tokyo 108 Resident Mita Building 5, Subject of amendment Column 6 of detailed explanation of the invention in the specification, Contents of amendment (1) Page 5, line 9 of the specification The "hard film" in the eyes has been corrected to "hard plastic film"0
Claims (1)
は貼夛合わされたロール状フィルムを貼シ付けする工程
と、該フィルムを所定の大きさに切断する工程と、該フ
ィルムを研削機のステージ上に吸着させウエノ・−裏面
を研削する工程を具備した半導体装置の製造方法。A process of pasting a roll-shaped film coated or laminated with an adhesive resin on the element forming surface of a semiconductor wafer, a process of cutting the film into a predetermined size, and a process of cutting the film into a grinding machine. A method for manufacturing a semiconductor device, which includes a step of adsorbing the semiconductor device on a stage and grinding the back surface of the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21355282A JPS59103342A (en) | 1982-12-06 | 1982-12-06 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21355282A JPS59103342A (en) | 1982-12-06 | 1982-12-06 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59103342A true JPS59103342A (en) | 1984-06-14 |
Family
ID=16641089
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21355282A Pending JPS59103342A (en) | 1982-12-06 | 1982-12-06 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59103342A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0182218A2 (en) * | 1984-11-07 | 1986-05-28 | Kabushiki Kaisha Toshiba | Method for dicing semiconductor wafer |
| EP0185767A1 (en) * | 1984-05-29 | 1986-07-02 | MITSUI TOATSU CHEMICALS, Inc. | Film for machining wafers |
| JPS62299034A (en) * | 1986-06-18 | 1987-12-26 | Matsushita Electronics Corp | Method of polishing semiconductor wafer |
| JPS6394630A (en) * | 1986-10-08 | 1988-04-25 | Rohm Co Ltd | Processing of rear of semiconductor wafer |
| JP2012143724A (en) * | 2011-01-13 | 2012-08-02 | Disco Corp | Resin coating apparatus |
-
1982
- 1982-12-06 JP JP21355282A patent/JPS59103342A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0185767A1 (en) * | 1984-05-29 | 1986-07-02 | MITSUI TOATSU CHEMICALS, Inc. | Film for machining wafers |
| EP0185767A4 (en) * | 1984-05-29 | 1987-09-02 | Mitsui Toatsu Chemicals | Film for machining wafers. |
| EP0182218A2 (en) * | 1984-11-07 | 1986-05-28 | Kabushiki Kaisha Toshiba | Method for dicing semiconductor wafer |
| JPS62299034A (en) * | 1986-06-18 | 1987-12-26 | Matsushita Electronics Corp | Method of polishing semiconductor wafer |
| JPS6394630A (en) * | 1986-10-08 | 1988-04-25 | Rohm Co Ltd | Processing of rear of semiconductor wafer |
| JP2012143724A (en) * | 2011-01-13 | 2012-08-02 | Disco Corp | Resin coating apparatus |
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