JPS62299034A - Method of polishing semiconductor wafer - Google Patents

Method of polishing semiconductor wafer

Info

Publication number
JPS62299034A
JPS62299034A JP14207086A JP14207086A JPS62299034A JP S62299034 A JPS62299034 A JP S62299034A JP 14207086 A JP14207086 A JP 14207086A JP 14207086 A JP14207086 A JP 14207086A JP S62299034 A JPS62299034 A JP S62299034A
Authority
JP
Japan
Prior art keywords
sheet
semiconductor wafer
resist
viscous material
holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14207086A
Other languages
Japanese (ja)
Inventor
Tomio Okamoto
岡本 富美夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP14207086A priority Critical patent/JPS62299034A/en
Publication of JPS62299034A publication Critical patent/JPS62299034A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To facilitate peeling a sheet off without applying any force to the sheet and a semiconductor wafer by a method wherein the rear surface of a semiconductor wafer is polished and the wefer is dipped in liquid in which viscous material is soluble and the sheet is peeled off when the viscous material is dissolved. CONSTITUTION:Resist is applied to the surface of a semiconductor wafer 1 as viscous material 2 and baked. Then a sheet 3 with a large number of holes 4 is applied. The sheet in which a large number of holes with diameters of, for instance, 50-500 mumphi is employed. Then, in this state, the rear surface is polished by a surface grinder or the like and the thickness of the semiconductor wafer becomes a predetermined value. As the holes provided in the sheet are minute, the vibration absorbing effect of the sheet is not degraded. Then, while the sheet is adhering, the wafer is dipped in liquid such as acetone in which the resist is soluble and subjected to an ultrasonic treatment. As the acetone reaches the resist through a large number of holes of the sheet and dissolves the resist, the sheet is peeled off naturally.

Description

【発明の詳細な説明】 3、発明の詳細な説明 産業上の利用分野 本発明は半導体ウェハーの研削方法、とくに研削後のシ
ート剥離工程の改善に関する。
DETAILED DESCRIPTION OF THE INVENTION 3. Detailed Description of the Invention Field of Industrial Application The present invention relates to a method for grinding semiconductor wafers, and in particular to an improvement in the sheet peeling process after grinding.

従来の技術 第2図を参照しながら従来の技術を説明する。Conventional technology The conventional technique will be explained with reference to FIG.

表面に素子の形成を終了した状態第2図(a) K示す
半導体ウェハー1の表面に第2図(b)に示すようにレ
ジストなどの粘性体2を塗布する。これは半導体ウェハ
ー表面の微小な凹凸を埋めるとともに、後に貼付される
シートの粘着剤が半導体ウェハー表面に直接付着するの
を避けるためである。次に第2図(C)に示すようにポ
リエチレンやポリ塩化ビニルの基材に粘着剤を塗布した
シート3を貼付する。このシートは60〜200μmの
厚さで、研削時の振動を吸収する働きを有する。次に第
2図(d)に示すように、この状態で半導体ウェハーの
裏面をサーフェスグラインダー等で所定の厚みだけ研削
を行なう。研削後、半導体ウェハーの厚みは160〜4
00μmとなっている。次に第2図(e)K示すように
手作業あるいは専用の装置を用いてシートをはがし取り
、更に、第2図(f)に示すように半導体ウェハー表面
に残った粘性体を、アセトンや発煙硝酸などで除去する
As shown in FIG. 2(b), a viscous material 2 such as a resist is applied to the surface of the semiconductor wafer 1 shown in FIG. 2(a) K after the formation of elements on the surface. This is to fill in minute irregularities on the surface of the semiconductor wafer and to prevent the adhesive of the sheet to be applied later from directly adhering to the surface of the semiconductor wafer. Next, as shown in FIG. 2(C), a sheet 3 coated with an adhesive is attached to a base material of polyethylene or polyvinyl chloride. This sheet has a thickness of 60 to 200 μm and has the function of absorbing vibrations during grinding. Next, as shown in FIG. 2(d), in this state, the back surface of the semiconductor wafer is ground to a predetermined thickness using a surface grinder or the like. After grinding, the thickness of the semiconductor wafer is 160~4
00 μm. Next, as shown in FIG. 2(e)K, the sheet is peeled off manually or using a special device, and the viscous material remaining on the semiconductor wafer surface is removed using acetone or Remove with fuming nitric acid, etc.

発明が解決しようとする問題点 以上述べた従来方法では、裏面研削が終わって薄くなっ
た半導体ウェハーの表面からシートをはがし取る際に半
導体ウェハーに大きな力(シートの幅1インチあたり5
o〜16oyりがかかり、半導体ウェハーが割れたり、
表面に形成された素子にダメージを与えたりする。また
シートが通常静電気を発生しやすい材質なので、半導体
ウェハー表面の素子が静電破壊に至るといった問題があ
った。さらに半導体ウェハーを一枚ずつ処理するのでス
ループットが低いという問題もあった。
Problems to be Solved by the Invention In the conventional method described above, when the sheet is peeled off from the surface of the semiconductor wafer which has been thinned after back grinding, a large force (50% force per inch of sheet width) is applied to the semiconductor wafer.
The semiconductor wafer may crack due to the stress of 0 to 16 oy.
This may cause damage to elements formed on the surface. Furthermore, since the sheet is usually made of a material that easily generates static electricity, there is a problem in that elements on the surface of the semiconductor wafer may be damaged by static electricity. Furthermore, since semiconductor wafers are processed one by one, there is also the problem of low throughput.

問題点を解決するための手段 前記問題点を解決するために本発明は、半導体ウェハー
の表面に粘性体を塗布し、適度に硬化させる工程と、前
記粘性体上に多数の孔を有するシートを貼布する工程と
、前記半導体ウェハーの裏面を前記半導体ウェハーが所
望の厚みになるように研削する工程と、前記粘性体の溶
液中に前記半導体基板を浸し、前記粘性体の溶解と同時
に前記シートを剥離する工程とを含む事を特徴とする半
導体ウェハーの研削方法を提供する。
Means for Solving the Problems In order to solve the above problems, the present invention includes a step of applying a viscous material to the surface of a semiconductor wafer and curing it appropriately, and a sheet having a large number of holes on the viscous material. a step of pasting the semiconductor wafer, a step of grinding the back surface of the semiconductor wafer so that the semiconductor wafer has a desired thickness, and a step of immersing the semiconductor substrate in a solution of the viscous material and simultaneously melting the viscous material and dissolving the sheet. Provided is a method for grinding a semiconductor wafer, which includes the step of peeling off the semiconductor wafer.

作   用 このような研削方法によれば半導体ウェハーの裏面研削
後、シートが貼付されたままの状態で、粘性体を溶解す
る液体中につけるとシートに設けられた多数の孔を通し
て粘性体を溶解する液が粘性体に達し、粘性体が溶解さ
れるため、シート及び半導体ウェハーに何ら力を加える
ことなくシートをはがし取ることが可能となる。
Effect: According to this grinding method, after grinding the back side of a semiconductor wafer, if the sheet is immersed in a liquid that dissolves the viscous material while it is attached, the viscous material will be dissolved through the many holes provided in the sheet. Since the liquid reaches the viscous body and dissolves the viscous body, the sheet can be peeled off without applying any force to the sheet and the semiconductor wafer.

実施例 第1図を参照しながら本発明の詳細な説明する。まず、
従来と同様に第1図(a) K示す半導体ウェハの表面
に第1図(b)に示すように粘性体2としてレジスト(
たとえば東京応化(株)製BCRンリ前 一ズ)を塗布し、100’C前後の温度で1分ゝ後のベ
ーキングを行なう。レジスト厚は1〜3μmでよい。次
に第1図(c)に示すように多数の孔4を有するシート
3を貼付する。このシートは材質は従来と同じく、たと
えば60〜200μmの厚さのポリエチレンあるいはポ
リ塩化ビニル等の基材に粘着剤を塗布したものを用いれ
ばよいが、たとえば50〜600μmφの孔が多数設け
られたものを用いる。次に第1図(cl) K示すよう
に、この状態で裏面をサーフェスグラインダー等で研削
し、半導体ウェハーを所定の厚みにする。シートに設け
られた孔は微小であるのでシートの振動吸収効果は損な
われない。次に第1図(、)に示すようにシートを貼付
した状態でレジストを溶解する液体、たとえばアセトン
の中にっけ超音波処理を行なう。
EMBODIMENT OF THE INVENTION The present invention will be described in detail with reference to FIG. first,
As before, a resist (as a viscous material 2) is applied to the surface of the semiconductor wafer shown in FIG. 1(a) K as shown in FIG. 1(b).
For example, BCR (produced by Tokyo Ohka Co., Ltd.) is applied and baked at a temperature of about 100'C for 1 minute. The resist thickness may be 1 to 3 μm. Next, as shown in FIG. 1(c), a sheet 3 having a large number of holes 4 is attached. The material of this sheet is the same as before, for example, a base material such as polyethylene or polyvinyl chloride with a thickness of 60 to 200 μm coated with an adhesive, but it may be made of a material having many holes of, for example, 50 to 600 μm in diameter. use something Next, as shown in FIG. 1 (cl) K, in this state, the back surface is ground with a surface grinder or the like to give the semiconductor wafer a predetermined thickness. Since the holes provided in the sheet are minute, the vibration absorption effect of the sheet is not impaired. Next, as shown in FIG. 1(,), with the sheet attached, it is placed in a liquid that dissolves the resist, such as acetone, and subjected to ultrasonic treatment.

アセトンがシートの多数の孔からレジストに達しレジス
トを溶解していくのでシートは自然に剥離する。
As the acetone reaches the resist through the many holes in the sheet and dissolves the resist, the sheet naturally peels off.

発明の効果 本発明の半導体ウェハーの研削方法によれば、半導体ウ
ェハーの裏面研削後、表面のシートをはがし7取る際に
シート及び半導体ウェハーに何らの力も加わらないので
半導体ウェハーが割れたり、表面の素子がダメージを受
けたりしない。またシート剥離時に静電気の発生がほと
んどないので表面の素子が静電破壊に至るおそれもない
。また複数の半導体ウェハーについてシートのはがし取
りを同時に行なうことができ作業のスループットの向上
が実現される。
Effects of the Invention According to the semiconductor wafer grinding method of the present invention, no force is applied to the sheet and the semiconductor wafer when peeling off the front sheet 7 after grinding the back surface of the semiconductor wafer. The element will not be damaged. Furthermore, since almost no static electricity is generated when the sheet is peeled off, there is no risk of electrostatic damage to the elements on the surface. In addition, sheets can be peeled off from a plurality of semiconductor wafers at the same time, resulting in improved work throughput.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜第1図(e)は本発明による半導体ウェ
ハーの研削方法の一例工程断面図、第2図(−)〜第2
図(f)は従来技術による工程断面図である。 1・・・・・・半導体ウェハー、2・・−粘性体(レジ
スト)、3・・・・シート、4・・・・孔。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名!−
−−+導本トクエハー Z−−−プrごジット生ト二伴 3−m−シート 第  1  図                 4
−、!L(eン     F■]=1=耳七で=肩七二
=−七「ゴ園■=珂七二ゴマ1=耳=〒−−七「二≧1
=耳=1− l/ −−−f−導体ヴニハー 2−fさ壬4り乞イ杢
FIG. 1(a) to FIG. 1(e) are process cross-sectional views of an example of the semiconductor wafer grinding method according to the present invention, and FIG.
Figure (f) is a sectional view of a process according to the prior art. 1... Semiconductor wafer, 2... Viscous body (resist), 3... Sheet, 4... Hole. Name of agent: Patent attorney Toshio Nakao and 1 other person! −
--+ Guidebook Tokueha Z --- Prigitte Raw Toniban 3-m-Sheet No. 1 Figure 4
-,! L(en F■] = 1 = Ears 7 = Shoulders 72 = -7 "Goen ■ = K72 Sesame 1 = Ears =〒--7" 2≧1
= ear = 1-l/ ---f-conductor vniha 2-f 4 rippai heather

Claims (1)

【特許請求の範囲】[Claims]  半導体ウェハーの表面に粘性体を塗布する工程と、前
記粘性体上に多数の孔を有するシートを貼布する工程と
、前記半導体ウェハーの裏面を前記半導体ウェハーが所
望の厚みになるように研削する工程と、前記粘性体の溶
液中に前記半導体基板を浸し、前記粘性体の溶解と同時
に前記シートを剥離する工程とを含む事を特徴とする半
導体ウェハーの研削方法。
A step of applying a viscous material to the surface of the semiconductor wafer, a step of pasting a sheet having a large number of holes on the viscous material, and a step of grinding the back surface of the semiconductor wafer so that the semiconductor wafer has a desired thickness. A method for grinding a semiconductor wafer, comprising the steps of: immersing the semiconductor substrate in a solution of the viscous material, and peeling off the sheet at the same time as the viscous material is dissolved.
JP14207086A 1986-06-18 1986-06-18 Method of polishing semiconductor wafer Pending JPS62299034A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14207086A JPS62299034A (en) 1986-06-18 1986-06-18 Method of polishing semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14207086A JPS62299034A (en) 1986-06-18 1986-06-18 Method of polishing semiconductor wafer

Publications (1)

Publication Number Publication Date
JPS62299034A true JPS62299034A (en) 1987-12-26

Family

ID=15306728

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14207086A Pending JPS62299034A (en) 1986-06-18 1986-06-18 Method of polishing semiconductor wafer

Country Status (1)

Country Link
JP (1) JPS62299034A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5414354A (en) * 1977-07-04 1979-02-02 Sansha Electric Mfg Co Ltd Equipment for controlling arc lenth in automatic direct current pulse arc welding apparatus
JPS59103342A (en) * 1982-12-06 1984-06-14 Nec Corp Manufacture of semiconductor device
JPS6110242A (en) * 1984-05-29 1986-01-17 Mitsui Toatsu Chem Inc Film for processing silicon wafer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5414354A (en) * 1977-07-04 1979-02-02 Sansha Electric Mfg Co Ltd Equipment for controlling arc lenth in automatic direct current pulse arc welding apparatus
JPS59103342A (en) * 1982-12-06 1984-06-14 Nec Corp Manufacture of semiconductor device
JPS6110242A (en) * 1984-05-29 1986-01-17 Mitsui Toatsu Chem Inc Film for processing silicon wafer

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