JPS61158145A - Processing method for semiconductor substrate - Google Patents
Processing method for semiconductor substrateInfo
- Publication number
- JPS61158145A JPS61158145A JP27872484A JP27872484A JPS61158145A JP S61158145 A JPS61158145 A JP S61158145A JP 27872484 A JP27872484 A JP 27872484A JP 27872484 A JP27872484 A JP 27872484A JP S61158145 A JPS61158145 A JP S61158145A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- supporting base
- quartz
- semiconductor substrate
- backside
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は半導体基板の加工方法に関し、特に半導体基
板の主面で能動素子または受動素子が形成されたのと反
対側主面（裏面）に対し、研摩、化学処理による鏡面化
およ５び、真空蒸着による金属膜の形成方法に用いられ
る。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for processing a semiconductor substrate, and particularly to a method for processing a semiconductor substrate on the main surface (back surface) opposite to the main surface on which active elements or passive elements are formed. , mirror polishing by polishing, chemical treatment, and metal film formation by vacuum deposition.
化合物半導体、特にＧａＡｓ結晶を用いたＧａＡｓＦＥ
Ｔは結晶技術及びプロセス技術の進歩により、各種マイ
クロ波素子及び集積回路用素子として広範囲に使用され
るに至った。しかし、これらのマイクロ波用素子は、一
般に基板の厚みを薄くする必要があり、特に大電力ＦＥ
Ｔに於いては熱抵抗の低減化を図るため、大口径基板の
裏面を加工する場合、従来、半導体基板の表面上にＦＥ
Ｔ等の素子を形成した後、基板裏面の研摩、化学処理及
び金属膜の形成の各工程に於いて、基板の割れ及び表面
側に形成されたＦＥＴ等素子のキズが発生し歩留りを大
きく低下させる問題があった。また、上記の理由により
、基板加工時に小さくし分割して加工を行なうため多大
な時間を費やす等いくつかの欠点があった。Compound semiconductors, especially GaAsFE using GaAs crystals
Due to advances in crystal technology and process technology, T has come to be widely used as various microwave devices and integrated circuit devices. However, these microwave devices generally require thinner substrates, especially for high-power FE devices.
When processing the back side of a large-diameter substrate in order to reduce thermal resistance, conventionally, FE was applied on the surface of the semiconductor substrate.
After forming elements such as T, cracks in the substrate and scratches on elements such as FET formed on the front side occur during the polishing of the back side of the substrate, chemical treatment, and formation of metal film, which greatly reduces the yield. There was a problem. Furthermore, due to the above-mentioned reasons, there have been several drawbacks, such as a large amount of time being spent since the substrate is divided into smaller pieces during processing.
以下に従来例によるＧａＡｓ基板の裏面加工方法につい
て説明する。A conventional method for processing the back surface of a GaAs substrate will be described below.
第３図（ａ）における（ｔｏＢは研摩用治具、（１０２
）はＧａＡｓ基板を接着するワックス、（１０３）はＧ
ａＡｓ基板（厚さｔ≦４００μｍ）である。まず、研摩
用治具（１０１）を加熱し、ワックス（１０，２）を融
解してＧａＡｓ基板（３）の裏面を露出せしめるように
研摩冶具（１０１）に平行に貼り付ける。貼れ付は後、
研摩材（例えばアルミナ粉末）を用いて所定の基板厚（
例えばｔ≦１００μｍ）まで研摩を行なう。研摩終了後
、研摩治具（１０１）を再加熱しＧａＡｓ基板（１０３
）を治具より剥離する６次に、第３図（ｂ）に示すよう
に石英又はシリコン支持台（１０４）を加熱してワック
ス（１０２）によってＧａＡｓ基板（１０３）を貼り付
ける。その後、ＧａＡｓ （ｌｐエツチング液（例えば
硫酸、水、過酸化水素の混合液）中で鏡面が得られる程
度にエツチングを施す。エツチング後、石英支持台（１
０４）に貼り付けたままＧａＡｓ基板を真空装置に入れ
真空蒸着により、第３図（ｃ）に示すように裏面の金属
膜（１０５）を形成する。最後に石英支持台（１０４）
を再加熱し、ＧａＡｓ基板（１０３）を剥離し、有機溶
剤で洗浄し裏面加工を終了する。In FIG. 3(a), (toB is a polishing jig, (102
) is wax for bonding the GaAs substrate, (103) is G
It is an aAs substrate (thickness t≦400 μm). First, the polishing jig (101) is heated to melt the wax (10, 2) and attached to the polishing jig (101) in parallel so as to expose the back surface of the GaAs substrate (3). Pasting is done later.
A predetermined substrate thickness (
For example, polishing is performed until t≦100 μm). After polishing, the polishing jig (101) is reheated and the GaAs substrate (103
) is peeled off from the jig.6 Next, as shown in FIG. 3(b), the quartz or silicon support base (104) is heated and the GaAs substrate (103) is attached using wax (102). After that, etching is performed in GaAs (lp etching solution (e.g., a mixture of sulfuric acid, water, and hydrogen peroxide) to the extent that a mirror surface is obtained. After etching, the quartz support (1
04), the GaAs substrate is placed in a vacuum apparatus and a metal film (105) on the back surface is formed by vacuum evaporation as shown in FIG. 3(c). Finally, the quartz support stand (104)
is reheated, the GaAs substrate (103) is peeled off, and the back surface processing is completed by cleaning with an organic solvent.
以上の工程に於いて、研摩終了後のＧａＡｓ基板（ｔ≦
ｌＯＯμｍ）は非常に割れやすいため、研摩治具がらの
剥離及び石英支持台へ貼り付ける場合にＧａＡｓ基板に
クラックや割れが生じる等の欠点がある６又、石英支持
台とＧａＡｓ基板の間に気泡が残りやすく、この状態で
真空装置に入れると、気泡の圧力によってＧａＡｓ基板
が割れる危険性が高く、製品の歩留りを著しく低下させ
る等の問題があった。In the above process, the GaAs substrate after polishing (t≦
100μm) is very easy to break, so there are drawbacks such as cracks and cracks in the GaAs substrate when peeling off the polishing jig and sticking it to the quartz support. If the GaAs substrate is placed in a vacuum device in this state, there is a high risk that the GaAs substrate will break due to the pressure of the bubbles, resulting in a significant decrease in product yield.
この発明は上記従来の問題点に鑑み半導体基板の裏面に
研摩、化学処理、及び金属膜形成の加工に半導体基板の
割れを防止する加工方法を提供する。In view of the above-mentioned conventional problems, the present invention provides a processing method that prevents cracking of a semiconductor substrate during polishing, chemical treatment, and metal film formation on the back surface of the semiconductor substrate.
この発明にかかる半導体基板の加工方法は平板状の支持
台に予め天主面間に連通した透孔を設け、これに半導体
基板をその主表面を接着剤層を介して貼着け、露出した
裏面を研摩、化学処理及び金属膜形成を支持台とともに
施すことを特徴とするものである。The method of processing a semiconductor substrate according to the present invention is to provide a flat support with a through hole that communicates between the main surfaces, attach the semiconductor substrate to the main surface through an adhesive layer, and leave the exposed back surface. It is characterized in that polishing, chemical treatment, and metal film formation are performed together with a support.
以下にこの発明の一つの実施例を図面を参照して説明す
る。An embodiment of the present invention will be described below with reference to the drawings.
従来例と同様にＧａＡｓ基板の裏面加工を行なう場合に
ついて説明する。尚各図中に記した番号は従来例と共通
にした。A case will be described in which the back surface of a GaAs substrate is processed in the same manner as in the conventional example. Note that the numbers written in each figure are the same as in the conventional example.
第１図（ａ）はＧａＡｓ基板を貼り付けるための支持台
（１）を示し、厚さ３１１Ｉ１１の石英板にその天主面
間に連通した透孔（Ｌａ、 ｌａ・・・）が形成されて
いる。Figure 1(a) shows a support base (1) for attaching a GaAs substrate, in which a quartz plate with a thickness of 311I11 is formed with through holes (La, la...) communicating between its main surfaces. There is.
第１図（ｂ）に示す様に石英支持台（１）を加熱しワッ
クス（１０２）を均一に塗布した後、ＧａＡｓ基板（１
０３）の裏面を露出する様にかつ、 ＧａＡｓ基板が
支持台と平行になる様充分圧着させる。この時にＧａＡ
ｓ基板（１０３）と石英支持台（１）の間にある気泡は
、石英支持台（１）の透孔（１ａ）を通して外部へ逃が
す事が出来る。As shown in FIG. 1(b), after heating the quartz support (1) and uniformly applying wax (102), the GaAs substrate (1) is heated.
03) is sufficiently pressed so that the back surface of the GaAs substrate is exposed and the GaAs substrate is parallel to the support base. At this time, GaA
Air bubbles between the s-substrate (103) and the quartz support (1) can escape to the outside through the through hole (1a) of the quartz support (1).
次に研摩冶Ａ （１０１）を加熱しワックス（１０２）
を均一に塗布した後前記石英支持台（１）とともにＧａ
Ａｓ基板（１０３）を貼り付ける（第１図（ｃ））、そ
の後所定の厚み（例えばｔ≦１００μｍ）まで研摩材（
例えばアルミナ粉末）を−用いて研摩する。研摩終了後
、再び研摩治具（１０１）を加熱し石英支持台（１）を
剥離する。Next, heat the polishing tool A (101) and polish the wax (102).
After uniformly applying Ga, along with the quartz support (1)
An As substrate (103) is attached (Fig. 1(c)), and then an abrasive (for example, t≦100 μm) is applied to
For example, alumina powder) is used for polishing. After polishing is completed, the polishing jig (101) is heated again to peel off the quartz support (1).
次に、ＧａＡｓのエツチング液（硫酸、水、過酸化水素
の混合液）中で鏡面が得られるまでエツチングを行ない
、続いて真空蒸着により金属膜（１０５）の形成を行な
う（第１図（ｄ））。Next, etching is performed in a GaAs etching solution (mixture of sulfuric acid, water, and hydrogen peroxide) until a mirror surface is obtained, and then a metal film (105) is formed by vacuum evaporation (Fig. 1(d) )).
最後に石英支持台（１）を加熱しＧａＡｓ基板（１０３
）を剥離し、有機溶剤処理を行ない裏面加工を終了する
。上記の方法によればＧａＡｓ基板の貼り付は及び剥離
が１回で済むとともに、ＧａＡｓ基板と石英支持台との
間に気泡が残留しないため、各工程でのＧａＡｓ基板の
クラック及び割れを防止する事が可能となり、大面積の
ＧａＡｓ基板を容易に加工する事が可能となる５又、上
記裏面加工方法の別の実施例として＋ ＧａＡｓ基板の
裏面エツチング後の時点で第２図（ａ）に示す様に、石
英支持台（１）とともにＧａＡｓ基板（１０３）上に基
板切断予定部のみを覆う様にレジスト（２）を形成する
０次に金属膜（１０５）を真空蒸着により形成し、リフ
トオフ法によりレジスト上の金属膜を除去して第２図（
ｂ）の如くする。最後に裏面のＧａＡｓ露出部より切断
する事により、半導体装置のチップ化まで、石英支持台
（１）とともに行なう事も可能である。Finally, the quartz support (1) is heated and the GaAs substrate (103
) is peeled off and treated with an organic solvent to complete the back side processing. According to the above method, the GaAs substrate only needs to be attached and peeled off once, and no air bubbles remain between the GaAs substrate and the quartz support, thereby preventing the GaAs substrate from cracking or breaking in each step. In addition, as another example of the above-mentioned back surface processing method, after etching the back surface of the GaAs substrate, as shown in FIG. 2(a), As shown, a resist (2) is formed on the GaAs substrate (103) together with the quartz support (1) so as to cover only the area where the substrate is to be cut.A metal film (105) is formed by vacuum evaporation to cover only the area where the substrate is to be cut. The metal film on the resist was removed by the method shown in Figure 2 (
Do as in b). Finally, by cutting from the GaAs exposed portion on the back surface, it is possible to make a semiconductor device into a chip together with the quartz support (1).
以上述べたようにこの発明によれば、半導体基板の裏面
加工に於いて、両主面間に開口した透孔を有する支持台
を用いる事により、基板裏面の研摩及び表面処理、裏面
金属膜の形成時に、基板のクラック、割れ及び表面のキ
ズ等を防止する半導体装置の裏面加工方法を提供できる
。As described above, according to the present invention, in processing the back surface of a semiconductor substrate, by using a support having a through hole opened between both principal surfaces, polishing and surface treatment of the back surface of the substrate, and formation of a metal film on the back surface can be performed. It is possible to provide a method for processing the back surface of a semiconductor device that prevents cracks, cracks, and scratches on the surface of the substrate during formation.
尚、前記使用例はＧａＡｓ基板の裏面加工方法について
説明したが本発明は基板の種類を特に限定するものでは
なく、各種半導体基板の裏面加工に広く適用されるもの
である。Although the above usage example describes a method for processing the back surface of a GaAs substrate, the present invention is not particularly limited to the type of substrate, and can be widely applied to processing the back surface of various semiconductor substrates.
第１図は本発明による半導体基板の裏面加工方法の実施
例にかかり１図（ａ）は石英支持台の斜視図、＠（ｂ）
〜（ｄ）は工程順に示すいずれも断面図。
第２図（ａ）、（ｂ）は別の実施例を工程順に示すいず
れも断面図、第３図（ａ）〜（Ｃ）は従来の方法を工程
順に示すいずれも断面図である。
１．１０４ −−−−一石英支持台
ｌａ、 ｌａ・・・ −一一−−石英支持台の透孔２、
−−−−−レジスト層
１０１ −−−−一研摩治具
１０２ −−−−一接着用ワックス１０３ −
−−−一半導体基板
１０５ −−一−−金属膜FIG. 1 shows an embodiment of the method for processing the back surface of a semiconductor substrate according to the present invention, and FIG. 1(a) is a perspective view of a quartz support, @(b)
- (d) are all sectional views shown in the order of steps. FIGS. 2(a) and 2(b) are sectional views showing another embodiment in the order of steps, and FIGS. 3(a) to 3(C) are sectional views showing the conventional method in the order of steps. 1.104 ----1 Quartz support la, la... -11-- Through hole 2 of the quartz support
------Resist layer 101 ---- One polishing jig 102 --- One Adhesive wax 103 -
---1 semiconductor substrate 105 ---1--metal film
Claims (1)
された該半導体基板の裏面の研摩と金属膜形成を含む裏
面加工にあたり、半導体基板の主面より大きくかつ、両
主面間に連通した透孔が設けられた平板状の支持台に接
着剤層を介して半導体基板をその主表面で貼着し、この
半導体基板の露出した裏面に研摩および化学処理を施し
鏡面化したのち、真空蒸着により金属膜を被着すること
を特徴とする半導体基板の加工方法。When performing backside processing including polishing and metal film formation on the backside of a semiconductor substrate on which an active element or a passive element is formed on the main surface side of the semiconductor substrate, a transparent material that is larger than the main surface of the semiconductor substrate and that communicates between the two main surfaces is used. The main surface of the semiconductor substrate is adhered to a flat support with holes through an adhesive layer, and the exposed back surface of the semiconductor substrate is polished and chemically treated to give it a mirror finish. A method for processing a semiconductor substrate, characterized by depositing a metal film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27872484A JPS61158145A (en) | 1984-12-28 | 1984-12-28 | Processing method for semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27872484A JPS61158145A (en) | 1984-12-28 | 1984-12-28 | Processing method for semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61158145A true JPS61158145A (en) | 1986-07-17 |
Family
ID=17601313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27872484A Pending JPS61158145A (en) | 1984-12-28 | 1984-12-28 | Processing method for semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61158145A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE112006003042T5 (en) | 2005-10-28 | 2008-09-25 | Tokyo Ohka Kogyo Co., Ltd., Kawasaki | Adhesive composition and adhesive film |
| US7459397B2 (en) | 2004-05-06 | 2008-12-02 | Opnext Japan, Inc. | Polishing method for semiconductor substrate, and polishing jig used therein |
| US7999052B2 (en) | 2006-09-07 | 2011-08-16 | Tokyo Ohka Kogyo Co., Ltd. | Process for producing an adhesive composition |
| US8088448B2 (en) | 2008-06-17 | 2012-01-03 | Tokyo Ohka Kogyo Co., Ltd. | Heat treatment method |
| US8124685B2 (en) | 2009-01-13 | 2012-02-28 | Tokyo Ohka Kogyo Co., Ltd. | Adhesive composition and film adhesive |
| US8148457B2 (en) | 2006-11-22 | 2012-04-03 | Tokyo Ohta Kogyo Co., Ltd. | Adhesive composition and film adhesive |
| US8426543B2 (en) | 2006-11-29 | 2013-04-23 | Tokyo Ohka Kogyo Co., Ltd. | Adhesive composition and adhesive film |
| US8877884B2 (en) | 2008-07-08 | 2014-11-04 | Tokyo Ohka Kogyo Co., Ltd. | Adhesive composition, film adhesive, and method for producing the adhesive composition |
-
1984
- 1984-12-28 JP JP27872484A patent/JPS61158145A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7459397B2 (en) | 2004-05-06 | 2008-12-02 | Opnext Japan, Inc. | Polishing method for semiconductor substrate, and polishing jig used therein |
| DE112006003042T5 (en) | 2005-10-28 | 2008-09-25 | Tokyo Ohka Kogyo Co., Ltd., Kawasaki | Adhesive composition and adhesive film |
| US8163836B2 (en) | 2005-10-28 | 2012-04-24 | Tokyo Ohka Kogyo Co., Ltd. | Adhesive composition and adhesive film |
| US7999052B2 (en) | 2006-09-07 | 2011-08-16 | Tokyo Ohka Kogyo Co., Ltd. | Process for producing an adhesive composition |
| US8148457B2 (en) | 2006-11-22 | 2012-04-03 | Tokyo Ohta Kogyo Co., Ltd. | Adhesive composition and film adhesive |
| US8426543B2 (en) | 2006-11-29 | 2013-04-23 | Tokyo Ohka Kogyo Co., Ltd. | Adhesive composition and adhesive film |
| US8088448B2 (en) | 2008-06-17 | 2012-01-03 | Tokyo Ohka Kogyo Co., Ltd. | Heat treatment method |
| US8901235B2 (en) | 2008-06-17 | 2014-12-02 | Tokyo Ohka Kogyo Co., Ltd. | Adhesive composition, film adhesive, and heat treatment method |
| US8901234B2 (en) | 2008-06-17 | 2014-12-02 | Tokyo Ohka Kogyo Co., Ltd. | Adhesive composition |
| US8877884B2 (en) | 2008-07-08 | 2014-11-04 | Tokyo Ohka Kogyo Co., Ltd. | Adhesive composition, film adhesive, and method for producing the adhesive composition |
| US8124685B2 (en) | 2009-01-13 | 2012-02-28 | Tokyo Ohka Kogyo Co., Ltd. | Adhesive composition and film adhesive |
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