JPH07130685A - Method of manufacturing semiconductor wafer - Google Patents

Method of manufacturing semiconductor wafer

Info

Publication number
JPH07130685A
JPH07130685A JP27652393A JP27652393A JPH07130685A JP H07130685 A JPH07130685 A JP H07130685A JP 27652393 A JP27652393 A JP 27652393A JP 27652393 A JP27652393 A JP 27652393A JP H07130685 A JPH07130685 A JP H07130685A
Authority
JP
Japan
Prior art keywords
semiconductor wafer
metal film
wafer
ground
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27652393A
Other languages
Japanese (ja)
Inventor
Noboru Goto
登 後藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP27652393A priority Critical patent/JPH07130685A/en
Publication of JPH07130685A publication Critical patent/JPH07130685A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/10155Shape being other than a cuboid
    • H01L2924/10158Shape being other than a cuboid at the passive surface

Landscapes

  • Grinding And Polishing Of Tertiary Curved Surfaces And Surfaces With Complex Shapes (AREA)
  • Weting (AREA)
  • Die Bonding (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Dicing (AREA)

Abstract

PURPOSE:To prevent a metal film from peeling off from a die by a method wherein, prior to a formation of a metal film, a reverse surface of a semiconductor wafer is ground by a grindstone to chemically etch the ground surface. CONSTITUTION:A device 5 such as IC, FET is formed on a wafer 1 according to mask patterns. An adhering surface 6 being a reverse surface of the wafer 1 is ground by a grindstone of #1000 or less, and the ground surface is finished to an irregularity 2 with a mean radius of curvature 0.1mum or more and a maximum radius about 1mum. At this time, a modified layer 3 can be formed ranging over the depth several mum by a generation of a plastic deformation or a crack due to grinding near the ground surface. The modified layer 3 generated by a grinding process is removed by chemical etching. As etching liquid, a solution of a sulfuric acid system or an ammonia system is suitable. A metal film 4 is formed on the etched wafer surface by a vapor-depositing method. Here, an adhering surface between the wafer and the metal film in increased.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、ダイを搬送しボンディ
ングするために適した半導体ダイの製造方法に関する。
FIELD OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor die suitable for transferring and bonding the die.

【0002】[0002]

【従来の技術】図4に示すように、表面にICあるいは
FET等が形成された半導体ダイ1−1をリードフレー
ムあるいはパッケージ等の被搭載物46に搬送して半
田、金あるいは樹脂等の接合剤により装着する集積回路
のダイボンディング工程において、テープ41上に固着
されたダイの供給、移送はダイ1−1を吸着するための
中心孔44−1を有するコレット44によって行ってい
る。ところで、上記ダイ1−1の裏面には金属膜4を設
けることによってダイ1−1と被搭載物46との接着性
を高めている。
2. Description of the Related Art As shown in FIG. 4, a semiconductor die 1-1 having an IC or FET or the like formed on its surface is conveyed to an object to be mounted 46 such as a lead frame or a package to bond solder, gold, resin or the like. In the die bonding process of the integrated circuit mounted by the agent, the die fixed on the tape 41 is supplied and transferred by the collet 44 having the central hole 44-1 for adsorbing the die 1-1. By the way, by providing the metal film 4 on the back surface of the die 1-1, the adhesiveness between the die 1-1 and the mounted object 46 is enhanced.

【0003】[0003]

【発明が解決しようとする課題】このような方法によっ
てダイ1−1を被搭載物46に搬送するため、ダイをテ
ープ41の下から針42で突き上げてコレット44に吸
着させる際に、金属膜4がダイ1−1から剥離すること
がある。かかる場合はダイと被搭載物との接合が不十分
となり、信頼性が低下するという問題があった。そこで
本発明は、かかる問題点を解決した半導体ダイの製造方
法を提供することを目的とする。
In order to convey the die 1-1 to the object to be mounted 46 by such a method, when the die 42 is pushed up from below the tape 41 by the needle 42 to be attracted to the collet 44, a metal film is formed. 4 may peel from the die 1-1. In such a case, there is a problem in that the die and the object to be mounted are not sufficiently joined and the reliability is lowered. Therefore, it is an object of the present invention to provide a method for manufacturing a semiconductor die that solves the above problems.

【0004】[0004]

【課題を解決するための手段】本発明にかかる半導体ウ
ェーハの製造方法は、ダイシングテープに付着される半
導体ウェーハの表面に各種半導体デバイスを形成し、そ
の裏面に金属膜を形成する半導体ウェーハの製造方法に
おいて、前記金属膜を形成するに先立って、半導体ウェ
ーハの裏面を砥石によって研削する工程と、研削された
面を化学エッチングする工程とを付加することを特徴と
する。
A method for manufacturing a semiconductor wafer according to the present invention is a method for manufacturing a semiconductor wafer in which various semiconductor devices are formed on the front surface of a semiconductor wafer attached to a dicing tape and a metal film is formed on the rear surface thereof. In the method, a step of grinding the back surface of the semiconductor wafer with a grindstone and a step of chemically etching the ground surface are added prior to forming the metal film.

【0005】上記の方法において、半導体ウェーハの裏
面を#1000以下の砥石を用いて平均曲率半径が0.
1μm以上、最大半径1μm程度の凹凸を有する面に研
削すること、研削された面を硫酸系エッチング液、ある
いはアンモニア系エッチング液によって略5μm除去す
ること、エッチングされた面の上に蒸着法により100
0Å以上の金属膜を形成すること、あるいは、エッチン
グされた面の上にTiの薄膜を形成し、その上にAuの
薄膜を形成することが好適である。
In the above method, the average radius of curvature of the back surface of the semiconductor wafer is less than 0.
Grinding to a surface having an unevenness of 1 μm or more and a maximum radius of about 1 μm, removing the ground surface by about 5 μm with a sulfuric acid-based etching solution or an ammonia-based etching solution, and depositing 100
It is preferable to form a metal film of 0 Å or more, or to form a thin film of Ti on the etched surface and then form a thin film of Au on it.

【0006】[0006]

【作用】上記の構成によれば、本発明にかかる方法は半
導体ウェーハの裏面が平均曲率半径で0.1μm以上、
最大半径が1μm程度の凹凸を設け、その上に金属膜を
施すのでウェーハと金属膜との接着面が大きくなり、荒
れ肌状となるので接着力が増大してダイボンディングの
信頼性が向上する。また、加工することによって生じる
変質層を除去するので剪断強度が劣化することが無い。
According to the above construction, the method according to the present invention is characterized in that the back surface of the semiconductor wafer has an average radius of curvature of 0.1 μm or more,
Since the unevenness having the maximum radius of about 1 μm is provided and the metal film is applied on the unevenness, the adhesion surface between the wafer and the metal film becomes large, and the surface becomes rough, so that the adhesive force is increased and the reliability of die bonding is improved. Further, since the deteriorated layer generated by processing is removed, the shear strength does not deteriorate.

【0007】上記の凹凸面をさらに細かくすると接着力
の効果が減少して好ましくない。加工歪の生じている変
質層を除去するためには化学エッチングによる方法が好
適である。凹凸の平均曲率半径が0.1μm以上あるの
で全面を金属膜で覆うためにはその厚さは0.1μm以
上必要である。Tiはウェーハと、またAuはダイボン
ドに使用するAuSn,AuSi等の接合剤とそれぞれ
密着性が良いので、エッチングされたウェーハ面上にT
iの薄膜、その上にAuの薄膜を施こすことが相互の接
着性を増大するために好適である。
If the uneven surface is made finer, the effect of the adhesive force is reduced, which is not preferable. A method using chemical etching is suitable for removing the deteriorated layer in which processing strain has occurred. Since the average radius of curvature of the unevenness is 0.1 μm or more, the thickness thereof must be 0.1 μm or more to cover the entire surface with the metal film. Since Ti has a good adhesiveness with the wafer and Au has a good adhesiveness with the bonding agent such as AuSn or AuSi used for die-bonding, it is possible to obtain T on the etched wafer surface.
It is preferable to apply a thin film of i and a thin film of Au on it in order to increase mutual adhesiveness.

【0008】[0008]

【実施例】以下、添付図面を参照して本発明の実施例を
説明する。なお、図面の説明において同一要素には同一
符号を付し、重複する説明を省略する。
Embodiments of the present invention will be described below with reference to the accompanying drawings. In the description of the drawings, the same elements will be denoted by the same reference symbols, without redundant description.

【0009】図1は本実施例の製法によって形成された
半導体ウェーハを示す断面図である。同図(a)は直径
3インチあるいは5インチのGaAsウェーハ1の上に
2mm〜10mmの大きさの中にIC,FET等のデ
バイス5がマスタパターンに従って形成され、裏面6は
本来のGaAsの状態である。
FIG. 1 is a sectional view showing a semiconductor wafer formed by the manufacturing method of this embodiment. FIG (a) the IC in the size of 2mm b ~10mm b on the GaAs wafer 1 of a diameter of 3 inches or 5 inches, the device 5 such as a FET formed in accordance with the master pattern, the back surface 6 original GaAs Is the state of.

【0010】図1(b)はGaAsウェーハ1の付着面
6を♯1000以下の砥石によって研削し、研削面を平
均曲率半径0.1μm以上、最大半径1μm程度の凹凸
2に仕上げる。この時、研削された面の近傍は研削によ
る塑性変形あるいはクラックの発生により深さ数μmに
わたって変質層3ができる。
In FIG. 1 (b), the adhering surface 6 of the GaAs wafer 1 is ground with a grindstone of # 1000 or less, and the ground surface is finished to have irregularities 2 having an average radius of curvature of 0.1 μm or more and a maximum radius of about 1 μm. At this time, an altered layer 3 is formed in the vicinity of the ground surface over a depth of several μm due to plastic deformation or cracking generated by grinding.

【0011】図2(a)は研削装置の構成を示す断面
図、同図(b)は平面図であり、矢印24の方向に回転
するチャック23に吸着されたウェーハ1が矢印25の
方向に回転しながら26の垂直方向に移動する円盤状の
砥石21であり、この砥石21によってウェーハ1の裏
面6を研削するウェーハ自転ダウンフィード方式の装置
である。研削中は発熱し、屑粉が発生するので冷却水が
吹き付けられ、研削が完了するとN2ガス等の乾燥用気
体を吹き付けて水分を除去する。
FIG. 2 (a) is a sectional view showing the structure of the grinding apparatus, and FIG. 2 (b) is a plan view showing that the wafer 1 attracted by the chuck 23 rotating in the direction of arrow 24 is in the direction of arrow 25. This is a disk-shaped grindstone 21 that moves in the vertical direction 26 while rotating, and is a wafer rotation down-feed type device that grinds the back surface 6 of the wafer 1 by this grindstone 21. During grinding, heat is generated and waste powder is generated, so cooling water is sprayed. When grinding is completed, a drying gas such as N 2 gas is sprayed to remove water.

【0012】図1(c)は研削加工して生じた変質層3
を化学エッチングによって除去した状態を示す。加工歪
を起こした変質層3があるとこの部分から割れやすく、
剪断強度が劣化するからである。変質層3はエッチング
液に浸せきして除去する。エッチング液あ硫酸系(H2
SO4+H22+H2O)、あるいはアンモニア系(NH
4OH+H22+H2O)の溶液が適している。これらの
溶液を用いた場合、エッチング速度は略1μm/min
であり、略5分で変質層を除去できる。
FIG. 1 (c) shows an altered layer 3 formed by grinding.
The figure shows a state in which is removed by chemical etching. If there is a deteriorated layer 3 that causes processing strain, it is easy to crack from this part,
This is because the shear strength deteriorates. The altered layer 3 is removed by immersing it in an etching solution. Etching solution, sulfuric acid system (H 2
SO 4 + H 2 O 2 + H 2 O) or ammonia system (NH
A solution of 4 OH + H 2 O 2 + H 2 O) is suitable. When these solutions are used, the etching rate is about 1 μm / min.
The deteriorated layer can be removed in about 5 minutes.

【0013】図1(d)はエッチングされたウェーハ面
上に蒸着法によって金属膜4を形成した状態を示す。図
3は真空蒸着法により薄膜を形成する方法の説明図であ
る。半導体ウェーハ1を保持するホルダ33、金属蒸気
の通路を開閉するシャッタ32及びるつぼ34は真空容
器31の中に設置され、排気は図示していないロータリ
ーポンプ及び油拡散ポンプによって行う。るつぼ34に
Auの粉末grを入れ、直径3インチのGaAsウェー
ハ1をホルダ33に設置し、容器31内は1×10-6
orrまで排気した。シャッタ32は開放してるつぼ3
4に内蔵したヒータに通電して加熱しAuを蒸発した。
蒸着する面には平均半径が略0.1μmの凹凸を有する
ので全面を金で覆うため膜4の厚さは1000Å以上必
要である。
FIG. 1D shows a state in which a metal film 4 is formed on the etched wafer surface by a vapor deposition method. FIG. 3 is an explanatory diagram of a method of forming a thin film by a vacuum vapor deposition method. A holder 33 that holds the semiconductor wafer 1, a shutter 32 that opens and closes a passage of metal vapor, and a crucible 34 are installed in a vacuum container 31, and exhaust is performed by a rotary pump and an oil diffusion pump (not shown). Au powder gr was put in the crucible 34, the GaAs wafer 1 having a diameter of 3 inches was placed in the holder 33, and the inside of the container 31 was 1 × 10 −6 T.
Exhausted to orr. Shutter 32 is open crucible 3
The heater built in No. 4 was energized and heated to evaporate Au.
Since the surface to be vapor-deposited has irregularities with an average radius of approximately 0.1 μm, the thickness of the film 4 must be 1000 Å or more to cover the entire surface with gold.

【0014】図1(e)はエッチングされたウェーハ面
上にTiの金属膜4−1、その上にAuの金属膜4−2
を施した状態を示す。Tiはウェーハと、また、Auは
ダイボンドに使用するAuSn,AuSi等の接合剤と
それぞれ密着性が良いからである。
FIG. 1E shows a Ti metal film 4-1 on the etched wafer surface, and an Au metal film 4-2 thereon.
It shows the state of applying. This is because Ti has good adhesiveness to the wafer, and Au has good adhesiveness to the bonding agent such as AuSn or AuSi used for die bonding.

【0015】[0015]

【発明の効果】以上説明したように、本発明によれば、
半導体ウェーハの裏面が平均曲率半径で0.1μm以
上、最大半径が1μm程度の凹凸を設け、その上に金属
膜を施すのでウェーハと金属膜との接着面が大きくな
り、荒れ肌状となるので接着力が増大してダイボンディ
ングの信頼性が向上する。また、加工することによって
生じる変質層を除去するので剪断強度が劣化することが
無い。
As described above, according to the present invention,
Since the back surface of the semiconductor wafer has unevenness with an average radius of curvature of 0.1 μm or more and a maximum radius of about 1 μm, and a metal film is applied on it, the bonding surface between the wafer and the metal film becomes large, resulting in rough skin-like bonding. The force is increased and the reliability of die bonding is improved. Further, since the deteriorated layer generated by processing is removed, the shear strength does not deteriorate.

【図面の簡単な説明】[Brief description of drawings]

【図1】本実施例の製法によって形成された工程別の半
導体ウェーハを示す断面図である。
FIG. 1 is a cross-sectional view showing a semiconductor wafer in each step, which is formed by a manufacturing method of this embodiment.

【図2】本実施例の製法に適用される研削装置の構成を
示す断面図(a)、及び平面図(b)である
FIG. 2 is a cross-sectional view (a) and a plan view (b) showing a configuration of a grinding device applied to the manufacturing method of the present embodiment.

【図3】本実施例の製法に適用される真空蒸着法の説明
図である。
FIG. 3 is an explanatory diagram of a vacuum vapor deposition method applied to the manufacturing method of the present embodiment.

【図4】従来のダイボンディング方法の構成を示す概略
図である。
FIG. 4 is a schematic diagram showing a configuration of a conventional die bonding method.

【符号の説明】[Explanation of symbols]

1:半導体ウェーハ 1−1:ダイ 2:凹凸 3:変質層 4、4′:金属膜 5:半導体デバイス 6:裏面 21:砥石 22:砥石台 23:チャック 24、25、26:矢印 31:真空容器 32:シャッタ 33:ホルダ 34:るつぼ 41:ダイシングテープ 44:コレット 46:被搭載物 1: Semiconductor wafer 1-1: Die 2: Concavo-convex 3: Altered layer 4, 4 ': Metal film 5: Semiconductor device 6: Back surface 21: Grindstone 22: Grindstone stand 23: Chuck 24, 25, 26: Arrow 31: Vacuum Container 32: Shutter 33: Holder 34: Crucible 41: Dicing tape 44: Collet 46: Mounted object

フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/52 C 21/301 Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI Technical display location H01L 21/52 C 21/301

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 ダイシングテープに付着される半導体ウ
ェーハの表面に各種半導体デバイスを形成し、その裏面
に金属膜を形成する半導体ウェーハの製造方法におい
て、 前記金属膜を形成するに先立って、半導体ウェーハの裏
面を砥石によって研削する工程と、研削された面を化学
エッチングする工程とを付加することを特徴とする半導
体ウェーハの製造方法。
1. A method of manufacturing a semiconductor wafer, wherein various semiconductor devices are formed on the front surface of a semiconductor wafer attached to a dicing tape, and a metal film is formed on the back surface thereof. Prior to forming the metal film, the semiconductor wafer is formed. And a step of chemically etching the ground surface of the semiconductor wafer.
【請求項2】 半導体ウェーハの裏面を#1000以下
の砥石を用いて平均曲率半径が0.1μm以上、最大半
径1μm程度の凹凸を有する面に研削することを特徴と
する請求項1に記載の半導体ウェーハの製造方法。
2. The back surface of a semiconductor wafer is ground to a surface having irregularities with an average radius of curvature of 0.1 μm or more and a maximum radius of about 1 μm by using a grindstone of # 1000 or less. Manufacturing method of semiconductor wafer.
【請求項3】 研削された面を硫酸系エッチング液、あ
るいはアンモニア系エッチング液によって略5μm除去
することを特徴とする請求項1に記載の半導体ウェーハ
の製造方法。
3. The method for producing a semiconductor wafer according to claim 1, wherein the ground surface is removed by about 5 μm with a sulfuric acid-based etching solution or an ammonia-based etching solution.
【請求項4】 エッチングされた面の上に蒸着法により
1000Å以上の金属膜を形成することを特徴とする請
求項1に記載の半導体ウェーハの製造方法。
4. The method of manufacturing a semiconductor wafer according to claim 1, wherein a metal film having a thickness of 1000 Å or more is formed on the etched surface by a vapor deposition method.
【請求項5】 エッチングされた面の上にTiの薄膜を
形成し、その上にAuの薄膜を形成することを特徴とす
る請求項1又は4に記載の半導体ウェーハの製造方法。
5. The method for manufacturing a semiconductor wafer according to claim 1, wherein a thin film of Ti is formed on the etched surface, and a thin film of Au is formed thereon.
JP27652393A 1993-11-05 1993-11-05 Method of manufacturing semiconductor wafer Pending JPH07130685A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27652393A JPH07130685A (en) 1993-11-05 1993-11-05 Method of manufacturing semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27652393A JPH07130685A (en) 1993-11-05 1993-11-05 Method of manufacturing semiconductor wafer

Publications (1)

Publication Number Publication Date
JPH07130685A true JPH07130685A (en) 1995-05-19

Family

ID=17570666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27652393A Pending JPH07130685A (en) 1993-11-05 1993-11-05 Method of manufacturing semiconductor wafer

Country Status (1)

Country Link
JP (1) JPH07130685A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030079560A (en) * 2002-04-04 2003-10-10 이성민 Semiconductor wafer on which FRP is coated and semiconductor chip using the same, and fabricating method thereof
JP2007528601A (en) * 2004-03-09 2007-10-11 インフィネオン テクノロジーズ アクチエンゲゼルシャフト Reliable, cost effective and thermally strong AuSn die attach technology
JP2015216242A (en) * 2014-05-12 2015-12-03 新日本無線株式会社 Semiconductor device
CN105590834A (en) * 2014-11-11 2016-05-18 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacturing method thereof, and electronic apparatus

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030079560A (en) * 2002-04-04 2003-10-10 이성민 Semiconductor wafer on which FRP is coated and semiconductor chip using the same, and fabricating method thereof
JP2007528601A (en) * 2004-03-09 2007-10-11 インフィネオン テクノロジーズ アクチエンゲゼルシャフト Reliable, cost effective and thermally strong AuSn die attach technology
JP4700681B2 (en) * 2004-03-09 2011-06-15 インフィネオン テクノロジーズ アクチエンゲゼルシャフト Si circuit die, method of manufacturing Si circuit die, method of attaching Si circuit die to heat sink, circuit package and power module
JP2015216242A (en) * 2014-05-12 2015-12-03 新日本無線株式会社 Semiconductor device
CN105590834A (en) * 2014-11-11 2016-05-18 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacturing method thereof, and electronic apparatus

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