JP3216583B2 - Manufacturing method of bonded SOI substrate - Google Patents
Manufacturing method of bonded SOI substrateInfo
- Publication number
- JP3216583B2 JP3216583B2 JP22627797A JP22627797A JP3216583B2 JP 3216583 B2 JP3216583 B2 JP 3216583B2 JP 22627797 A JP22627797 A JP 22627797A JP 22627797 A JP22627797 A JP 22627797A JP 3216583 B2 JP3216583 B2 JP 3216583B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- wafer
- bonded
- wax
- grinding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
Description
【0001】[0001]
【発明の属する技術分野】本発明は、第1の半導体ウエ
ーハと第2の半導体ウエーハの間に誘電体層を介在させ
て貼り合わせ接着される貼り合わせSOI基板の製造方
法と、これに用いる保護剤塗布装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a bonded SOI substrate, which is bonded and bonded with a dielectric layer interposed between a first semiconductor wafer and a second semiconductor wafer, and a protection method used for the bonded SOI substrate. The present invention relates to an agent application device.
【0002】[0002]
【従来の技術】従来において、第1の半導体ウエーハと
第2の半導体ウエーハの間に誘電体層を介在させて貼り
合わせて形成されるSOI(Silicon on Insulator)基
板が知られている。貼り合わせSOI基板の製造におい
て、支持基板となる第1の半導体ウエーハと素子形成層
となる第2の半導体ウエーハの誘電体層を介在させて貼
り合わせ、貼り合わせ半導体ウエーハを形成した後、前
記第2の半導体ウエーハの所定の厚さまで薄膜化する製
造方法が知られている。2. Description of the Related Art Conventionally, there has been known an SOI (Silicon on Insulator) substrate formed by bonding a first semiconductor wafer and a second semiconductor wafer with a dielectric layer interposed therebetween. In the production of a bonded SOI substrate, the first semiconductor wafer serving as a support substrate and the second semiconductor wafer serving as an element forming layer are bonded with a dielectric layer interposed therebetween to form a bonded semiconductor wafer. 2. Description of the Related Art A manufacturing method for reducing the thickness of a second semiconductor wafer to a predetermined thickness is known.
【0003】例えば、図5に示すように、半導体ウエー
ハ1,2の一方に誘電体層5を形成し(図5(1)参
照)、これらの半導体ウエーハ1,2のその鏡面同士を
接合させて、接着ウエーハ3を形成する(図5(2)参
照)。接着後の酸化性雰囲気中での熱処理によって接着
を強固にするとともに外周に酸化膜6を形成する(図5
(3)参照)。For example, as shown in FIG. 5, a dielectric layer 5 is formed on one of semiconductor wafers 1 and 2 (see FIG. 5A), and the mirror surfaces of these semiconductor wafers 1 and 2 are joined together. Thus, an adhesive wafer 3 is formed (see FIG. 5B). Bonding is strengthened by heat treatment in an oxidizing atmosphere after bonding, and an oxide film 6 is formed on the outer periphery.
(3)).
【0004】この種の半導体ウエーハは、鏡面加工時に
ウエーハ周縁部にダレが発生しており、このダレ等によ
って貼り合わせ接着された接着ウエーハ3の周縁部には
隙間が生じて未接着部が発生する。このような未接着部
は、貼り合わせウエーハを形成する後の工程で、素子形
成層となるウエーハを数μmに薄くする際に、剥がれて
飛散し、その一部が表面に付着して加工時に傷をつけた
り、また、素子形成時のパターン切れの原因にもなった
りするおそれがあるため、あらかじめ除去しておく必要
があった。In this type of semiconductor wafer, sagging occurs at the peripheral edge of the wafer during mirror polishing, and a gap occurs at the peripheral edge of the bonded wafer 3 bonded and bonded due to the sagging, and an unbonded portion is generated. I do. Such a non-adhered portion is peeled and scattered when a wafer to be an element forming layer is thinned to several μm in a process after forming a bonded wafer, and a part of the unadhered portion adheres to the surface and is processed during processing. It is necessary to remove them beforehand because they may cause damage or cause pattern breakage during element formation.
【0005】このため、前記接着ウエーハ3の周縁部に
発生する未接着部を除去する。この場合は、半導体ウエ
ーハ1と半導体ウエーハ2の未接着となる部分を含む領
域を、厚さ方向に接着界面の直前まで研削し、(図5
(4)参照)、アルカリ性のエッチング液(KOH水溶
液)等を使用したエッチングにより研削部8を除去する
(図5(5)参照)。尚、10はエッチング後の研削部
である。[0005] For this reason, unbonded portions generated at the peripheral portion of the bonded wafer 3 are removed. In this case, the region including the unbonded portion between the semiconductor wafer 1 and the semiconductor wafer 2 is ground in the thickness direction until just before the bonding interface (FIG. 5).
(See (4)), the grinding portion 8 is removed by etching using an alkaline etching solution (KOH aqueous solution) or the like (see FIG. 5 (5)). In addition, 10 is a grinding part after etching.
【0006】その後、フッ化水素水等により、酸化膜6
を除去し(図5(6)参照)、素子形成層の研削(図5
(7)参照)、鏡面仕上げを等を行い(図5(8)参
照)、貼り合わせSOI基板を形成する。After that, the oxide film 6 is formed with a hydrogen fluoride solution or the like.
Is removed (see FIG. 5 (6)), and the element forming layer is ground (FIG. 5
(See (7)), mirror finishing is performed (see FIG. 5 (8)), and a bonded SOI substrate is formed.
【0007】[0007]
【発明が解決しようとする課題】しかし、貼り合わせS
OIウエーハを形成する工程で、接着ウエーハの周縁部
の未接着部を除去する際に、研削時のダイヤモンドブレ
ード等の砥石から加わる力によって、接着ウエーハを形
成する第1の半導体ウエーハ又は第2の半導体ウエーハ
が大きく割れたり、端が欠けたりする場合があり、良品
率が悪くなるという不都合を生じていた。However, the bonding S
In the step of forming the OI wafer, the first semiconductor wafer or the second semiconductor wafer forming the bonded wafer is formed by a force applied from a grindstone such as a diamond blade at the time of grinding when removing an unbonded portion at the peripheral edge of the bonded wafer. In some cases, the semiconductor wafer may be severely cracked or the edges may be chipped, resulting in an inconvenience that the yield is reduced.
【0008】例えば、図4(a)及び図4(b)に示す
ように、第1及び第2の半導体ウエーハを貼り合わせた
接着ウエーハ3の周縁部の未接着部を研削する際に、砥
石18から研削研磨時に未接着部に直接に力が加わり、
力方向に沿って接着ウエーハ3の縁部が大きく割れたり
欠けたりする場合があった(図中矢印は、力の加わる方
向を示す)。For example, as shown in FIGS. 4 (a) and 4 (b), a grindstone is used to grind an unbonded portion of the peripheral portion of the bonded wafer 3 on which the first and second semiconductor wafers are bonded. From 18 a force is directly applied to the unbonded part during grinding and polishing,
In some cases, the edge of the bonded wafer 3 was severely cracked or chipped along the direction of the force (the arrow in the figure indicates the direction in which the force was applied).
【0009】また、研削時によって生じたウエーハの破
片等のパーティクルが、接着ウエーハに介在する誘電体
層に飛散し、誘電体層である埋め込み酸化膜が傷ついて
しまうことがあった。このように酸化膜に傷がついてし
まうと、その後のエッチング時に前記傷が選択的にエッ
チングされてエッチピットが発生し、製品不良となって
いた。Further, particles such as wafer fragments generated by grinding may be scattered to the dielectric layer interposed between the bonded wafers, and the embedded oxide film as the dielectric layer may be damaged. If the oxide film is scratched in this way, the scratch is selectively etched at the time of subsequent etching, and an etch pit is generated, resulting in a defective product.
【0010】そこで、本発明は前記問題点を解決するた
めに、第1の半導体ウエーハ及び第2の半導体ウエーハ
を貼り合わせて接着した後、前記接着ウエーハの周縁部
位をワックス等によって保護することにより、接着ウエ
ーハの縁部研削時に生じる割れや欠け等の発生を防止
し、また、飛散したパーティクル等によって埋め込み酸
化膜が傷つくのを防いで、良品率を向上することを可能
とした貼り合わせSOI基板の製造方法と、これに用い
る保護剤塗布装置を提供することを目的としている。Therefore, the present invention solves the above-mentioned problems by bonding and bonding a first semiconductor wafer and a second semiconductor wafer, and protecting the peripheral portion of the bonded wafer with wax or the like. A bonded SOI substrate that can prevent cracks and chips from occurring during edge grinding of the bonded wafer, and also prevents buried oxide films from being damaged by scattered particles and the like, thereby improving the yield rate. It is an object of the present invention to provide a method for producing the same and a protective agent applying device used for the method.
【0011】[0011]
【課題を解決するための手段】 本発明に係るSOI基
板の製造方法は、第1の半導体ウエーハ及び第2の半導
体ウエーハの一方もしくは双方に誘電体層を有すると共
に、これら半導体ウエーハの鏡面同士を密着させ酸化性
雰囲気中で熱処理により接着する工程と、前記第1の半
導体ウエーハの周縁部に発生する未接着となる部分を含
む領域を、前記第2の半導体ウエーハにダメージが達し
ない厚みまで研削する工程とを備え、前記第1の半導体
ウエーハの周縁部を研削する際に、第1の半導体ウエー
ハ及び第2の半導体ウエーハの周辺部に保護材を塗布す
ることによって接着された前記半導体ウエーハを保護
し、研削時のウェーハの割れや欠け等の発生を防止した
構成の貼り合わせSOI基板の製造方法である。According to a method for manufacturing an SOI substrate according to the present invention, a dielectric layer is provided on one or both of a first semiconductor wafer and a second semiconductor wafer, and mirror surfaces of these semiconductor wafers are connected to each other. a step of adhesion is caused to adhere by heat treatment in an oxidizing atmosphere, the unbonded portion serving generated in the peripheral portion of the first semiconductor wafer including
Grinding a region to be damaged to a thickness at which the second semiconductor wafer is not damaged. When grinding the peripheral portion of the first semiconductor wafer, the first semiconductor wafer and the second semiconductor wafer are ground. A method of manufacturing a bonded SOI substrate having a configuration in which the semiconductor wafer bonded by applying a protective material to a peripheral portion of the substrate is protected, and cracking, chipping, and the like of the wafer during grinding are prevented.
【0012】このように、第1の半導体ウエーハと第2
の半導体ウエーハを貼り合わせた後、第1及び第2の半
導体ウエーハの周縁部にワックス等の保護剤を塗布する
と、前記保護剤が緩衝材となって、研削研磨時に半導体
ウエーハに加わる力が分散し、半導体ウエーハの割れや
欠けを防止し、良品率を向上することができる。Thus, the first semiconductor wafer and the second semiconductor wafer
When a protective agent such as wax is applied to the peripheral portions of the first and second semiconductor wafers after bonding the semiconductor wafers, the protective agent serves as a buffer, and the force applied to the semiconductor wafers during grinding and polishing is dispersed. In addition, cracking and chipping of the semiconductor wafer can be prevented, and the yield can be improved.
【0013】また、第1の半導体ウエーハ及び第2の半
導体ウエーハの周縁部位は、ワックス等の保護剤が塗布
されているため、第1及び第2の半導体ウエーハの間に
介在する埋め込み酸化膜に研削研磨時に発生したパーテ
ィクル等が入り込むのを防止することができ、更に、良
品率を向上させることができる。Further, since a protective agent such as wax is applied to the peripheral portions of the first semiconductor wafer and the second semiconductor wafer, the peripheral portions of the first semiconductor wafer and the second semiconductor wafer are filled with a buried oxide film interposed between the first and second semiconductor wafers. Particles and the like generated during grinding and polishing can be prevented from entering, and the yield rate can be further improved.
【0014】[0014]
【0015】[0015]
【0016】[0016]
【発明の実施の形態】以下、本発明を詳細に説明する。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail.
【0017】図1は本発明に係る貼り合わせ基板の製造
方法を示す工程図である。FIG. 1 is a process chart showing a method for manufacturing a bonded substrate according to the present invention.
【0018】本発明に係る貼り合わせ基板の製造方法に
ついて、図1の製造方法を示す工程図に基づいて説明す
る。A method of manufacturing a bonded substrate according to the present invention will be described with reference to a process chart showing the manufacturing method of FIG.
【0019】図1に示すように、半導体ウエーハ1,2
は、鏡面加工等を施して所定形状に形成した後(図1
(1)参照)、半導体ウエーハ1,2のどちらか一方、
本例においては、第1の半導体ウエーハに埋め込み酸化
膜となる誘電体層5を形成する(図1(2)参照)。次
に、これらの半導体ウエーハ1,2をその鏡面同士を接
合させて、接着ウエーハ3を形成する(図1(3)参
照)。そして、接着後に熱処理(例えば1,100℃×
2Hr)によって接着ウエーハ3の外周に酸化膜6を形
成する(図1(4)参照)。As shown in FIG. 1, semiconductor wafers 1 and 2
Is formed into a predetermined shape by mirror finishing or the like (see FIG. 1).
(1)), one of the semiconductor wafers 1 and 2,
In this example, a dielectric layer 5 serving as a buried oxide film is formed on a first semiconductor wafer (see FIG. 1 (2)). Next, these semiconductor wafers 1 and 2 are bonded together with their mirror surfaces to form an adhesive wafer 3 (see FIG. 1 (3)). Then, after bonding, heat treatment (for example, 1,100 ° C. ×
2Hr) to form an oxide film 6 on the outer periphery of the bonding wafer 3 (see FIG. 1 (4)).
【0020】その後、接着ウエーハ3の周縁部位に後述
する方法で保護剤たるワックス7を塗布し、接着ウエー
ハ3を保護する(図1(5)参照)。Thereafter, a wax 7 serving as a protective agent is applied to the peripheral portion of the bonding wafer 3 by a method described later to protect the bonding wafer 3 (see FIG. 1 (5)).
【0021】このように、ワックス7が接着ウエーハ3
の周縁部位に塗布されていると、研削時に半導体ウエー
ハ1,2に加わる力の緩衝材となり、半導体ウエーハ
1,2の割れや欠けの発生を防止することが可能とな
る。また、接着ウエーハ3の周縁部位はワックス7で保
護されているため、半導体ウエーハ1,2間の誘電体層
5中に研削時に生じたパーティクル等が入り込むのを防
止することができ、誘電体層5及び酸化膜6を傷つける
ことなく研削が行える。As described above, the wax 7 is bonded to the bonding wafer 3
Is applied to the peripheral portions of the semiconductor wafers 1 and 2 and serves as a cushioning material for the force applied to the semiconductor wafers 1 and 2 during grinding, thereby preventing the semiconductor wafers 1 and 2 from being cracked or chipped. Further, since the peripheral portion of the bonding wafer 3 is protected by the wax 7, it is possible to prevent particles or the like generated during grinding from entering the dielectric layer 5 between the semiconductor wafers 1 and 2. Grinding can be performed without damaging the oxide film 5 and the oxide film 6.
【0022】その後、前記ワックス7ごと接着ウエーハ
3の外周部に発生した未接部を除去する。また、研削
後、溶剤等によって周縁部に塗布したワックス7を除去
する。この場合は、半導体ウエーハ1と半導体ウエーハ
2の未接着となる部分を含む領域を、厚さ方向に接着界
面の直前(約50μm手前)まで研削する(図1(6)
参照)。Thereafter, the non-contact portion generated on the outer peripheral portion of the bonding wafer 3 together with the wax 7 is removed. After grinding, the wax 7 applied to the peripheral portion is removed with a solvent or the like. In this case, the region including the unbonded portion between the semiconductor wafer 1 and the semiconductor wafer 2 is ground in the thickness direction to just before (approximately 50 μm before) the bonding interface (FIG. 1 (6)).
reference).
【0023】更に、アルカリ性のエッチング液(TMA
H:水酸化テトラメチルアンモニウム水溶液、APW:
エチレンジアミン、ピロカテコール及び水の混合液)を
使用して研削部8の研削による破壊層及び酸化膜上部の
シリコンを除去する(図1(7)参照)。ここで、図中
11は、APW溶液又はTMAH溶液によるエッチング
後の研削部である。その後、素子形成層の研削(図1
(8)参照)を行い、鏡面仕上げ等を行う(図1
(9))。尚、本例においては、貼り合わせSOIウエ
ーハの裏面に形成された酸化膜を除去せずに貼り合わせ
SOIウエーハを形成する工程を示している。また、前
記エッチングにおいて、外周部に残った酸化膜は素子形
成層の研削、鏡面仕上げの工程において粉砕され平坦化
される。Further, an alkaline etching solution (TMA)
H: Tetramethylammonium hydroxide aqueous solution, APW:
Using a mixture of ethylenediamine, pyrocatechol and water), the destruction layer and the silicon on the oxide film are removed by grinding the grinding portion 8 (see FIG. 1 (7)). Here, reference numeral 11 in the figure denotes a ground portion after etching with the APW solution or the TMAH solution. Then, the element formation layer is ground (FIG. 1)
(Refer to (8)) to perform mirror finishing and the like (FIG. 1)
(9)). In this example, a process of forming a bonded SOI wafer without removing an oxide film formed on the back surface of the bonded SOI wafer is shown. In the above etching, the oxide film remaining on the outer peripheral portion is pulverized and flattened in the steps of grinding and mirror finishing the element formation layer.
【0024】次に、前述した接着ウエーハ3にワックス
7を塗布するワックス塗布装置を図面に基づいて説明す
る。図2は、接着ウエーハの外周部にワックスを塗布す
るワックス塗布装置12の概略構成図を示す。Next, a wax coating apparatus for applying the wax 7 to the above-mentioned bonded wafer 3 will be described with reference to the drawings. FIG. 2 is a schematic configuration diagram of a wax application device 12 that applies wax to an outer peripheral portion of an adhesive wafer.
【0025】図2に示すように、ワックス塗布装置12
は、接着ウエーハ3を保持する真空チャック13、前記
真空チャック13を回転させるモータ14、ワックス保
持容器15、前記ワックス保持容器15に連結されてい
るワックス供給用ノズル16、及び温風ヒータ17から
構成されている。As shown in FIG. 2, the wax coating device 12
Comprises a vacuum chuck 13 for holding the bonding wafer 3, a motor 14 for rotating the vacuum chuck 13, a wax holding container 15, a wax supply nozzle 16 connected to the wax holding container 15, and a hot air heater 17. Have been.
【0026】前記ワックス供給用ノズル16は、真空チ
ャック13に保持された接着ウエーハ3の周縁部に接触
する位置に設置されている。The wax supply nozzle 16 is provided at a position in contact with the peripheral edge of the adhesive wafer 3 held by the vacuum chuck 13.
【0027】真空チャック13に保持された接着ウエー
ハ3は、モータ14によって回動する真空チャック13
に伴って回転し、前記ワックス用ノズル16から一定量
のワックスが接着ウエーハ3の周縁部に供給されて、接
着ウエーハ3の外縁部全周に一定量のワックスが塗布さ
れるようになっている。The bonded wafer 3 held by the vacuum chuck 13 is rotated by a motor 14
, And a certain amount of wax is supplied from the wax nozzle 16 to the periphery of the bonding wafer 3, and a certain amount of wax is applied to the entire periphery of the bonding wafer 3. .
【0028】図3は、周縁部位にワックス塗布した接着
ウエーハの周縁部拡大図を示す。FIG. 3 is an enlarged view of the peripheral portion of the adhesive wafer whose peripheral portion is coated with wax.
【0029】図3に示すように接着ウエーハ3の周縁部
にワックス7が塗布されていると、研削時に研削装置等
の砥石18等から加わる力が直接ウエーハ3に加わら
ず、前記ワックス7が緩衝材となって力が分散するた
め、ウエーハ3の割れや欠けを防止することができる。As shown in FIG. 3, when the wax 7 is applied to the peripheral portion of the bonding wafer 3, the force applied from the grindstone 18 or the like of the grinding device or the like during grinding is not directly applied to the wafer 3, and the wax 7 is buffered. Since the force is dispersed as a material, cracking and chipping of the wafer 3 can be prevented.
【0030】また、接着ウエーハの外縁部がワックスに
よって保護されていると、研削時に生じたダスト等のパ
ーティクルが誘電体層に入り込むことを防止することが
でき、前記パーティクルによって誘電体層が傷ついて、
後にエッチピット等が発生するのを防止し、良品率を向
上させることができる。If the outer edge of the adhesive wafer is protected by the wax, particles such as dust generated during grinding can be prevented from entering the dielectric layer, and the dielectric layer is damaged by the particles. ,
It is possible to prevent the occurrence of etch pits and the like later, and to improve the yield rate.
【0031】[0031]
【発明の効果】 以上説明したように本発明に係る貼り
合わせSOI基板の製造方法は、第1の半導体ウエーハ
及び第2の半導体ウエーハの一方もしくは双方に誘電体
層を有すると共に、これら半導体ウエーハの鏡面同士を
密着させ酸化性雰囲気中で熱処理により接着する工程
と、前記第1の半導体ウエーハの周縁部に発生する未接
着となる部分を含む領域を、前記第2の半導体ウエーハ
にダメージが達しない厚みまで研削する工程とを備え、
前記第1の半導体ウエーハの周縁部を研削する際に、第
1の半導体ウエーハ及び第2の半導体ウエーハの周辺部
にワックス等の保護材を塗布するため、前記保護剤が緩
衝材となって、研削研磨時に半導体ウエーハに加わる力
が分散し、半導体ウエーハの割れや欠けを防止し、良品
率を向上することができる。As described above, the method for manufacturing a bonded SOI substrate according to the present invention uses the first semiconductor wafer.
A dielectric material on one or both of the second semiconductor wafer and the second semiconductor wafer
Layers, and mirror surfaces of these semiconductor wafers
Step of bonding by heat treatment in an oxidizing atmosphere
And unconnected portions generated at the periphery of the first semiconductor wafer.
A region including a portion to be attached to the second semiconductor wafer.
Grinding to a thickness that does not cause damage to the
When grinding the peripheral portion of the first semiconductor wafer, a protective material such as wax is applied to the peripheral portions of the first semiconductor wafer and the second semiconductor wafer. The force applied to the semiconductor wafer at the time of grinding and polishing is dispersed, so that the semiconductor wafer can be prevented from cracking or chipping, and the yield can be improved.
【0032】また、第1の半導体ウエーハ及び第2の半
導体ウエーハの周縁部位は、ワックス等の保護剤が塗布
されているため、第1及び第2の半導体ウエーハの間に
介在する埋め込み酸化膜に研削研磨時に発生したパーテ
ィクル等が入り込むのを防止することができ、埋め込み
酸化膜5や酸化膜6が傷付くのを防いで良品率を向上さ
せることができる。The peripheral portions of the first semiconductor wafer and the second semiconductor wafer are coated with a protective agent such as wax, so that the peripheral portions of the first semiconductor wafer and the second semiconductor wafer are filled with a buried oxide film interposed between the first and second semiconductor wafers. Particles and the like generated during grinding and polishing can be prevented from entering, and the buried oxide film 5 and the oxide film 6 can be prevented from being damaged, and the yield can be improved.
【0033】[0033]
【0034】[0034]
【図1】本発明に係る貼り合わせSOI基板の製造方法
示す工程図である。FIG. 1 is a process chart showing a method for manufacturing a bonded SOI substrate according to the present invention.
【図2】本発明に係る貼り合わせSOI基板のワックス
塗布装置を示す概略構成図である。FIG. 2 is a schematic configuration diagram illustrating a wax application device for a bonded SOI substrate according to the present invention.
【図3】本発明に係り、貼り合わせSOI基板の外縁部
位を示す一部拡大図である。FIG. 3 is a partially enlarged view showing an outer edge portion of the bonded SOI substrate according to the present invention.
【図4】従来例に係り、(a)及び(b)は貼り合わせ
SOI基板の外縁部位を示す一部拡大図である4A and 4B are partially enlarged views showing an outer edge portion of a bonded SOI substrate according to a conventional example.
【図5】従来例に係る貼り合わせSOI基板の製造方法
を示す工程図である。FIG. 5 is a process chart showing a method for manufacturing a bonded SOI substrate according to a conventional example.
1 第1の半導体ウエーハ 2 第2の半導体ウエーハ 3 接着ウエーハ 5 誘電体層 6 酸化膜 7 ワックス 8 研削部 10 研削部 11 研削部 12 ワックス塗布装置 13 真空チャック 14 モータ 15 ワックス保持容器 16 ワックス供給用ノズル 17 温風ヒータ 18 砥石 DESCRIPTION OF SYMBOLS 1 1st semiconductor wafer 2 2nd semiconductor wafer 3 Adhesion wafer 5 Dielectric layer 6 Oxide film 7 Wax 8 Grinding part 10 Grinding part 11 Grinding part 12 Wax coating device 13 Vacuum chuck 14 Motor 15 Wax holding container 16 Wax supply Nozzle 17 Hot air heater 18 Whetstone
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/304 622 H01L 21/02 H01L 27/12 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/304 622 H01L 21/02 H01L 27/12
Claims (1)
ウエーハの一方もしくは双方に誘電体層を有すると共
に、これら半導体ウエーハの鏡面同士を密着させ酸化性
雰囲気中で熱処理により接着する工程と、前記第1の半
導体ウエーハの周縁部に発生する未接着となる部分を含
む領域を、前記第2の半導体ウエーハにダメージが達し
ない厚みまで研削する工程とを備え、前記第1の半導体
ウエーハの周縁部を研削する際に、第1の半導体ウエー
ハ及び第2の半導体ウエーハの周辺部に保護材を塗布す
ることを特徴とするSOI基板の製造方法。A step of having a dielectric layer on one or both of a first semiconductor wafer and a second semiconductor wafer, bringing mirror surfaces of these semiconductor wafers into close contact with each other, and bonding them by heat treatment in an oxidizing atmosphere; Including the unbonded portion generated at the peripheral portion of the first semiconductor wafer
Grinding a region to be damaged to a thickness at which the second semiconductor wafer is not damaged. When grinding the peripheral portion of the first semiconductor wafer, the first semiconductor wafer and the second semiconductor wafer are ground. A method for manufacturing an SOI substrate, comprising applying a protective material to a peripheral portion of the SOI substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22627797A JP3216583B2 (en) | 1997-08-22 | 1997-08-22 | Manufacturing method of bonded SOI substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22627797A JP3216583B2 (en) | 1997-08-22 | 1997-08-22 | Manufacturing method of bonded SOI substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH1167701A JPH1167701A (en) | 1999-03-09 |
JP3216583B2 true JP3216583B2 (en) | 2001-10-09 |
Family
ID=16842696
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22627797A Expired - Fee Related JP3216583B2 (en) | 1997-08-22 | 1997-08-22 | Manufacturing method of bonded SOI substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3216583B2 (en) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11204452A (en) | 1998-01-13 | 1999-07-30 | Mitsubishi Electric Corp | Semiconductor substrate and method for treatment thereof |
US6908027B2 (en) * | 2003-03-31 | 2005-06-21 | Intel Corporation | Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening process |
JP2008060355A (en) | 2006-08-31 | 2008-03-13 | Sumco Corp | Laminated wafer, and manufacturing method therefor |
FR2935536B1 (en) | 2008-09-02 | 2010-09-24 | Soitec Silicon On Insulator | PROGRESSIVE DETOURING METHOD |
FR2961630B1 (en) | 2010-06-22 | 2013-03-29 | Soitec Silicon On Insulator Technologies | APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICES |
US8338266B2 (en) | 2010-08-11 | 2012-12-25 | Soitec | Method for molecular adhesion bonding at low pressure |
FR2964193A1 (en) | 2010-08-24 | 2012-03-02 | Soitec Silicon On Insulator | METHOD FOR MEASURING ADHESION ENERGY, AND ASSOCIATED SUBSTRATES |
JP5841738B2 (en) * | 2011-04-05 | 2016-01-13 | 株式会社ディスコ | Wafer grinding method |
JP5784658B2 (en) | 2013-02-28 | 2015-09-24 | 株式会社東芝 | Semiconductor device manufacturing method and manufacturing apparatus |
KR102524962B1 (en) * | 2016-11-14 | 2023-04-21 | 삼성전자주식회사 | Method for fabricating substrate structure and substrate structure fabricated by using the method |
CN109786234B (en) * | 2017-11-13 | 2021-06-04 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
CN108899272A (en) * | 2018-07-06 | 2018-11-27 | 德淮半导体有限公司 | Method for manufacturing semiconductor device |
WO2023182393A1 (en) * | 2022-03-25 | 2023-09-28 | 株式会社村田製作所 | Method for manufacturing wafer |
-
1997
- 1997-08-22 JP JP22627797A patent/JP3216583B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH1167701A (en) | 1999-03-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4846915B2 (en) | Manufacturing method of bonded wafer | |
KR100542850B1 (en) | Manufacturing method of semiconductor apparatus | |
JP3216583B2 (en) | Manufacturing method of bonded SOI substrate | |
KR100789205B1 (en) | Production method for silicon wafer and soi wafer, and soi wafer | |
US6214704B1 (en) | Method of processing semiconductor wafers to build in back surface damage | |
JP3368876B2 (en) | Semiconductor chip manufacturing method | |
JP3352896B2 (en) | Manufacturing method of bonded substrate | |
US6958298B2 (en) | Method for thinning wafer by grinding | |
JPH0376118A (en) | Manufacture of substrate for semiconductor element formation | |
US6113721A (en) | Method of bonding a semiconductor wafer | |
JP4198966B2 (en) | Manufacturing method of semiconductor device | |
JP2005050997A (en) | Semiconductor element isolation method | |
JPH07106285A (en) | Manufacture of semiconductor device | |
JPH0917984A (en) | Bonded soi substrate manufacturing method | |
JP2662495B2 (en) | Method for manufacturing bonded semiconductor substrate | |
JP3352129B2 (en) | Semiconductor substrate manufacturing method | |
EP0860862B1 (en) | Method of manufacturing a bonding substrate | |
JP2000348992A (en) | Manufacture of semiconductor substrate | |
JPH05226305A (en) | Manufacture of laminated wafer | |
CN113471069A (en) | Infrared detector, hybrid chip and back thinning scratch processing method thereof | |
JPH10209408A (en) | Manufacture of soi substrate | |
JPH03183130A (en) | Manufacture of semiconductor substrate | |
JP3422225B2 (en) | Laminated semiconductor substrate and method of manufacturing the same | |
JPH10335195A (en) | Production of pasted board | |
JP2003151939A (en) | Method of manufacturing soi substrate |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20070803 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080803 Year of fee payment: 7 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080803 Year of fee payment: 7 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090803 Year of fee payment: 8 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090803 Year of fee payment: 8 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100803 Year of fee payment: 9 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110803 Year of fee payment: 10 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110803 Year of fee payment: 10 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120803 Year of fee payment: 11 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120803 Year of fee payment: 11 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130803 Year of fee payment: 12 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |