JPH1187203A - Method for bonding substrates - Google Patents

Method for bonding substrates

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Publication number
JPH1187203A
JPH1187203A JP26491297A JP26491297A JPH1187203A JP H1187203 A JPH1187203 A JP H1187203A JP 26491297 A JP26491297 A JP 26491297A JP 26491297 A JP26491297 A JP 26491297A JP H1187203 A JPH1187203 A JP H1187203A
Authority
JP
Japan
Prior art keywords
bonding
wafer
wafers
bonded
width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26491297A
Other languages
Japanese (ja)
Inventor
Muneharu Shimanoe
宗治 島ノ江
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP26491297A priority Critical patent/JPH1187203A/en
Publication of JPH1187203A publication Critical patent/JPH1187203A/en
Pending legal-status Critical Current

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  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PROBLEM TO BE SOLVED: To form a bonded substrate with a narrow non-contact area at the peripheral portion thereof, which can be readily treated. SOLUTION: After having a pair of Si wafers 11, 12 make contact with each other for bonding through a suction force, at least one of the Si wafers 11, 12 is pressured at the periphery thereof, to bring the peripheries of both of the wafers into contact with each other for further bonding. In the case where there exist large spaces between the peripheries of the Si wafers 11, 12 such that they do not cause a suction force to be generated for bonding, owing to the forced contact of the peripheries by pressure for bonding, the width of the bonding portion at the peripheral portion can be rendered narrow, and thus peeling or the like is hardly caused in the treatment thereafter.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本願の発明は、一対の基板同
士を貼り合わせて貼り合わせ基板を形成するための基板
の貼り合わせ方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of bonding substrates for bonding a pair of substrates together to form a bonded substrate.

【0002】[0002]

【従来の技術】例えばSOI構造の半導体装置を製造す
るための一つの方法として、第1の半導体ウェハの表面
上に絶縁膜と平坦化加工膜とを順次に形成し、平坦化加
工膜を介して第1の半導体ウェハに第2の半導体ウェハ
を貼り合わせ、第1の半導体ウェハを裏面側から研削し
て、絶縁膜のうちで第2の半導体ウェハとは反対側の面
に第1の半導体ウェハから形成された半導体薄膜を有す
る貼り合わせSOIウェハを形成する方法がある。
2. Description of the Related Art For example, as one method for manufacturing a semiconductor device having an SOI structure, an insulating film and a planarizing film are sequentially formed on the surface of a first semiconductor wafer, and the planarizing film is formed on the insulating film. The first semiconductor wafer is bonded to the second semiconductor wafer by grinding, and the first semiconductor wafer is ground from the back side, and the first semiconductor wafer is formed on the surface of the insulating film opposite to the second semiconductor wafer. There is a method of forming a bonded SOI wafer having a semiconductor thin film formed from a wafer.

【0003】図2は、一対のSiウェハ同士を貼り合わ
せるための一般的な方法を示している。この方法では、
図2(a)に示す様に、絶縁膜としてのSiO2 膜(図
示せず)と平坦化加工膜としての多結晶Si膜(図示せ
ず)とが表面上に順次に形成されていてボンドウェハと
称されているSiウェハ11と、ベースウェハと称され
ていてSiウェハ11に貼り合わされるべきSiウェハ
12とを用意する。
FIG. 2 shows a general method for bonding a pair of Si wafers together. in this way,
As shown in FIG. 2A, a SiO 2 film (not shown) as an insulating film and a polycrystalline Si film (not shown) as a planarization film are sequentially formed on the surface, and a bond wafer is formed. An Si wafer 11 referred to as a base wafer and a Si wafer 12 referred to as a base wafer to be bonded to the Si wafer 11 are prepared.

【0004】この貼り合わせはSiウェハ11、12の
貼り合わせ面に介在する水や水酸基の作用による水素結
合によって達成されると考えられているので、十分な水
素結合力を得るために、貼り合わせに先立って、Siウ
ェハ11、12の貼り合わせ面に親水性処理を施すと共
に塵埃を除去する。
[0004] Since this bonding is considered to be achieved by hydrogen bonding due to the action of water or a hydroxyl group interposed on the bonding surfaces of the Si wafers 11 and 12, the bonding is performed in order to obtain a sufficient hydrogen bonding force. Prior to this, the bonding surfaces of the Si wafers 11 and 12 are subjected to a hydrophilic treatment and dust is removed.

【0005】親水性処理としては、弗酸による処理とア
ンモニア過酸化水素水混合液による処理とを連続的に行
う。この親水性処理によって、Siウェハ11、12の
貼り合わせ面の水酸基が増加する。なお、親水性処理と
しては弗酸による処理のみでもよい。
As the hydrophilic treatment, treatment with hydrofluoric acid and treatment with a mixed solution of aqueous ammonia and hydrogen peroxide are continuously performed. By this hydrophilic treatment, hydroxyl groups on the bonding surfaces of the Si wafers 11 and 12 increase. In addition, only the treatment with hydrofluoric acid may be performed as the hydrophilic treatment.

【0006】親水性処理の後、真空チャック13の平坦
な多孔質部材14でSiウェハ11を吸引し、このSi
ウェハ11上にSiウェハ12を位置合わせして載置す
る。しかし、この状態では、空気の粘性抵抗等のために
Siウェハ11、12同士の間に数μmの間隔が生じて
いて、Siウェハ11、12同士は接着しない。
After the hydrophilic treatment, the Si wafer 11 is sucked by the flat porous member 14 of the vacuum chuck 13 and the Si wafer 11 is sucked.
The Si wafer 12 is positioned and placed on the wafer 11. However, in this state, an interval of several μm is generated between the Si wafers 11 and 12 due to viscous resistance of air and the like, and the Si wafers 11 and 12 do not adhere to each other.

【0007】そこで、図2(b)に示す様に、押し棒1
5でSiウェハ12の中心部に圧力を加えて、Siウェ
ハ11、12の中心部同士を接触させる。すると、この
接触部同士が上述の水素結合力で接着し、更に、図2
(c)に示す様に、水素結合力による接着がSiウェハ
11、12の周辺部へ進行する自己接着が生じる。この
結果、図3(a)に示す様に、Siウェハ11、12同
士が貼り合わされた貼り合わせSiウェハ16が形成さ
れる。
[0007] Therefore, as shown in FIG.
In step 5, pressure is applied to the center of the Si wafer 12 to bring the centers of the Si wafers 11 and 12 into contact with each other. Then, the contact portions adhere to each other by the above-described hydrogen bonding force,
As shown in (c), self-adhesion occurs in which the adhesion due to the hydrogen bonding force proceeds to the peripheral portions of the Si wafers 11 and 12. As a result, as shown in FIG. 3A, a bonded Si wafer 16 in which the Si wafers 11 and 12 are bonded to each other is formed.

【0008】ところで、インゴットから切断されて形成
されたSiウェハ11、12には研磨や面取り等が施さ
れるが、この研磨等のために、図3(b)に示す様に、
Siウェハ11、12の周辺部に、0.15〜0.5m
m程度の幅Aを有する面取り部以外に、厚さの僅かに薄
い部分が1.0〜2.0mm程度の幅Bで形成されてし
まう。
By the way, the Si wafers 11 and 12 formed by cutting from the ingot are subjected to polishing and chamfering. For this polishing and the like, as shown in FIG.
0.15 to 0.5 m around the Si wafers 11 and 12
In addition to the chamfered portion having a width A of about m, a slightly thinner portion is formed with a width B of about 1.0 to 2.0 mm.

【0009】この厚さの薄い部分ではSiウェハ11、
12同士の間隔が広過ぎて自己接着が生じないので、厚
さの薄い部分が非接着部になる。貼り合わせSiウェハ
16に非接着部を残存させておくと、SOI構造の半導
体装置を製造するためのその後の工程でこの非接着部が
剥離する可能性があって、半導体装置の歩留りが低下す
る。
In the thin portion, the Si wafer 11,
Since the interval between the 12 is too wide and self-adhesion does not occur, a thin portion becomes a non-adhesion portion. If the non-bonded portion is left on the bonded Si wafer 16, the non-bonded portion may be peeled off in a subsequent process for manufacturing a semiconductor device having an SOI structure, and the yield of the semiconductor device is reduced. .

【0010】そこで、図3(a)に示した状態から貼り
合わせSiウェハ16の表裏を反転させ、図3(b)中
に一点鎖線で示す様に、非接着部を除去するために主に
Siウェハ11の周辺部に対して1.0mm程度の幅C
の面取りを施している。なお、主にSiウェハ11に対
して面取りを施すのは、貼り合わせSiウェハ16の径
を一定に維持するためである。
Therefore, the bonded Si wafer 16 is turned upside down from the state shown in FIG. 3A, and as shown by the dashed line in FIG. A width C of about 1.0 mm with respect to the peripheral portion of the Si wafer 11
Has been chamfered. The reason why the chamfering is mainly performed on the Si wafer 11 is to keep the diameter of the bonded Si wafer 16 constant.

【0011】また、貼り合わせSiウェハ16の周辺部
における面取りの幅Cよりも非接着部の幅Bの方が広い
可能性も高いので、図3(b)の状態からSiウェハ1
1を研削して形成したSi薄膜がその後の工程で剥離す
るのを防止するために、このSi薄膜のうちで非接着部
の部分を予め強制的に剥離している。
Since the width B of the non-adhered portion is more likely to be wider than the width C of the chamfer in the peripheral portion of the bonded Si wafer 16, the Si wafer 1 shown in FIG.
In order to prevent the Si thin film formed by grinding No. 1 from peeling in a subsequent step, the non-bonded portion of the Si thin film is forcibly peeled in advance.

【0012】[0012]

【発明が解決しようとする課題】しかし、図2、3に示
した本願の発明の一従来例では、貼り合わせSiウェハ
16の周辺部における非接着部の幅Bが広いので、非接
着部を除去するための面取りの幅Cも広かった。このた
め、面取り工程で貼り合わせSiウェハ16に欠け等の
不良の発生する可能性が高くて、半導体装置の歩留りが
低かった。
However, in the conventional example of the present invention shown in FIGS. 2 and 3, since the width B of the non-adhesive portion in the peripheral portion of the bonded Si wafer 16 is large, the non-adhesive portion is The width C of the chamfer for removal was also wide. Therefore, there is a high possibility that a defect such as chipping occurs in the bonded Si wafer 16 in the chamfering step, and the yield of the semiconductor device is low.

【0013】一方、Siウェハ11、12のうちで半導
体装置が形成されない部分つまり周辺部に、Siウェハ
11、12を識別するためのウェハ番号がレーザで刻印
されている。しかし、上述の欠けによってこのウェハ番
号が判読不能になる可能性も高く、半導体装置の製造に
支障を生じ易かった。
On the other hand, a wafer number for identifying the Si wafers 11 and 12 is laser-engraved on a portion of the Si wafers 11 and 12 where no semiconductor device is formed, that is, a peripheral portion. However, there is a high possibility that the wafer number becomes unreadable due to the above-mentioned chipping, and the production of the semiconductor device is likely to be hindered.

【0014】また、上述の様に、Siウェハ11の研削
で形成したSi薄膜のうちで非接着部の部分を予め強制
的に剥離しているが、非接着部の幅Bが広い。このた
め、Si薄膜を剥離するために必要な時間も長く、半導
体装置を高いスループットで製造することが困難であっ
た。
As described above, the non-bonded portion of the Si thin film formed by grinding the Si wafer 11 is forcibly peeled in advance, but the width B of the non-bonded portion is large. Therefore, the time required for removing the Si thin film is long, and it has been difficult to manufacture a semiconductor device with high throughput.

【0015】つまり、図2、3に示した本願の発明の一
従来例で形成した貼り合わせSiウェハ16では、周辺
部における非接着部の幅が広いので、その後の処理が容
易ではなかった。従って、本願の発明は、周辺部におけ
る非接着部の幅が狭くて、その後の処理が容易な貼り合
わせ基板を形成することかできる方法を提供することを
目的としている。
That is, in the bonded Si wafer 16 formed in the conventional example of the present invention shown in FIGS. 2 and 3, since the width of the non-bonded portion in the peripheral portion is wide, the subsequent processing is not easy. Accordingly, an object of the present invention is to provide a method capable of forming a bonded substrate in which the width of a non-adhesive portion in a peripheral portion is small and the subsequent processing is easy.

【0016】[0016]

【課題を解決するための手段】請求項1に係る基板の貼
り合わせ方法では、一対の基板の周辺部同士に大きな隙
間が存在していて吸着力による接着が周辺部で生じない
場合でも、周辺部同士を圧力で強制的に接触させて接着
させるので、周辺部における非接着部の幅が狭い。
According to the first aspect of the present invention, even when a large gap exists between the peripheral portions of a pair of substrates and adhesion by an attraction force does not occur in the peripheral portions, the method for bonding substrates can be performed in a peripheral region. Since the parts are forcibly brought into contact with each other by pressure and bonded, the width of the non-bonded part in the peripheral part is narrow.

【0017】請求項2に係る基板の貼り合わせ方法で
は、中心部から中心部以外の部分つまり周辺部へ接着を
進行させるので、例えば周辺部の一部から反対側の周辺
部へ接着を進行させる場合に比べて、接着の進行に要す
る時間が短い。しかも、中心部から接着を開始しても、
一対の基板の周辺部同士を加圧で強制的に接触させて接
着させるので、周辺部における非接着部の幅が狭い。
In the method for bonding substrates according to the second aspect, since the adhesion proceeds from the central portion to a portion other than the central portion, that is, the peripheral portion, for example, the adhesive proceeds from a part of the peripheral portion to the peripheral portion on the opposite side. The time required for the adhesion to proceed is shorter than in the case. Moreover, even if you start bonding from the center,
Since the peripheral portions of the pair of substrates are forcibly brought into contact with each other by pressing and bonded, the width of the non-bonded portion in the peripheral portions is narrow.

【0018】[0018]

【発明の実施の形態】以下、一対のSiウェハ同士の貼
り合わせに適用した本願の発明の一実施形態を、図1を
参照しながら説明する。本実施形態でも、水素結合力に
よる接着がSiウェハ11、12の中心部から周辺部へ
進行する自己接着を生じさせるまでは、図2、3に示し
た一従来例と実質的に同様の工程を実行する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to bonding a pair of Si wafers will be described below with reference to FIG. Also in the present embodiment, steps substantially the same as those in the conventional example shown in FIGS. 2 and 3 until the bonding by the hydrogen bonding force causes self-adhesion that progresses from the center of the Si wafers 11 and 12 to the periphery. Execute

【0019】しかし、本実施形態では、図3(a)に示
した様に自己接着が終了した後、直ちに、図1に示す様
に、Siウェハ11、12の周端から幅5〜10mmの
周辺部に環帯状の治具17で圧力を加え、Siウェハ1
1、12の周辺部同士を弾性変形させて互いに接触させ
て、これらの周辺部でも水素結合力による接着を生じさ
せる。
However, in the present embodiment, immediately after the self-adhesion is completed as shown in FIG. 3A, as shown in FIG. Pressure is applied to the peripheral portion with a ring-shaped jig 17 and the Si wafer 1
The peripheral portions 1 and 12 are elastically deformed and brought into contact with each other, and the peripheral portions also cause adhesion by hydrogen bonding force.

【0020】Siウェハ11、12の周辺部同士が接着
すると、治具17によるSiウェハ11、12の周辺部
への圧力を解除しても、Siウェハ11、12の弾性応
力よりも接着力の方が強ければ、Siウェハ11、12
の周辺部同士の接着が維持される。
When the peripheral portions of the Si wafers 11 and 12 are adhered to each other, even if the pressure applied to the peripheral portions of the Si wafers 11 and 12 by the jig 17 is released, the adhesive force of the Si wafers 11 and 12 is smaller than the elastic stress of the Si wafers 11 and 12. If it is stronger, Si wafers 11 and 12
The adhesion between the peripheral portions is maintained.

【0021】従って、以上の実施形態で形成した貼り合
わせSiウェハ18の周辺部における非接着部の幅は、
図2、3に示した一従来例で形成した貼り合わせSiウ
ェハ16の周辺部における非接着部の幅Bよりも狭い。
このため、非接着部を除去するための面取りの幅も狭く
てよく、面取り工程で貼り合わせSiウェハ18に欠け
等の不良の発生する可能性が低くて、半導体装置の歩留
りが高い。
Therefore, the width of the non-bonded portion in the peripheral portion of the bonded Si wafer 18 formed in the above embodiment is
The width B of the non-bonded portion in the peripheral portion of the bonded Si wafer 16 formed in the conventional example shown in FIGS.
For this reason, the width of the chamfer for removing the non-adhered portion may be narrow, and the possibility of occurrence of defects such as chipping in the bonded Si wafer 18 in the chamfering step is low, and the yield of the semiconductor device is high.

【0022】また、この様に非接着部の幅が狭ければ、
幅1mmの面取り部よりも内側の部分が剥離する可能性
が低いので、Siウェハ11、12に刻印されているウ
ェハ番号が判読不能になる可能性も低く、半導体装置の
製造に支障を生じにくい。更に、上述の様に非接着部の
幅が狭いので、この後のSiウェハ11の研削で形成す
るSi薄膜のうちで非接着部の部分を予め強制的に剥離
するために必要な時間も短く、半導体装置を高いスルー
プットで製造することができる。
In addition, if the width of the non-adhesive portion is narrow as described above,
Since there is a low possibility that the portion inside the chamfered portion having a width of 1 mm is peeled off, the possibility that the wafer numbers imprinted on the Si wafers 11 and 12 become unreadable is also low, and it is unlikely to hinder the manufacture of the semiconductor device. . Further, since the width of the non-bonded portion is narrow as described above, the time required for forcibly peeling off the non-bonded portion in advance in the Si thin film formed by the subsequent grinding of the Si wafer 11 is also short. In addition, a semiconductor device can be manufactured with high throughput.

【0023】なお、以上の実施形態では、一対のSiウ
ェハ11、12のうちでSiウェハ12にのみ治具17
で圧力を加えているが、一対のSiウェハ11、12の
両方に圧力を加えてもよい。また、上述の実施形態で
は、押し棒15でSiウェハ12の中心部に圧力を加え
て、この中心部から周辺部へ進行する自己接着を生じさ
せているが、中心部以外の部分から自己接着を生じさせ
てもよい。
In the above embodiment, the jig 17 is used only for the Si wafer 12 of the pair of Si wafers 11 and 12.
Is applied, but pressure may be applied to both the pair of Si wafers 11 and 12. Further, in the above-described embodiment, the pressure is applied to the central portion of the Si wafer 12 by the push rod 15 to cause self-adhesion to progress from the central portion to the peripheral portion. May be caused.

【0024】また、上述の実施形態は一対のSiウェハ
11、12同士の貼り合わせに本願の発明を適用したも
のであるが、Siウェハ11、12以外の半導体ウェハ
同士の貼り合わせや半導体ウェハ以外の基板の貼り合わ
せにも本願の発明を適用することができる。
In the above embodiment, the present invention is applied to the bonding of a pair of Si wafers 11 and 12, but the bonding of the semiconductor wafers other than the Si wafers 11 and 12 and the bonding of the semiconductor wafers other than the semiconductor wafer are performed. The present invention can be applied to the bonding of the substrates.

【0025】[0025]

【発明の効果】請求項1に係る基板の貼り合わせ方法で
は、周辺部における非接着部の幅が狭いので、その後の
処理が容易な貼り合わせ基板を形成することかできる。
According to the method for bonding substrates according to the first aspect, since the width of the non-bonded portion in the peripheral portion is narrow, a bonded substrate that can be easily processed thereafter can be formed.

【0026】請求項2に係る基板の貼り合わせ方法で
は、接着の進行に要する時間が短く、しかも、周辺部に
おける非接着部の幅が狭いので、その後の処理が容易な
貼り合わせ基板を高いスループットで形成することかで
きる。
In the substrate bonding method according to the second aspect, the time required for the progress of bonding is short, and the width of the non-bonded portion in the peripheral portion is narrow, so that the bonded substrate that can be easily processed thereafter has a high throughput. Can be formed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本願の発明の一実施形態の最後の工程を示す側
断面図である。
FIG. 1 is a side sectional view showing a final step of an embodiment of the present invention.

【図2】基板を貼り合わせるための一般的な方法を工程
順に示す側断面図である。
FIG. 2 is a side sectional view showing a general method for bonding substrates in the order of steps.

【図3】(a)は本願の発明の一従来例の最後の工程を
示す側断面図、(b)は一従来例で形成した貼り合わせ
基板の周辺部近傍の側断面図である。
FIG. 3A is a side sectional view showing a final step of a conventional example of the invention of the present application, and FIG. 3B is a side sectional view of the vicinity of a peripheral portion of a bonded substrate formed in the conventional example.

【符号の説明】[Explanation of symbols]

11、12…Siウェハ(基板)、18…貼り合わせS
iウェハ
11, 12: Si wafer (substrate), 18: Bonded S
i wafer

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 一対の基板の一部同士を接触させ、前記
一対の基板同士の吸着力による接着を前記接触部からこ
の接触部以外の部分へ進行させて、前記一対の基板同士
を貼り合わせる基板の貼り合わせ方法において、 前記接着の終了後に前記一対の基板の少なくとも一方の
周辺部に圧力を加え、前記一対の基板の周辺部同士を接
触させて接着させることを特徴とする基板の貼り合わせ
方法。
1. A method in which a part of a pair of substrates is brought into contact with each other, and the adhesion of the pair of substrates by an attraction force is advanced from the contact portion to a portion other than the contact portion to bond the pair of substrates. In the method of bonding substrates, after the bonding is completed, pressure is applied to at least one peripheral portion of the pair of substrates, and the peripheral portions of the pair of substrates are brought into contact with each other and bonded. Method.
【請求項2】 前記一対の基板の夫々の中心部を前記一
部にする請求項1記載の基板の貼り合わせ方法。
2. The method according to claim 1, wherein the center of each of the pair of substrates is set to the part.
JP26491297A 1997-09-11 1997-09-11 Method for bonding substrates Pending JPH1187203A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26491297A JPH1187203A (en) 1997-09-11 1997-09-11 Method for bonding substrates

Publications (1)

Publication Number Publication Date
JPH1187203A true JPH1187203A (en) 1999-03-30

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007036279A (en) * 2000-01-07 2007-02-08 Canon Inc Method for manufacturing semiconductor substrate
JP2007515779A (en) * 2003-05-19 2007-06-14 ジプトロニクス・インコーポレイテッド Room temperature covalent bonding method
JP2013191893A (en) * 2013-07-02 2013-09-26 Nikon Corp Method of manufacturing laminate semiconductor device
WO2021039427A1 (en) * 2019-08-30 2021-03-04 東京エレクトロン株式会社 Pressing device, substrate processing system, and substrate processing method

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007036279A (en) * 2000-01-07 2007-02-08 Canon Inc Method for manufacturing semiconductor substrate
JP2007515779A (en) * 2003-05-19 2007-06-14 ジプトロニクス・インコーポレイテッド Room temperature covalent bonding method
US8163373B2 (en) 2003-05-19 2012-04-24 Ziptronix, Inc. Method of room temperature covalent bonding
US8841002B2 (en) 2003-05-19 2014-09-23 Ziptronix, Inc. Method of room temperature covalent bonding
US10434749B2 (en) 2003-05-19 2019-10-08 Invensas Bonding Technologies, Inc. Method of room temperature covalent bonding
US11760059B2 (en) 2003-05-19 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Method of room temperature covalent bonding
JP2013191893A (en) * 2013-07-02 2013-09-26 Nikon Corp Method of manufacturing laminate semiconductor device
WO2021039427A1 (en) * 2019-08-30 2021-03-04 東京エレクトロン株式会社 Pressing device, substrate processing system, and substrate processing method

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