JP2007036279A - Method for manufacturing semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor substrate on which particles are hardly sticked and a mark is formed easily, and to provide a method for manufacturing it. <P>SOLUTION: In the semiconductor substrate which has a semiconductor layer 3 formed above a supporting substrate 1 via an insulating layer 2, a mark 4 is formed in a region other than the surface region of the semiconductor layer 3. Specifically, a first substrate is prepared, and the mark is formed at the periphery of a second substrate. The first and the second substrates are bonded so as not to be bonded with each other in a part in which the mark is formed, and the unnecessary part of the first substrate is removed. Thus, a transfer layer of the first substrate is transferred to make an SOI substrate. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor substrate used for manufacturing a semiconductor integrated circuit device such as a semiconductor memory, a microprocessor, a system LSI, and the like, and a manufacturing method thereof, and more particularly to a semiconductor substrate on which a mark used for identification of a semiconductor substrate is formed and the semiconductor substrate. It belongs to the technical field of manufacturing methods.

  Examples of the semiconductor substrate include a mirror wafer obtained by polishing at least one surface of a disk-shaped substrate sliced from an ingot, and an epitaxial wafer in which a single crystal semiconductor layer is formed by epitaxial growth on the surface of the mirror wafer.

  In addition to this, a technique for forming a single crystal semiconductor layer on an insulator or a substrate having an insulating layer is called silicon-on-insulator or semiconductor-on-insulator and is widely known as SOI technology, and a semiconductor formed thereby. The substrate is called an SOI substrate or an SOI wafer.

Recently, the following three are typical examples of SOI substrates.
(1) In this method, a SiO ₂ layer is formed by ion implantation of oxygen into a Si single crystal substrate called SIMOX (Separation by Ion Implanted Oxygen).
(2) A microbubble formed in an ion-implanted layer by ion implantation of hydrogen into a Si single crystal substrate by a method called smart cut method, followed by bonding to another substrate and heat treatment Is a method for separating a Si single crystal substrate. The SOI substrate obtained by this method is known as a unibond. Details are disclosed in Japanese Patent Application Laid-Open No. 5-211128 and the corresponding US Pat. No. 5,374,564.

Also, in a modification of this method, hydrogen ions were implanted from a hydrogen plasma into a Si single crystal substrate, and then bonded to another substrate, and high-pressure nitrogen gas was applied to the side wall, thereby performing ion implantation at room temperature. A method for separating a Si single crystal substrate in a layer is also known.
(3) The SOI substrate described last is a method in which a porous semiconductor layer formed on a porous body is transferred to another substrate, and the highest quality can be obtained from the fact that a semiconductor layer can be formed on the porous body by epitaxial growth. It is known as a method for obtaining a good SOI substrate. Specifically, in Japanese Patent No. 2608351 or the specification of USP53771037 corresponding thereto, Japanese Patent Application Laid-Open No. 7-302889 or the specification of USP5856229 corresponding thereto, Japanese Patent No. 2877800 and the corresponding EP0867717. It is disclosed. The methods disclosed therein are excellent in uniformity of the SOI layer thickness, easy to suppress the crystal defect density of the SOI layer low, good in surface flatness of the SOI layer, and expensive in manufacturing. It is excellent in that it does not require special specification equipment and can be manufactured with the same equipment for a wide SOI film thickness range from several hundred angstroms to about 10 microns.

  By the way, it is desirable that the wafers can be individually identified when the wafer is subjected to the manufacturing process (device process) of the semiconductor integrated circuit device. Such identification is a very effective means for managing the process history of each wafer, and is used for defect analysis, process optimization, manufacturing management, and the like. The mirror wafer is identified by marks drawn by processing the wafer surface with laser light.

FIG. 18 shows a cross section of the wafer after such laser marking.
The laser irradiation region on the surface of the wafer is melted by the laser beam to form a concave portion, and the constituent material of the wafer that is melted and ejected from the concave portion rises around the concave portion and hardens again. That is, the outer ring mountain shown in FIG.

  For example, when the laser power is 220 mW and the silicon wafer surface is irradiated in the form of dots, the maximum diameter X1 of the deformed region is 0.04 mm to 0.05 mm, and the diameter X2 of the central recess is 0.02 mm to 0.03 mm. The depth Y1 of the concave portion is 2 μm to 3 μm, and the height Y2 of the convex portion is 0.5 μm to 1.0 μm.

  These values vary with the laser power. Actually, a laser is output in a pulse form, and a number of dots are connected or arranged to draw a mark.

  This mark on the mirror wafer is usually made up of approximately 10 alphanumeric characters and is a unique ID number assigned to each wafer. This standard is also defined in the international standard of SEMI and is a standard method.

  By adjusting the laser output, the drive frequency, the number of shots, etc., it is possible to blow off most of the molten substrate material and prevent the outer ring from being formed. For example, if the laser output is increased, the melted substrate material is blown away to form a deep mark without an outer ring mountain, and if the laser output is lowered, a shallow mark with an outer ring mountain is easily formed.

  Such laser marking is usually assumed for Si mirror wafers, and the printing position is also described in the SEMI standard.

FIG. 19 is a top view of the mirror wafer 21 on which the mark is drawn, and FIG. 20 is a cross-sectional view of the vicinity of the mark.
For example, as shown in FIG. 19, in an 8-inch wafer, for example, when the wafer center 100 is set to the (0, 0) point of the xy coordinates with the notch 12 facing upward,
X: -9.25 to +9.25 mm
Y: +93.7 to +96.5 mm
Thus, the above standard defines that the mark 4 is printed in a rectangular area 24 having a height L2 of 2.8 mm and a length L1 of 18.5 mm.

  When this standard is applied to the SOI wafer, the SOI wafer is in the surface region of the semiconductor layer where the semiconductor layer (SOI layer) on the insulating layer exists.

FIG. 21 is a top view of an SOI wafer on which a mark is drawn, and FIG. 22 is a cross-sectional view of the vicinity of the mark. Furthermore, since the laser output conditions and the like are conditions designed and determined so that particles do not jump out on the Si mirror wafer, when marking on the SOI wafer in accordance with the SEMI standard, the multilayer structure and the SiO 2 Due to the action of the heat storage layer ₂ , particles are generated and the dot diameter may change. With deep marks, this problem is even more serious.

  This state is schematically shown in FIG. For example, when laser irradiation is performed on an SOI wafer having a SOI layer thickness of 100 to 200 nm and a buried insulating layer thickness of 100 to 200 nm under the same laser irradiation conditions as in the example of FIG. The diameter X1 of the recess is about 0.045 mm, the diameter X2 of the recess is about 0.04 mm, the distance X3 between the inner and outer protrusions is 0.02 mm to 0.03 mm, and the depth Y1 of the recess is 2.5 μm to 3.0 μm. The height Y2 of the inner convex portion is 1.0 μm to 1.5 μm, the height Y3 of the outer convex portion is 0.8 μm to 1.5 μm, and the concave depths Y1, Y2, and Y3 are approximate values. .

  When a character is marked on the surface of the SOI layer, it can be seen that the thickness of the character consisting of the concave portion is thick and the particles 25 are scattered around the character as shown in FIG. Even if the conditions for preventing the particles from scattering depend on the SOI layer structure and the thickness of each layer, the condition setting is very complicated and requires a lot of labor. In addition, when the laser output is weak enough to suppress the scattering of particles, the depth of the concave portion that can be dug by the laser becomes shallow, which makes it difficult to read the mark.

  An object of the present invention is to provide a semiconductor substrate that can easily read a mark, has few adhered particles, and can be easily marked, and a manufacturing method thereof.

  The present invention relates to a method for manufacturing a semiconductor substrate having a semiconductor layer provided over an insulating layer or at least one layer of different materials above a supporting substrate, wherein a mark is formed on an inclined surface in a peripheral region of the supporting substrate. A method for manufacturing a semiconductor substrate, comprising a step of forming a semiconductor substrate.

The present invention is a method of manufacturing a semiconductor substrate,
Preparing a first substrate;
Preparing a second substrate;
Forming a mark on the periphery of the second substrate;
Bonding the first substrate and the second substrate;
Removing an unnecessary portion of the first substrate to transfer a transfer layer of the first substrate.

The present invention is a method of manufacturing a semiconductor substrate,
Preparing a first substrate;
Preparing a second substrate;
Forming a mark on the periphery of the second substrate;
A step of bonding the first substrate and the second substrate so as not to be bonded at a portion having the mark;
Removing an unnecessary portion of the first substrate to transfer a transfer layer of the first substrate.

The present invention is a method of manufacturing a semiconductor substrate,
Preparing a first substrate;
Preparing a second substrate;
Forming a mark on the periphery of the second substrate;
A step of bonding the first substrate and the second substrate so that a contact edge or a bonding edge exists inward from a portion having the mark;
Removing an unnecessary portion of the first substrate to transfer a transfer layer of the first substrate.

The present invention is a method of manufacturing a semiconductor substrate,
Preparing a first substrate;
Preparing a second substrate;
Forming a mark on the periphery of the second substrate;
Bonding the first substrate and the second substrate by locally retracting the bonding edge so that the bonding edge is present inward from the portion with the mark;
Removing an unnecessary portion of the first substrate to transfer a transfer layer of the first substrate.

  The present invention is characterized in that a mark is formed in a region other than the surface region of the semiconductor layer in a semiconductor substrate having a semiconductor layer provided above the support substrate via an insulating layer.

  The present invention relates to a method for manufacturing a semiconductor substrate having a semiconductor layer provided above a support substrate with an insulating layer interposed, and includes a step of forming a mark in a region other than the surface region of the semiconductor layer. To do.

  The present invention is characterized in that a mark is formed in a region other than the surface region of the semiconductor layer in the semiconductor substrate in which the semiconductor layer is formed via at least one layer of different materials above the support substrate. To do.

  According to the present invention, in a method for manufacturing a semiconductor substrate having a semiconductor layer provided above a support substrate via at least one layer made of different materials, a step of forming a mark in a region other than the surface region of the semiconductor layer It is characterized by including.

  According to the present invention, it is possible to provide a semiconductor substrate in which an ID mark can be easily read, the number of adhered particles is small, and marking is easy.

I. Configuration of Semiconductor Substrate First, an embodiment of a semiconductor substrate according to the present invention will be described.

(Embodiment 1)
FIG. 1 shows a top surface of a part of a semiconductor substrate according to the present invention, and FIG. 2 shows a cross section taken along line AA ′.

  Reference numeral 1 is a support substrate such as a single crystal silicon wafer, 2 is a buried insulating layer such as silicon oxide, and 3 is a semiconductor layer (SOI layer) such as single crystal silicon. These constitute an SOI substrate.

  Reference numeral 5 denotes a surface region of the semiconductor layer 3 in which a semiconductor device such as an integrated circuit is manufactured. Reference numeral 6 denotes a region having a substantially flat surface in the peripheral region 13 of the semiconductor substrate, and the mark 4 is drawn in this region 6. Reference numeral 12 denotes a notch.

  The edge of the surface region 5 of the SOI layer 3 (inner edge of the peripheral region) is indicated by a circle with a radius R2. Further, the outer peripheral edge (outer edge of the peripheral region) of the substrate is indicated by a circle having a radius R1. The peripheral region 13 is outside the circle having the radius R2 and inside the circle having the radius R1.

  As will be described in detail below, a typical SOI wafer that can be obtained at present usually has an area that is several mm inside from the outer peripheral edge of the wafer and has an area in which no device is formed. This is referred to as “Edge Exclusion”.

  For example, in SIMOX, the SOI layer in the region from the outer peripheral edge to the inside several millimeters from the outer peripheral edge becomes a region having a nonstandard film thickness, defect, etc. due to the uniformity of ion implantation.

  Further, in the bonded SOI wafer, the peripheral portion of the original wafer as a starting material does not adhere to the peripheral portion of several mm, so that the peripheral portion does not have an SOI structure. Also, the edge contour of the SOI layer is not smooth. Therefore, the edge of the SOI layer is artificially removed from the beginning by a method such as patterning.

  In order to provide a mark on such an SOI wafer, it is important to mark an area that does not have an SOI structure. Therefore, when there is no SOI layer in the peripheral region as in the bonded wafer, the peripheral region 13 is marked as shown in FIGS. This method is advantageous in that it requires fewer steps than the case where the SOI layer is removed, and the number of chips produced in the SOI region does not decrease.

(Embodiment 2)
3 shows a top surface of a part of the semiconductor substrate according to the present invention, and FIG. 4 shows a cross section taken along the line BB ′.

  The exposed region 14 where the semiconductor layer (SOI layer) 3 and the insulating layer 2 are partially hollowed out and removed to expose a part of the support substrate 1 is inward from the edge of the semiconductor layer 3 when viewed from above. That is, it is formed in a region (inner region) excluding the peripheral region 13 from the support substrate 1.

  A mark 4 is drawn in the exposed area 14. In the figure, the case where an alphabet as a character is used as the mark 4 is illustrated, but a combination of a barcode, a number, a character, and a symbol may be used.

  The edge of the surface region 5 of the SOI layer 3 (inner edge of the peripheral region) is indicated by a circle with a radius R2. Further, the outer peripheral edge (outer edge of the peripheral region) of the substrate is indicated by a circle having a radius R1. In the present embodiment, a mark is formed inside a circle having a radius R2.

  In the semiconductor substrate manufacturing method according to the present embodiment, a semiconductor substrate such as an SOI wafer is prepared, and the exposed region of the semiconductor layer 3 exposed from the mask is covered with a mask except for a portion where the exposed region 14 is to be formed. A portion to be formed 14 is removed by etching or the like.

  Further, the underlying insulating layer 2 is removed by etching or the like to expose the semiconductor surface of the support substrate 1.

  The exposed area 14 is marked with a laser or the like.

  Thus, an SOI substrate as shown in FIGS. 3 and 4 is obtained.

(Embodiment 3)
In the present embodiment, marking is performed on the back surface of the support substrate.

  In the present embodiment, the mark is applied to the back surface of the support substrate of the SOI substrate in the same manner as in FIGS. 19 and 20 showing the marking on the surface of the mirror wafer. Since the mark is formed on the back surface of the support substrate, the effective area of the SOI layer on the front surface side of the support substrate is not reduced.

(Embodiment 4)
FIGS. 5 and 6 show the structure in the vicinity of the peripheral region where the mark of the semiconductor substrate according to the present embodiment is formed.

  FIG. 5 is a top view in the vicinity of the peripheral region, and FIG. 6 is a cross-sectional view in the vicinity of the peripheral region.

  Reference numeral 34 denotes an edge of the buried insulating layer 2, and 35 denotes an edge of the SOI layer 3. In this embodiment, by extending the edge 34 of the insulating layer 2 outward from the edge 35 of the SOI layer 3, the insulating layer 2 is under-etched by cleaning or the like using an etching cleaning solution, and the SOI layer causes chipping. This is not necessary. More preferably, the corners of the SOI layer 3 and the corners of the buried insulating layer 2 may be chamfered or processed to have an obtuse angle.

  The mark 4 is unevenly distributed outward in the peripheral region 13 and is drawn outward from the virtual line indicated by reference numeral 33 ′ in FIG. 5.

  Here, the line 33 'will be described with reference to FIG.

  FIG. 7 is a cross-sectional view of a bonded substrate in which two substrates are bonded to form a bonded SOI substrate. In the figure, the mark 4 is drawn outward from the position indicated by reference numeral 33. The surface on which the mark 4 is drawn is a flat and smooth surface on the upper surface of the substrate, and is not an inclined surface greatly inclined by beveling, but is a surface that is not bonded to the substrate 30 due to a minute gradient. The marking is preferably formed on such a surface. However, as long as the mark can be read, a part of the mark may be on an inclined surface by beveling.

  The edge of the bonding interface in the state where the two substrates are brought into close contact with each other is at the position indicated by reference numeral 32, and this is called a contact edge. Thereafter, when a heat treatment for increasing the bonding strength of the bonded substrate, so-called bonding annealing, is performed, the edge of the bonding interface extends to a position indicated by reference numeral 33. That is, the area of the bonding interface increases.

  Thereafter, unnecessary portions of the substrate 30 are removed, and the substrate 30 is thinned to produce an SOI substrate. On the surface of the support substrate 1 of the SOI substrate thus obtained, the position where the bonding edge 33 once existed is indicated by a virtual line 33 ′, and the position where the contact edge 32 once existed is indicated by a virtual line 32 ′. Yes.

  Reference numeral 31 indicates a position to be the edge 35 of the completed SOI layer 3. The distance L31 from the outer peripheral edge of the support substrate 1 may be 3 mm or less, more desirably, a value as small as possible further than 3 mm.

  The position of the contact edge 32 is determined depending on the shape of the outer periphery of the substrates 1 and 30 to be used by beveling. That is, the distance L32 from the outer peripheral edge of the support substrate 1 to the contact edge 32 varies depending on the shape of the outer peripheral portion by beveling. Similarly, the bonding edge 33 moves slightly.

  If irregularities and foreign particles are present near the contact edge 32 on the bonding surface of each substrate, it becomes difficult to bond there, and the contact edge 32 may also move slightly inward. . Then, the position where sufficient bonding strength can be obtained moves inward, and the edge 35 of the SOI layer 3 inevitably has to be retracted inward to a position where sufficient bonding strength can be secured. With this, the distance L31 cannot be shortened.

  The mark according to the present invention can be formed in a portion from the outer peripheral edge of the support substrate to the edge of the SOI layer, but more preferably, it is formed outside the position 32 ′ where the contact edge 32 was present. Furthermore, it is also preferable to form the bonding edge 33 outside the position 33 'where the bonding edge 33 was located, as in the present embodiment.

  Also, if the mark is formed by locally retracting at least one of the bonding edge 33 or the contact edge 32 only in the vicinity of the portion where the mark is to be formed, the effective area of the SOI layer can be unnecessarily increased. This is preferable because there is no fear of reduction.

  Although the embodiments of the semiconductor substrate of the present invention have been described above, the present invention is not limited to these embodiments, and the equivalents of the respective constituent elements are within the scope of achieving the object of the present invention. This includes those that have been replaced with.

  As the support substrate used in the present invention, a semiconductor substrate such as Si, Ge, SiC, GaAs, GaAlAs, GaN, InP is preferably used, but is limited to these materials as long as marks can be formed on the surface. Never happen.

  As the insulating layer used in the present invention, at least one selected from silicon nitride, silicon oxynitride, and the like can be used in addition to silicon oxide. The insulating layer may be a single layer or a plurality of stacked bodies. The thickness can be, for example, 1 nm to 10 μm.

  As the semiconductor layer used in the present invention, at least one semiconductor selected from Si, Ge, SiC, GaAs, GaAlAs, GaN, InP and the like is used. The semiconductor layer may be a single layer or a plurality of stacked bodies. The thickness can be, for example, 1 nm to 10 μm.

  The shape of the semiconductor substrate of the present invention is not limited to the notch wafer as shown in FIG. 1, and may be another wafer such as a wafer with an orientation flat. When an SOI substrate is used as the semiconductor substrate of the present invention, a non-bonded substrate such as a SIMOX wafer may be used, but a bonded SOI substrate is more preferable.

  The area where the mark is drawn may be near the notch or the orientation flat, at a position facing it, or at any other position.

  As described above, the marking is performed in the peripheral region, and more preferably, the surface in the peripheral region may be a substantially flat region or may be a region slightly inclined by beveling. Alternatively, the exposed region may be marked by removing a part of the semiconductor layer.

  Marking may be performed with an Nd: YAG laser, a CO2 laser, or the like. Alternatively, a diamond pen can be used.

  The depth of the concave portion of the mark is, for example, 1 μm to several hundred μm, and this depth can be adjusted by laser output or the like.

  The mark may be at least one selected from the group of numbers, characters, symbols, barcodes, and the like, and may be a mixture of these. Examples of characters include alphabets, kana, and Greek characters.

  For specific applications, the SEMI standard may not be applied. The numbers, characters, and symbols that serve as marks may be arranged in a straight line or may be curved along the outer peripheral edge of the wafer. When the peripheral removal region formed by removing the semiconductor layer is narrow or when the number of digits of the mark is large, the curve along the outer peripheral edge is less likely to interfere with the SOI layer.

  The marked wafer is then packaged and shipped as it is. Alternatively, the products are packaged and shipped after at least one of cleaning and inspection.

  Alternatively, the marked wafer may be input to the device manufacturing process as it is, or may be input to the device manufacturing process after at least one of cleaning and inspection.

II. Next, an embodiment of a method for manufacturing a semiconductor substrate according to the present invention for manufacturing the above-described semiconductor substrate will be described.

  The method for manufacturing a semiconductor substrate of the present invention includes a step of preparing a semiconductor substrate having a semiconductor layer provided over an insulating layer via an insulating layer and forming a mark in a region other than the surface region of the semiconductor layer. .

  As the semiconductor substrate used in the present invention, those described above are used, and more preferably, a non-bonded SOI substrate having an insulating layer formed by oxygen and / or nitrogen ion implantation and heat treatment, It is formed by a method including the steps of implanting hydrogen and / or inert gas ions into a substrate, bonding the first substrate to a second substrate to be a supporting substrate, and separating in a separation layer formed by the ion implantation. A bonded SOI substrate having a semiconductor layer formed by transferring a non-porous semiconductor layer formed over a porous body to a supporting substrate may be used.

  In addition, another method for manufacturing a semiconductor substrate of the present invention includes a step of marking a support substrate such as a handle wafer before forming an SOI structure.

(Embodiment 5)
A method for manufacturing a semiconductor substrate will be described with reference to FIGS.

  The surface of the first substrate 30 such as a single crystal silicon wafer is anodized to form a porous layer 37 such as porous silicon. If necessary, after the inner wall of the porous silicon layer is thermally oxidized to form a silicon oxide protective film, heat treatment is performed in a hydrogen atmosphere to seal the surface opening on the surface of the porous layer 37.

  A non-porous semiconductor layer 38 such as single crystal silicon is formed on the porous layer 37 by epitaxial growth such as CVD. This semiconductor layer 38 becomes a transfer layer.

  Further, the insulating layer 39 is formed by thermally oxidizing the first substrate 30 as necessary.

  Thus, a structure as shown in FIG. 8A is obtained through steps S11 and S12 of FIG.

  Next, in step S21, a second substrate such as a single crystal silicon wafer is prepared, and in step S22, marking is performed on the peripheral portion of the surface. Further, if necessary, the surface of the second substrate may be thermally oxidized to form an insulating film. Alternatively, marking may be applied to an arbitrary part on the back surface of the second substrate.

  A method for manufacturing a single crystal silicon wafer generally includes a slicing step for a single crystal silicon ingot, a lapping step for a sliced wafer, a surface etching step for the lapped wafer, and a polishing step for the etched wafer. In the case of deep marking, marking is performed before or after the lapping process, and in the case of shallow marking, it is performed after the polishing process.

  In step S13, bonding is performed as shown in FIG. Furthermore, if necessary, heat treatment is performed in an oxidizing atmosphere to increase the bonding strength. When marking is performed on the surface side, as described above, it is preferable that the marking is formed outside the contact edge in step S13 or outside the bonding edge.

  In step S14, unnecessary portions of the first substrate are removed. Specifically, as shown in FIG. 8C, the non-porous portion 36 on the back surface side of the first substrate is removed from the bonded substrate by at least one method selected from grinding, polishing, etching, separation, and the like. remove.

  Further, the porous layer 37 remaining on the front surface (former back surface) of the semiconductor layer 38 bonded to the second substrate is removed by polishing, etching, hydrogen annealing, or made non-porous. Thus, the transfer of the semiconductor layer 38 is completed.

  In step S15, the peripheral portion of the SOI substrate is formed. Specifically, as shown in FIG. 8E, an etching mask such as a sealant or a photoresist is applied on the exposed surface of the semiconductor layer 38, and the edge of the semiconductor layer 38 serving as the SOI layer is shown in FIGS. The peripheral portion of the semiconductor layer 38 is removed by etching so that the described position 31 is obtained. Further, the peripheral portion of the insulating layer 39 is also removed by etching. Instead of etching at this time, molding may be performed by polishing.

  In this way, an SOI substrate as shown in FIG. 8F is obtained.

  The mark on the SOI substrate is drawn at a position as shown in FIGS.

(Embodiment 6)
A method for manufacturing a semiconductor substrate will be described with reference to FIGS.

  The difference from Embodiment 5 described above is that the step of forming a mark is in the middle of the step of removing unnecessary portions of the first substrate.

Similarly to the embodiment, the first substrate that has undergone the steps S11 and S12 is bonded to a second substrate that is not marked. (Process S13)
In step S14, a part of the unnecessary portion of the first substrate is removed. Specifically, as shown in FIG. 8C, the non-porous portion 36 on the back surface side of the first substrate is removed from the bonded substrate by at least one method selected from grinding, polishing, etching, separation, and the like. remove.

  Thereafter, in step S15, marking is performed on the peripheral portion on the surface side of the second substrate. At this time, even if foreign matter scattered by the marking adheres to the surface side of the second substrate, the porous layer 37 on the surface side is removed in the next step, so the surface region of the semiconductor layer that becomes the SOI layer is It becomes difficult to be contaminated by the foreign matter. Or you may mark on the back surface of a 2nd board | substrate.

  Further, in step S16, the porous layer 37 remaining on the front surface (former back surface) of the semiconductor layer 38 bonded to the second substrate is removed by polishing, etching, and hydrogen annealing. Thus, the transfer of the semiconductor layer 38 is completed.

  Thereafter, in step S17, the peripheral portion of the SOI substrate is formed.

  In this way, an SOI substrate as shown in FIG. 8F is obtained. The mark on the SOI substrate is drawn at a position as shown in FIGS.

(Embodiment 7)
A method for manufacturing a semiconductor substrate will be described with reference to FIGS.

  The difference from the above-described embodiment 5 is that the step of forming the mark is performed after the step of removing the unnecessary portion of the first substrate and before the step of forming the peripheral portion.

Similarly to the embodiment, the first substrate that has undergone the steps S11 and S12 is bonded to a second substrate that is not marked. (Process S13)
In step S14, unnecessary portions of the first substrate are removed. Specifically, as shown in FIG. 8C, the non-porous portion 36 on the back surface side of the first substrate is removed from the bonded substrate by at least one method selected from grinding, polishing, etching, separation, and the like. remove. Further, as shown in FIG. 8D, the porous layer 37 remaining on the front surface (former back surface) of the semiconductor layer 38 bonded to the second substrate is polished, etched, and hydrogen annealed. Removed or made non-porous. Thus, the transfer of the semiconductor layer 38 is completed.

  When the non-porous portion is separated, the porous layer may be cracked at the semiconductor layer 38 side interface, and the porous layer may not remain on the semiconductor layer 38 after the separation.

  Thereafter, in a state where the mask MK is applied on the surface region of the semiconductor layer 38 as shown in FIG. 8E, marking is performed on the peripheral portion on the surface side of the second substrate in step S15. At this time, even if the foreign matter scattered by the marking adheres to the surface side of the second substrate, the mask MK on the surface side is removed in the next step, so the surface region of the semiconductor layer to be the SOI layer It becomes difficult to be contaminated by. Or you may mark on the back surface of a 2nd board | substrate.

  Further, in step S16, the peripheral portion of the SOI substrate is formed using the mask MK.

  In this way, an SOI substrate as shown in FIG. 8F is obtained. The mark on the SOI substrate is drawn at a position as shown in FIGS.

(Embodiment 8)
A method for manufacturing a semiconductor substrate will be described with reference to FIGS.

  The difference from the seventh embodiment described above is that the mark forming step performs the same marking as that of the seventh embodiment without removing the mask MK used for forming after forming the peripheral portion.

  Also in this embodiment, an SOI substrate as shown in FIG. 8F is obtained in this way.

  The mark on the SOI substrate is drawn at a position as shown in FIGS.

(Embodiment 9)
A method for manufacturing a bonded semiconductor substrate using an ion-implanted layer as a separation layer will be described with reference to FIGS.

  The surface of the first substrate 30 such as a single crystal silicon wafer is thermally oxidized to form an insulating layer 39 such as silicon oxide. An ion implantation layer 40 in which ions of an inert gas such as hydrogen ions, helium ions, or neon ions are implanted to a predetermined depth, and the concentration of ion species implanted in the vicinity of the depth is locally increased. Form. The semiconductor layer 38 on the ion implantation layer 40 is a transfer layer. The structure of the first substrate 30 obtained in this way is shown in FIG.

  On the other hand, a second substrate such as a single crystal silicon wafer is prepared, and marking is performed on the peripheral portion on the surface side. Or you may mark on the back surface side of a 2nd board | substrate.

  The first substrate and the second substrate are bonded so that the semiconductor layer 38 is on the inner side. Thus, a structure as shown in FIG. 13B is obtained.

  Next, when heat treatment is performed at a temperature of 400 ° C. to 600 ° C. or higher, the bonding strength is increased, cracks are generated in the ion implantation layer 40, and the first substrate portion 36 is separated from the bonded substrate, As shown in FIG. 13E, the semiconductor layer 38 is transferred to the second substrate.

  The exposed separation surface of the semiconductor layer 38 is polished. At this time, the peripheral portions of the layers 38 and 39 may be removed at the same time so that the structure shown in FIG. Alternatively, hydrogen annealing may be performed instead of polishing, or hydrogen annealing after polishing may be performed.

  Then, the peripheral part of the SOI substrate is formed. Specifically, as shown in FIG. 13E, an etching mask MK such as a sealant or a photoresist is applied on the exposed surface of the semiconductor layer 38, and the edge of the semiconductor layer 38 serving as the SOI layer is shown in FIGS. The peripheral portion of the semiconductor layer 38 is removed by etching so as to be the position 31 described in the above. Further, the peripheral portion of the insulating layer 39 is also removed by etching. Instead of etching at this time, molding may be performed by polishing.

  In this way, an SOI substrate as shown in FIG. 13F is obtained. The mark on the SOI substrate is drawn at a position as shown in FIGS.

  Further, the process of FIG. 13 (c) may be shifted to the process of (e) without going through (d).

(Embodiment 10)
This embodiment is different from the above-described embodiment 9 in the timing for marking. The rest is the same as in the ninth embodiment, and the peripheral region on the surface side of the support substrate 1 is removed before the peripheral portion of the semiconductor layer 38 is removed in the state covered with the mask MK as shown in FIG. Mark the

  In this way, an SOI substrate as shown in FIG. 13F is obtained. The mark on the SOI substrate is drawn at a position as shown in FIGS.

  Or you may mark on the back surface of a support substrate.

(Embodiment 11)
This embodiment is different from the above-described embodiment 9 in the timing for marking. Otherwise, this embodiment is the same as the ninth embodiment. In the state covered with the mask MK as shown in FIG. 13E, after the peripheral portion of the semiconductor layer 38 is removed, the supporting substrate is removed before the mask MK is removed. Marking is performed on the peripheral region on the surface side of 1.

  In this way, an SOI substrate as shown in FIG. 13F is obtained. The mark on the SOI substrate is drawn at a position as shown in FIGS.

  Or you may mark on the back surface of a support substrate.

Embodiment 12
A method for manufacturing a semiconductor substrate by a non-bonding method will be described with reference to FIGS.

  In step S11 of FIG. 15, a semiconductor substrate 1 such as a single crystal silicon wafer is prepared as shown in FIG.

  Then, in step S12 of FIG. 15, marking is performed on the peripheral region on the surface side of the semiconductor substrate. Alternatively, marking can be applied to the back side of the semiconductor substrate.

  As shown in FIG. 14B, the surface of the semiconductor substrate 1 is thermally oxidized to form an insulating layer 41 such as silicon oxide.

  In step S13 of FIG. 15, an insulator-forming ion species such as oxygen ions is implanted to a predetermined depth, and an ion implantation layer in which the concentration of the ion species implanted in the vicinity of the depth is locally increased is formed. To do. Here, heat treatment is performed to form a buried insulating layer 2 made of a compound of implanted oxygen and silicon. The semiconductor layer 3 on the insulating layer 2 is an SOI layer. The structure of the SOI substrate thus obtained is shown in FIG.

  Then, in step S14 of FIG. 15, if the insulating layer 41, which is an unnecessary part and is at least on the surface side of the SOI layer, is peeled off, the SOI substrate with the marking is obtained. When marking is performed on the surface side, the mark portion also has an uneven SOI structure by ion implantation and heat treatment after marking, and the mark can be recognized from the surface side.

  In this case, the step shown in FIG. 14D is not necessary.

  As a modification, a mark having no SOI structure can be formed in the peripheral portion on the surface side by performing ion implantation while avoiding the marked portion.

(Embodiment 13)
A method for manufacturing a semiconductor substrate will be described with reference to FIGS. The difference of this embodiment from the above-described embodiment is the timing of marking, and the other points are the same as those of the twelfth embodiment.

  In step S11 of FIG. 16, a semiconductor substrate 1 such as a single crystal silicon wafer is prepared as shown in FIG.

  As shown in FIG. 14B, the surface of the semiconductor substrate 1 is thermally oxidized to form an insulating layer 41 such as silicon oxide.

  In step S12 of FIG. 16, an ion-implanted layer in which an insulator-forming ion species such as oxygen ions is implanted to a predetermined depth, and the concentration of the ion species implanted in the vicinity of the depth is locally high. Form. Here, heat treatment is performed to form a buried insulating layer 2 made of a compound of implanted oxygen and silicon. The semiconductor layer 3 on the insulating layer 2 is an SOI layer. The structure of the SOI substrate thus obtained is shown in FIG.

  Then, in step 13 of FIG. 16, as shown in FIG. 14D, a mask MK is applied, and if necessary, the insulating layer 41 is removed and marking is performed. At this time, the concave portion of the mark passes through the semiconductor layer 3 and reaches below the insulating layer 2.

  In step S14 of FIG. 16, as shown in FIG. 14E, the mask MK and unnecessary insulating layer 41 are removed to obtain an SOI substrate.

  In this case, even if particles due to laser marks are scattered, the surface of the SOI layer is protected by the mask, so that particle contamination can be prevented.

(Embodiment 14)
A method for manufacturing a semiconductor substrate will be described with reference to FIGS. The difference of this embodiment from the above-described embodiment is the timing of marking, and the other points are the same as those of the thirteenth embodiment.
Steps S11 and S12 in FIG. 17 are the same as those in the thirteenth embodiment.
In step 13 of FIG. 17, the unnecessary insulating layer 41 is removed from the SOI substrate thus obtained as shown in FIG. 14E to obtain an SOI substrate.
In step S14 of FIG. 17, the surface region of the semiconductor layer is covered with a mask, and marking is performed on the peripheral region on the surface side of the SOI substrate. At this time, the concave portion of the mark passes through the semiconductor layer 3 and reaches below the insulating layer 2.
In this case, even if particles due to laser marks are scattered, the surface of the SOI layer is protected by the mask, so that particle contamination can be prevented.

(Embodiment 15)
With reference to FIG. 8 again, a method for manufacturing a bonded semiconductor substrate will be described.

  A P-type or N-type first single crystal Si substrate having a specific resistance of 0.01 Ω · cm is prepared as a first substrate, anodized in a HF-containing solution, and a porous layer 37 serving as a separation layer is formed. Form.

Anodizing conditions for forming the porous layer 37 made of a single porous silicon are, for example, as follows.
Current density: 7 (mA · cm ⁻² )
Anodizing solution: hydrofluoric acid: water: ethanol = 1: 1: 1
Time: 11 (minutes)
Porous layer thickness: 12 (μm)
The thickness of the porous layer is not limited to this, and can be changed from several hundred μm to about 0.1 μm by adjusting the formation time.

Or when forming the porous layer which consists of a several porous silicon layer, you may perform the 2nd step anodization following the 1st step anodization as follows.
First stage current density: 7 (mA · cm ⁻² )
Anodizing solution: hydrofluoric acid: water: ethanol = 1: 1: 1
Time: 5 (minutes)
Thickness of the first porous Si layer: 5.5 (μm)
Second stage current density: 30 (mA · cm ⁻² )
Anodizing solution: hydrofluoric acid: water: ethanol = 1: 1: 1
Time: 10 (seconds)
Thickness of the second porous Si layer: 0.2 (μm)

  The porous Si layer of the surface layer previously anodized at a low current is used to form a high quality epitaxial Si layer, and the lower porous Si layer anodized at a high current later is a layer that facilitates separation. Separation of functions used as. Therefore, the thickness of the porous Si layer is not limited to this, and it can be used from several hundred μm to about 0.1 μm.

  Even if the third and subsequent porous layers are formed after the formation of the second porous Si layer, there is no problem.

This substrate is oxidized at, for example, 300 ° C. to 600 ° C. in an oxygen atmosphere. By this oxidation, the inner wall of the porous silicon hole is covered with a protective film made of a thermal oxide film. The surface of the porous layer 37 is treated with hydrofluoric acid, and only the oxide film on the surface of the porous layer 37 is removed, leaving the oxide film on the inner wall of the hole. An epitaxial growth layer 38 is formed thereon by CVD. The CVD conditions at this time are as follows, for example.
Source gas: SiH ₂ Cl ₂ / H ₂
Gas flow rate: 0.5 / 180 l / min
Gas pressure: 1.1 × 10 ⁴ Pa (about 80 Torr)
Temperature: 950 ° C
Growth rate: 0.3 μm / min

Prior to epitaxial growth, a heat treatment (pre-baking of the porous layer 37 is performed in an H ₂ atmosphere in the epitaxial apparatus. This is necessary for improving the crystal quality of the epitaxial growth layer 38. Actually, this treatment is effective for the epitaxial growth layer. The crystal defects 38 can be reduced to 10 ⁴ cm ⁻² or less, and the epitaxially grown layer 38 thus obtained becomes a transfer layer.

Further, as the insulating layer 39, a ₂₀ nm to _{2 [} mu] m SiO2 layer is formed on the surface of this epitaxial growth layer by thermal oxidation. Thus, the structure shown in FIG. 8A is obtained.

  After the surface of the insulating layer 39 and the surface of the second Si substrate 1 prepared separately are brought into contact with each other, heat treatment is performed at a temperature of 1100 ° C. for 2 hours to perform bonding. Thus, the structure shown in FIG. 8B is obtained.

  The porous layer 37 is removed from the multilayer structure thus obtained to obtain an SOI substrate in which the epitaxial growth layer 38 is transferred onto the second substrate 1. For this purpose, the portion 36 of the first Si substrate is removed by grinding, polishing, etching or the like to expose the porous layer 37, and then the porous layer 37 is removed by etching. Alternatively, the multilayer structure is separated in the porous layer 37, and if the porous body remains on the separation surface of the epitaxial growth layer 38 transferred on the second substrate 1, it is removed by etching or hydrogen annealing. To do.

Separation methods include
Method of inserting wedges between substrates Method of pulling wafers together Method of applying shear force Method of using fluid wedge effect by water jet, gas jet, hydrostatic fluid, etc. Method of applying ultrasonic waves Method of thermal stress of temperature rising and cooling There is.
Thus, the structure shown in FIG. 8C is obtained.

  Thereafter, the porous Si layer 37 remaining on the second substrate 1 is selectively etched with a mixed solution of hydrofluoric acid, hydrogen peroxide solution, and water. The semiconductor layer 38 made of non-porous single crystal Si is left unetched, and the porous Si is completely removed by selective etching using the layer 38 as an etch stop material. Thus, the structure shown in FIG. 8D is obtained.

  The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount in the non-porous layer (several tens of angstroms) ) Is a practically negligible film thickness reduction.

  That is, the semiconductor layer 38 made of single crystal Si having a thickness of 0.2 μm could be formed on the insulating layer 39. There was no change in the single crystal Si layer even by selective etching of porous Si. When the film thickness of the formed semiconductor layer 38 is measured at 100 points on the entire surface, the uniformity of the film thickness is about 201 nm ± 4 nm.

  As a result of cross-sectional observation with a transmission electron microscope, it can be confirmed that no new crystal defects have been introduced into the Si layer and that good crystallinity is maintained.

  Further, when heat treatment is performed at 1100 ° C. in hydrogen, the surface becomes smooth.

  Similar results can be obtained when the oxide film is formed not on the epitaxial layer surface but on the second substrate surface, or on both surfaces.

  As shown in FIG. 8 (e), a mask MK is applied to cover the surface region of the semiconductor layer 38, and then the peripheral region having a width of 1 mm to 3 mm from the outer peripheral end in order to adjust the shape of the peripheral portion. The semiconductor layer 38 and the insulating layer 39 are removed by patterning. This peripheral patterning may be omitted.

  A predetermined number of alphanumeric characters are printed by a laser mark device near the notch or orientation flat in the surrounding area. As described above, it may be a symbol or a barcode.

  The characters do not have to conform to the SEMI standard, and the size of the characters can be adjusted in units of about 0.8 mm in the case of a general laser mark device, so it can be small or large so that it can be easily read. I can do it.

  Further, the heat treatment (hydrogen annealing) in a hydrogen atmosphere for smoothing the surface may be performed after the laser mark is applied.

  Thereafter, the mask MK is peeled off, and the SOI substrate is cleaned and inspected and shipped.

  Further, the porous Si remaining on the substrate portion 36 side of the first substrate is then selectively etched while being stirred with a mixed solution of hydrofluoric acid, hydrogen peroxide solution, and water. Thereafter, it can be used as the first substrate 30 or the second substrate 1 again after being subjected to surface treatment such as hydrogen annealing or surface polishing.

(Embodiment 16)
Referring to FIG. 13 again, a method for manufacturing a bonded semiconductor substrate using an ion implantation layer as a separation layer will be described.

An insulating layer 39 made of SiO ₂ of 200 nm is formed on a first substrate 30 such as a single crystal Si wafer by thermal oxidation.

5 × 10 ¹⁶ cm ⁻² ions of hydrogen are implanted at 50 keV through the insulating layer 39 on the surface. Instead of hydrogen ions, ions of an inert gas such as helium may be used. Thus, a structure as shown in FIG. 13A is obtained.

  The surface of the second substrate 1 such as a single crystal Si wafer prepared separately is superimposed and brought into contact with the surface of the insulating layer. Thus, a structure as shown in FIG. 13B is obtained.

  After that, when annealed at 600 ° C., it is separated into two pieces in the vicinity of the projection range of ion implantation (ion implantation layer 40). Since the ion implantation layer 40 when separated by the heat treatment is porous, the separated surface is rough. The surface on the second substrate 1 side can be smoothed by at least either polishing or hydrogen annealing. Thus, a structure as shown in FIG. 13C or 13D is obtained.

  Furthermore, it is also preferable to perform heat treatment (bonding annealing) for increasing the bonding strength before or after smoothing, if necessary.

  That is, the semiconductor layer 38 made of non-porous single crystal Si having a thickness of 0.2 μm can be formed on the insulating layer 39. When the film thickness of the formed semiconductor layer 38 is measured at 100 points on the entire surface, the uniformity of the film thickness is about 201 nm ± 6 nm.

  Further, heat treatment was performed in hydrogen at 1100 ° C. for 1 hour, and the surface roughness was evaluated by an atomic force microscope. The mean square roughness in a 50 μm square region was about 0.2 nm, which is usually a commercially available single unit. This is equivalent to a crystal Si mirror wafer.

  As a result of cross-sectional observation with a transmission electron microscope, it can be confirmed that no new crystal defects are introduced into the semiconductor layer 38 and that good crystallinity is maintained.

  Thereafter, in order to adjust the shape of the peripheral portion, as shown in FIG. 13E, a mask MK that exposes the semiconductor layer 38 and the insulating layer 39 in the peripheral region having a width of 3 mm from the outer peripheral end is provided and exposed. The part is removed by patterning.

  A 12-digit alphanumeric character is printed by a laser mark device in the vicinity of a notch or orientation flat in a 3 mm area on the outer periphery. As described above, it may be a symbol or a barcode. At this time, there is no increase in particles on the SOI wafer.

  The laser power at that time is about 220 mW. Of course, the power should be adjusted according to the depth and shape of the mark.

  The size of the alphanumeric character is the SEMI standard described above. In the case of a general laser mark apparatus, the character size can be adjusted in steps of about 0.8 mm, so it can be small or large so that it can be easily read.

  Thereafter, the mask MK is removed, cleaning and inspection are performed, and an SOI substrate having a structure as shown in FIG.

  At the same time, the ion implantation layer remaining on the substrate portion 36 side of the first substrate was then flattened by at least one of etching, polishing, and annealing, and the ion implantation layer was also removed. The substrate can be loaded again as the first substrate 30 or as the second substrate 1.

  As a modification, in this embodiment, single crystal Si may be epitaxially grown on the first substrate by a CVD method in advance by 0.50 μm.

The growth conditions at that time are, for example, as follows.
Source gas: SiH ₂ Cl ₂ / H ₂
Gas flow rate: 0.5 / 180 l / min
Gas pressure: 1.1 × 10 ⁴ Pa (about 80 Torr)
Temperature: 950 ° C
Growth rate: 0.30 μm / min

  In this case, when the substrate is introduced again as a first substrate, it can be reused semi-permanently by compensating for the reduced thickness of the wafer with the epitaxial layer. That is, in the second and subsequent repetitions, the epitaxial film thickness is not 0.50 μm but the wafer thickness reduction, and the ion-implanted layer is formed inside the epitaxial layer.

Furthermore, after performing ion implantation, separation may be performed by applying an external force for separation and growing a crack from the edge of the bonded substrate without separation by heat treatment, as in Embodiment 16. Good.
Moreover, you may perform a smoothing process after marking.

(Embodiment 17)
Referring to FIGS. 14A, 14B, 14C, and 14E again, a method for manufacturing a semiconductor substrate by a non-bonding method will be described.

  As shown in FIGS. 14A and 14B, a substrate 1 made of a first single crystal CZ-Si wafer is prepared, and an oxide film 41 made of SiO 2 of 50 nm is formed thereon by thermal oxidation. The purpose of this oxide film is to prevent surface roughness during ion implantation, and may not be present.

4 × 10 ¹⁷ cm ⁻² ions are implanted through O ² at 180 keV through the surface oxide film 41. The temperature at the time of injection was 550 ° C. As a result, an oxygen ion implanted layer having a concentration peak near the interface between the epitaxial layer and the original substrate is formed. Nitrogen ions may be implanted in addition to or in place of oxygen ions.

Thereafter, the substrate is heat-treated at 1350 ° C. for 4 hours in an O ₂ (10%) / Ar atmosphere.

Thereafter, a heat treatment is further performed in an O ₂ (70%) / Ar atmosphere at 1350 ° C. for 4 hours to complete an SOI substrate having an SOI layer of 300 nm / buried oxide film of 90 nm as shown in FIG. .

A mask MK is applied to the surface region of the semiconductor layer 3 as shown in FIG.
When the center of the wafer is (0, 0) with the notch of the substrate facing up,
X: -9.25 to +9.25 mm
Y: +93.7 to +96.5 mm
The semiconductor layer 3 and the insulating layer 2 in the area exposed from the mask having a height of 2.8 mm and a length of 18.5 mm are patterned and etched to expose the underlying support substrate.

  With the mask covering the surface area of the semiconductor layer 3, a 10-digit ID code is printed on the printing area by a laser mark device.

The laser power at that time is 220 mW, and the size of alphanumeric characters is the SEMI standard. Since the character size can be adjusted in steps of about 0.8 mm, it can be small or large so that it can be easily read. In that case, the size of the region where the SOI structure is removed by patterning may be changed. In particular, when the character is made smaller, the area removed by patterning is increased, so the area is made smaller and the number of chips taken is increased.
If it is a specific application, it may not be SEMI standard.

Then, after removing the mask MK and then removing the surface oxide film 41, an SOI wafer having an SOI layer of 200 nm / buried oxide film of 120 nm is completed. Thereafter, hydrogen annealing may be further performed. ((E) in FIG. 14)
After that, it is cleaned and inspected before being shipped in a package.

  As described above, the marking method used in the present invention described by taking each embodiment as an example includes marking using a laser such as an Nd: YAG laser or a CO2 laser, or a diamond pen. Further, after the mark is formed, the convex portion of the mark may be removed by polishing or the like at an appropriate timing.

  Although the mask used in each embodiment is very effective in preventing particles on the SOI layer surface, marking can be performed without using a mask, and a particle removal process can be performed thereafter. The particle removal process includes wet cleaning, brush cleaning, scrub cleaning, ultrasonic cleaning, polishing, etching, and the like.

In the case of the bonding method, before bonding, the bonded surface is plasma-treated and rinsed with pure water, or bonded, or after bonding, in an atmosphere containing at least one of oxygen and nitrogen It is also preferable to perform bonding annealing at 400 ° C. to 1100 ° C.
The heat treatment in a hydrogen atmosphere may be performed at 800 ° C. to 1150 ° C. or higher.

Example 1
As shown in FIGS. 3 and 4, when a wafer center 100 is set to (0, 0) with a notch facing up on a commercially available 8-inch SOI wafer,
X: -9.25 to +9.25 mm
Y: +93.7 to +96.5 mm
The portions of the semiconductor layer 3 and the insulating layer 2 (portions other than the edge exclusion) having a width L2 of 2.8 mm and a length L1 of 18.5 mm at the position are removed by etching to expose the underlying support substrate. It was.

  A 10-digit ID code was printed on the exposed area 14 using a NEC laser marker SL473F.

  The laser power at that time was 220 mW.

Alphanumeric size is
Height: 1.624 ± 0.025mm
Width: 0.812 ± 0.025mm
Line thickness: 0.200 + 0.050mm to 0.200-0.150mm
Character spacing: 1.420 ± 0.025mm
SEMI standard.

  Since the character size can be adjusted in steps of about 0.8 mm, it can be small or large so that it can be easily read. In that case, the size of the region where the SOI layer and the insulating layer are removed by patterning may be changed. In particular, when the characters are made smaller, the area removed by patterning is increased, so the print area can be reduced and the number of chips taken can be increased.

(Example 2)
As shown in FIGS. 1 and 2, a 12-digit ID code was printed by a laser mark device on the peripheral region 13 exposed by the support substrate under the commercially available bonded SOI wafer. At that time, 12-digit characters were printed in a straight line.
The laser power was 220 mW.

Alphanumeric size is
Height: 1.624 ± 0.025mm
Width: 0.812 ± 0.025mm
Line thickness: 0.200 + 0.050mm to 0.200-0.150mm
Character spacing: 1.420 ± 0.025mm
SEMI standard.

  Since the character size can be adjusted in steps of about 0.8 mm, it can be small or large so that it can be easily read. Again, smaller characters are preferred when the width of the peripheral removal region becomes narrower.

(Example 3)
A 12-digit ID code was printed with a laser mark device in a peripheral region where a support substrate underlying a commercially available SOI wafer was covered only with an oxide film.

  The laser power at that time was 300 mW. The concave portion formed by the laser reached the support substrate through the oxide film.

Alphanumeric size is
Height: 1.624 ± 0.025mm
Width: 0.812 ± 0.025mm
Line thickness: 0.200 + 0.050mm to 0.200-0.150mm
Character spacing: 1.420 ± 0.025mm
SEMI standard.

Since the character size can be adjusted in steps of about 0.8 mm, it can be small or large so that it can be easily read. Again, smaller letters are preferred when marginal removal becomes narrower.
If it is a specific application, it may not be SEMI standard.

Example 4
A P-type first single crystal Si substrate having a specific resistance of 0.01 Ω · cm was anodized in an HF solution.

The anodizing conditions were as follows.
Current density: 7 (mA · cm ⁻² )
Anodizing solution: hydrofluoric acid: water: ethanol = 1: 1: 1
Time: 11 (minutes)
Thickness of porous Si layer: 12 (μm)
The thickness of the porous Si layer is not limited to this, and can be selected from several hundred μm to about 0.1 μm.

This substrate was oxidized in an oxygen atmosphere at 400 ° C. for 1 hour. By this oxidation, the inner walls of the porous Si holes were covered with a thermal oxide film. The surface of this porous Si layer is treated with hydrofluoric acid to leave only the oxide film on the surface of the porous Si layer, leaving an oxide film on the inner wall of the hole, and then single crystal Si is deposited on the porous Si by a CVD method. The epitaxial growth was 0.3 μm. The growth conditions are as follows.
Source gas: SiH ₂ Cl ₂ / H ₂
Gas flow rate: 0.5 / 180 l / min
Gas pressure: 1.1 × 10 ⁴ Pa (about 80 Torr)
Temperature: 950 ° C
Growth rate: 0.3 μm / min
Prior to epitaxial growth by introducing source gas, heat treatment (pre-baking) was performed in an epitaxial apparatus in an H2 atmosphere.

Further, as the insulating layer, a 200 nm oxide film (SiO ₂ layer) was formed on the surface of the epitaxial Si layer by thermal oxidation.

The surface of the second Si substrate prepared separately from the surface of the SiO ₂ layer was placed in contact with each other, and then heat-treated at a temperature of 1100 ° C. for 2 hours in an oxygen-containing atmosphere to perform bonding.

  Most of the bonded substrate board formed as described above on the first substrate side was ground, and then the remaining part was removed by reactive ion etching to expose a porous Si layer.

Thereafter, the porous Si layer transferred on the second substrate was etched while stirring with a mixed solution of hydrofluoric acid having an HF concentration of 49 wt%, hydrogen peroxide water having an H ₂ O ₂ concentration of 30 wt%, and water. Single crystal Si remained without being etched. The porous Si was selectively etched and completely removed.

  Thus, a single crystal Si layer having a thickness of 0.2 μm was formed on the Si oxide film. There was no change in the single crystal Si layer even by selective etching of porous Si. When the film thickness of the formed single crystal Si layer was measured at 100 points on the entire surface, the uniformity of the film thickness was 201 nm ± 4 nm.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the Si layer and that good crystallinity was maintained.

  Further, hydrogen annealing was performed in hydrogen at 1100 ° C. for 1 hour, and the surface roughness was evaluated by an atomic force microscope. The average square roughness in a 50 μm square region was about 0.2 nm, and was usually commercially available Si. It was equivalent to a wafer.

Thereafter, in order to adjust the shape of the peripheral portion was removed by patterning the Si layer and SiO ₂ layer from the outer peripheral edge to the peripheral region of width 3 mm.

  A 12-digit alphanumeric character was printed with a laser mark device in the vicinity of the notch in the peripheral area of 3 mm width. At that time, there was no increase in particles on the SOI wafer.

(Example 5)
A P-type first single crystal Si substrate having a specific resistance of 0.01 Ω · cm was anodized in an HF solution.

The anodizing conditions were as follows.
First stage current density: 7 (mA · cm ⁻² )
Anodizing solution: hydrofluoric acid: water: ethanol = 1: 1: 1
Time: 5 (minutes)
The thickness of the first porous Si layer on the surface side: 5.5 (μm)
Second stage current density: 30 (mA · cm−2)
Anodizing solution: hydrofluoric acid: water: ethanol = 1: 1: 1
Time: 10 (seconds)
Thickness of the second porous Si layer below the first porous Si layer: 0.2 (μm)

This substrate was oxidized in an oxygen atmosphere at 400 ° C. for 1 hour. Due to this oxidation, the inner walls of the pores of the first and second porous Si layers were covered with a thermal oxide film. The surface of this porous Si layer is treated with hydrofluoric acid to leave only the oxide film on the surface of the porous Si layer, leaving an oxide film on the inner wall of the hole, and then single crystal Si is deposited on the porous Si by a CVD method. The epitaxial growth was 0.3 μm. The growth conditions are as follows.
Source gas: SiH ₂ Cl ₂ / H ₂
Gas flow rate: 0.5 / 180 l / min
Gas pressure: 1.1 × 10 ⁴ Pa (about 80 Torr)
Temperature: 950 ° C
Growth rate: 0.3 μm / min
Prior to epitaxial growth, heat treatment was performed in an epitaxial apparatus in an H ₂ atmosphere. Actually, the crystal defects of the epi layer could be reduced to 10 ⁴ cm ⁻² or less by this treatment.

Further, as the insulating layer, a 200 nm oxide film (SiO ₂ layer) was formed on the surface of the epitaxial Si layer by thermal oxidation.

The SiO ₂ layer surface and the surface of a second Si substrate prepared separately were superposed and brought into contact with each other, and then heat treated at a temperature of 1100 ° C. for 2 hours for bonding.

  The bonded substrate formed as described above was separated in the second porous layer Si layer along the interface between the first and second porous Si layers. As a separation method, a method of inserting a solid wedge and a method of inserting a water wedge by a water jet were used.

Thereafter, the porous Si layer transferred on the second substrate was selectively etched while stirring with a mixed solution of hydrofluoric acid having an HF concentration of 49 wt%, hydrogen peroxide water having an H ₂ O ₂ concentration of 30 wt%, and water. .

  Thus, a single crystal Si layer having a thickness of 0.2 μm was formed on the Si oxide film. There was no change in the single crystal Si layer even by selective etching of porous Si. When the film thickness of the formed single crystal Si layer was measured at 100 points on the entire surface, the uniformity of the film thickness was 201 nm ± 4 nm.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the Si layer and that good crystallinity was maintained.

  Further, heat treatment was performed in hydrogen at 1100 ° C. for 1 hour, and the surface roughness was evaluated by an atomic force microscope. The average square roughness in a 50 μm square region was about 0.2 nm, and it is a commercially available Si wafer. It was equivalent.

Thereafter, in order to adjust the shape of the peripheral portion, the Si layer and the SiO ₂ layer in the peripheral region having a width of 2.5 mm from the outer peripheral end were removed by patterning.

A 12-digit alphanumeric character was printed by a laser mark device near the notch in the peripheral area. At that time, there was no increase in particles on the SOI wafer.
The laser power at that time was 220 mW.

Alphanumeric size is
Height: 1.624 ± 0.025mm
Width: 0.812 ± 0.025mm
Line thickness: 0.200 + 0.050mm to 0.200-0.150mm
Character spacing: 1.420 ± 0.025mm
SEMI standard.

  The porous Si remaining on the first substrate side is then selectively etched while being stirred with the mixed solution of hydrofluoric acid, hydrogen peroxide solution, and water. After that, hydrogen annealing was performed to return to a state where it can be used again as the first substrate or the second substrate.

(Example 6)
A P-type first single crystal Si substrate having a specific resistance of 0.01 Ω · cm was anodized in an HF solution.

The anodizing conditions were as follows.
First stage current density: 7 (mA · cm ⁻² )
Anodizing solution: hydrofluoric acid: water: ethanol = 1: 1: 1
Time: 5 (minutes)
The thickness of the first porous Si layer on the surface side: 5.5 (μm)
Second stage current density: 30 (mA · cm ⁻² )
Anodizing solution: hydrofluoric acid: water: ethanol = 1: 1: 1
Time: 10 (seconds)
Thickness of the second porous Si layer below the first porous Si layer: 0.2 (μm)

This substrate was oxidized in an oxygen atmosphere at 400 ° C. for 1 hour. Due to this oxidation, the inner walls of the pores of the first and second porous Si layers were covered with a thermal oxide film. The surface of this porous Si layer is treated with hydrofluoric acid to leave only the oxide film on the surface of the porous Si layer, leaving an oxide film on the inner wall of the hole, and then single crystal Si is deposited on the porous Si by a CVD method. The epitaxial growth was 0.3 μm. The growth conditions are as follows.
Source gas: SiH ₂ Cl ₂ / H ₂
Gas flow rate: 0.5 / 180 l / min
Gas pressure: 1.1 × 10 ⁴ Pa (about 80 Torr)
Temperature: 950 ° C
Growth rate: 0.3 μm / min
Prior to epitaxial growth, heat treatment was performed in an epitaxial apparatus in an H ₂ atmosphere. Actually, the crystal defects of the epi layer could be reduced to 10 ⁴ cm ⁻² or less by this treatment.

Further, as the insulating layer, a 200 nm oxide film (SiO ₂ layer) was formed on the surface of the epitaxial Si layer by thermal oxidation.

Prepare another Si substrate, the part that will be outside the contact edge of the peripheral region of the substrate near the notch, that is, the surface of the peripheral portion of the Si substrate slightly inclined by beveling processing, and the laser mark device 12-digit alphanumeric characters were printed.
The laser power at that time was 220 mW.

Alphanumeric size is
Height: 1.624 ± 0.025mm
Width: 0.812 ± 0.025mm
Line thickness: 0.200 + 0.050mm to 0.200-0.150mm
Character spacing: 1.420 ± 0.025mm
After the SEMI standard, cleaning was performed.

The surface of the SiO ₂ layer on the first Si substrate and the surface of the marked second Si substrate were overlaid and brought into contact, and then heat treated at 1100 ° C. for 2 hours for bonding. . Later analysis revealed that the marked parts were not pasted together.

  The bonded substrate formed as described above was separated inside the second porous Si layer along the interface between the first porous layer and the second porous layer. As a separation method, a method of inserting a solid wedge and a method of inserting a water wedge by a water jet were used.

Thereafter, the first and second porous Si layers transferred on the second substrate are stirred with a mixture of hydrofluoric acid having an HF concentration of 49 wt%, hydrogen peroxide water having an H ₂ O ₂ concentration of 30 wt%, and water. However, selective etching was performed.

  Thus, a single crystal Si layer having a thickness of 0.2 μm was formed on the Si oxide film. There was no change in the single crystal Si layer even by selective etching of porous Si. When the film thickness of the formed single crystal Si layer was measured at 100 points on the entire surface, the uniformity of the film thickness was 201 nm ± 4 nm.

  As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that no new crystal defects were introduced into the Si layer and that good crystallinity was maintained.

  Further, heat treatment was performed in hydrogen at 1100 ° C. for 1 hour, and the surface roughness was evaluated by an atomic force microscope. The average square roughness in a 50 μm square region was about 0.2 nm, and it is a commercially available Si wafer. It was equivalent.

Thereafter, in order to adjust the shape of the peripheral portion, the SOI layer in the peripheral region having a width of 2.5 mm from the outer peripheral end was removed by patterning, and the SiO ₂ layer having a width of 2.3 mm was removed from the outer peripheral end by patterning.

  Since the mark portion was not pasted from the beginning, the mark portion was hardly deformed even after processes such as separation and etching.

  As described above in detail, according to each embodiment, generation of particles is suppressed because laser marking is performed on a region not having an SOI multilayer structure. In addition, there is no need to adjust and optimize the laser power by combining the SOI layer thicknesses. Any SOI structure can be marked under uniform conditions.

  The generation of particles is a major cause of decreasing the device yield. In particular, for the recent rule of 0.1 micron or less, no particles or small particles are allowed. Under such circumstances, optimizing the laser power or the like in accordance with the SOI film thickness configuration can somewhat suppress the generation of particles. However, this affects the yield in mass production. Accordingly, if marking can be performed under uniform conditions even if the SOI film thickness configuration is slightly different, the smallest possible increase in particles can be suppressed.

1 is a top view of a part of a semiconductor substrate according to an embodiment of the present invention. 1 is a cross-sectional view of a part of a semiconductor substrate according to an embodiment of the present invention. The top view of a part of another semiconductor substrate according to an embodiment of the present invention. Sectional drawing of a part of another semiconductor substrate by one embodiment of this invention. 1 is a top view of a part of a semiconductor substrate according to an embodiment of the present invention. 1 is a cross-sectional view of a part of a semiconductor substrate according to an embodiment of the present invention. 1 is a cross-sectional view of a part of a bonded substrate according to an embodiment of the present invention. Sectional drawing for demonstrating the manufacturing process of the semiconductor substrate by one embodiment of this invention. The figure which shows the flowchart of the manufacturing process of the semiconductor substrate by one embodiment of this invention. The figure which shows the flowchart of the manufacturing process of the semiconductor substrate by one embodiment of this invention. The figure which shows the flowchart of the manufacturing process of the semiconductor substrate by one embodiment of this invention. The figure which shows the flowchart of the manufacturing process of the semiconductor substrate by one embodiment of this invention. Sectional drawing for demonstrating the manufacturing process of the semiconductor substrate by one embodiment of this invention. Sectional drawing for demonstrating the manufacturing process of the semiconductor substrate by one embodiment of this invention. The figure which shows the flowchart of the manufacturing process of the semiconductor substrate by one embodiment of this invention. The figure which shows the flowchart of the manufacturing process of the semiconductor substrate by one embodiment of this invention. The figure which shows the flowchart of the manufacturing process of the semiconductor substrate by one embodiment of this invention. The figure which shows the cross-sectional shape of a laser mark. FIG. 6 is a top view of a part of a semiconductor substrate. 1 is a cross-sectional view of a part of a semiconductor substrate. The top view of a part of SOI substrate. FIG. 6 is a cross-sectional view of part of an SOI substrate. The figure which shows the cross-sectional shape of a laser mark.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Support substrate 2 Insulating layer 3 Semiconductor layer (SOI layer)
4 mark

Claims (5)

  A method for manufacturing a semiconductor substrate having a semiconductor layer provided above a support substrate, the method including a step of forming a mark on an inclined surface in a peripheral region of the support substrate. A method for manufacturing a semiconductor substrate, comprising:
Preparing a first substrate;
Preparing a second substrate;
Forming a mark on the periphery of the second substrate;
Bonding the first substrate and the second substrate;
Removing a unnecessary portion of the first substrate to transfer a transfer layer of the first substrate. A method for manufacturing a semiconductor substrate, comprising: A method for manufacturing a semiconductor substrate, comprising:
Preparing a first substrate;
Preparing a second substrate;
Forming a mark on the periphery of the second substrate;
A step of bonding the first substrate and the second substrate so as not to be bonded at a portion having the mark;
Removing a unnecessary portion of the first substrate to transfer a transfer layer of the first substrate. A method for manufacturing a semiconductor substrate, comprising: A method for manufacturing a semiconductor substrate, comprising:
Preparing a first substrate;
Preparing a second substrate;
Forming a mark on the periphery of the second substrate;
Bonding the first substrate and the second substrate such that a contact edge or a bonding edge is present inward from a portion having the mark;
Removing a unnecessary portion of the first substrate to transfer a transfer layer of the first substrate. A method for manufacturing a semiconductor substrate, comprising: A method for manufacturing a semiconductor substrate, comprising:
Preparing a first substrate;
Preparing a second substrate;
Forming a mark on the periphery of the second substrate;
Bonding the first substrate and the second substrate by locally retracting the bonding edge so that the bonding edge is present inward from the portion having the mark;
Removing a unnecessary portion of the first substrate to transfer a transfer layer of the first substrate. A method for manufacturing a semiconductor substrate, comprising:

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