TW300318B - - Google Patents

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TW300318B
TW300318B TW85103834A TW85103834A TW300318B TW 300318 B TW300318 B TW 300318B TW 85103834 A TW85103834 A TW 85103834A TW 85103834 A TW85103834 A TW 85103834A TW 300318 B TW300318 B TW 300318B
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substrate
active
grinding
active substrate
substrates
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TW85103834A
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Chinese (zh)
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Komatsu Denshi Kinzoku Kk
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經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明(1 ) 本發明係有關使得活性基板用之半導體晶圓與支持基 板用之半導體晶圓相貼合所得出SOI基板之製造方法。 最近,隨著積體電路開發技術之提高,自裝置工程起 之SOI基板製造也越來越嚴格要求品質之提高。特別是, 爲了謀求積體電路作動速度之高速化,必須儘可能地將活 性層薄膜化。 習知之將活性基板用之半導體晶圓與支持基板用之 半導體晶圓相貼合以得出SOI基板係依下述之工程製造 出。 (1) 使得支持基板用之半導體晶圓表面形成氧化膜,於 其上方貼合活性基板用之半導體晶圓,接著使得活性基板 之表面亦形成氧化膜而得貼合晶圓。 (2) 接著,藉由研削或蝕刻以除去此貼合晶圓周缘部之 未接著部分。 (3) 平面研削活性基板之表面,以使其厚度減少。 (4) 使得支持基板之裡面貼付於貼付阻片,並研磨活性 基板之表面,以使得活性基板之厚度再減少。 然而,依此研磨而薄化之活性基板之厚度爲2〜3μιη之 程度,而於製造高速積體電路時所使用之SOI基板係,必 須要求將活性基板之厚度薄膜化至Ο.ΐμπι之程度。此薄膜 化係使用PACE加工。即,依上述方法所研磨得之活性基 板表面再經此PACE加工而形成均一地薄膜化。 然而,如此般之將經貼付研磨後之活性基板進行PACE 加工之方法係,爲了進行研磨則必須將支持基板之裡面貼 4 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) ---------ΐ衣------ΪΤ------.^ (請先.閱讀背面•之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 ------__B7 五、發明説明(2 ) 付於貼付阻片,只要貼付阻片之貼付面與支持基板之趣面 之間有異物及凹陷存在,將會使得研磨後之活性基板表面 產生微小的凹凸。 例如,當貼付阻片4之貼付面有異物5時[圖2(a)],只 要此貼付面貼付於支持基板13上,將會使支持基板W 種面產生源於異物5之凹陷5a,此凹陷5a可於支持基板 la之上面介入氧化膜3a而貼合活性基板。,亦可於不介 入氧化膜3a而直接於活性基板2a之上面進行研磨,於活 性基板2a上會產生極薄部分5b[圖2(b)]。於研磨終了後, 自貼付阻片4剥離,當除去蠛4a後,支持基板la將回復 原先之狀態,如此可使得活性基板2a之極薄部分讣以凹 陷之狀態殘存著[圖2(c)]。 又’當支持基板lb之裡面有凹陷6時[圖3(a)],只要 將此支持基板lb貼付於貼付阻片4並進行研磨,對應於氧 化膜3b及活性基板2b之凹陷6之部分會由於研磨壓力而 形成凹陷,如此般進行研磨,該部分會形成極厚部分6a[圖 3(b)]。研磨終了後,自貼付阻片4剥離並除去蠟乜後,支 持基板lb將回復原狀,如此極厚部分以係以突出於活性 基板2b表面之狀態殘存著[圖3(c)]。 然而,若於支持基板之表面局部的存在上述般之微小 的凹凸,則就算進行PACE加工亦無法達成平坦化,因此 產生無法得到具均一厚度之活性基板之問題。 本發明係著眼於上述之問題,其目的爲提供—種具有 經均一薄膜化的活性基板之SOI基板之製造方法。 5 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 裝------1T-------^ .(請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明(3 ) 因此本發明之SOI基板之製造方法係,使用兩面研磨 裝置同時研磨支持基板用之半導體晶圓之兩面,接著於經 兩面研磨之支持基板之上面貼合活性基板用之半導體晶 圓而得貼合晶圓,除去貼合晶圓之周缘部之未接著部分, 平面研削經除去未接著部分之貼合晶圓之活性基板表面 以減少其厚度,使用旋轉蝕刻以蝕刻經平面研削之活性基 板表面,藉由PACE加工而薄膜化經旋轉蝕刻之活性基 板0 又,SOI基板之製造之方法可爲,使用兩面研磨裝置 同時研磨支持基板用之半導體晶圓之兩面,接著於經兩面 研磨之支持基板之上面貼合活性基板用之半導體晶圓而 得貼合晶圓,除去貼合晶圓之周緣部之未接著部分,平面 研削經除去未接著部分之貼合晶圓之活性基板表面以減 少其厚度,將一牧一枚之經平面研削之貼合晶圓藉由頂環 (top ring)支持著、即將活性基板進行枚葉研磨,藉由PACE 加工而薄膜化經枚葉研磨之活性基板。 [實施例] 以下,基於圖面以説明本發明之實施例。 圖1係有關本發明之SOI基板製造方法之各工程的側 面剖面圖,圖2及圖3係依據習知技術之製造方法所製得 SOI基板之側面剖面圖。 本實施例之SOI基板係由以下之方法製造出。 (1)使用兩面研磨裝置同時研磨支持基板1用之半導體 晶圓的兩面,而得表面及裡面皆平坦之半導體晶圓[圖 6 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 批衣 訂 線 (請先.閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 ---__£L_ 五、發明説明(4 ) 1(a)]。此經兩面研磨之支持基板丨之裡面係,不存在 最終工程之活性基板之薄膜化產生不良影響之凹陷等= ⑺使得經兩面研磨之支持基板】之表面產生氧化膜 3,於其上面貼合活性基板2用之半導體晶圓,接著於活 性基板2上亦形成我化膜3而得貼合晶圓[圖1 (b)]。 (3) 除去貼合晶圓周缘部之未接著部分,並除去活性基 板2與支持基板i間之氧化膜3以外之氧化膜接著平面 研削活性基板之上面以減少其厚度[圖1(c)]。 (4) 藉由旋轉蝕刻而將經平面研削之活性基板2之表面 進行蝕刻,以使得活性基板2厚度更減少[圖2(d)]。此旋 轉蝕刻可除去約10.0〜20.Ομπι之程度,其所形成之厚度不 均爲所除去厚度之± 5.0%以内,即可藉由緊接著之pACE 加工而除去之厚度。又相對於習知技術之研磨速率爲 〇.8μηι/分而言,使用旋轉蝕刻之蝕刻速率爲相當快速之 30μιη/分’故可顯著地提高作業效率。 (5) 藉由PACE加工以薄膜化經旋轉蝕刻之活性基板之 表面[圖1(e)]。由於經旋轉蝕刻所產生之厚度不均不同於 習知技術之貼付研磨時所產生小凹凸、而呈平滑之狀態, 故使用PACE加工時之分解能即可完善地處理,因此可均 一地薄膜化活性基板1。又,此經PACE加工而薄膜化之 活性基板1之厚度不均爲士 1〇 0nm之程度。 又,上述實施例中’經平面研削之活性基板2係藉由 旋轉蝕刻而進行薄化加工,但並不以此爲限,亦可取代旋 +紙》尺度通用中國國家標準(CNS ) A4規格(21〇χπ?公釐 I ----裝-- (請先閲讀背面之注意事項再填寫本頁) 訂 -線 經濟部中央標準局員工消f A7 -----------B7 __ 五、發明酬(5 ) - 轉蝕刻,而將經平面研削之貼合晶圓一牧一枚藉由頂環支 持著,即使用牧葉研磨之方法亦可。於此方法中由於亦使 用經兩面研磨之半導體晶圓作爲支持基板使用之,故於枚 葉研磨時不致產生由於支持基板裡面之不適而帶給活性 基板之不良影響。 由於本發明具以上般之構成,故可防止於pACE加工 之前工程所發生之厚度不均,因此可得具有經均一薄膜化 的活性基板之SOI基材之優點效果。 又,由於使用經兩面研磨之半導體晶圓作爲支持基板 使用之,故支持基板之裡面不致產生凹陷等不適之狀況, 故具有於活性基板薄膜化時不致產生不佳之影響之優異 效果。 再者,與習知技術之貼付研磨相比較,由於旋轉餘刻 之速率較快,故具有生產效率佳之優異效果。 [圖面之簡單説明] 圖1係有關本發明SOI基板製造方法的各工程之側面剖 面圖。 圖2係依照習知技術之製造方法以製造出SOI基板之側 面剖面圖。 圖3係依照習知技術之製造方法以製造出s〇l基板之側 面剖面圖。 [符號説明] 1〜支持基板,la〜支持基板,lb〜支持基板,2〜活性基 2a〜活性基板,2b〜活性基板,3〜氧化膜,3a〜氧化 8 國國家標準(CNS ) A4規格(210X297公董) II 辦衣 |,訂 線 .(請先閱讀背面之注意事項再填转本頁) A7 B7 五、發明説明(6 ) 膜,3b〜氧化膜,4〜貼付阻片,4a〜蠟,5〜異物,5a〜凹 陷,5b〜極薄部分,6〜凹陷,6a〜極厚部分。 (請先閲讀背面之注意事項再填寫本頁) -裝.Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 V. Description of the invention (1) The present invention relates to a method for manufacturing an SOI substrate obtained by laminating a semiconductor wafer for an active substrate and a semiconductor wafer for a supporting substrate. Recently, with the improvement of integrated circuit development technology, the manufacture of SOI substrates since device engineering has become more and more strict with the improvement of quality. In particular, in order to increase the operating speed of the integrated circuit, it is necessary to make the active layer as thin as possible. It is known to bond semiconductor wafers for active substrates and semiconductor wafers for support substrates to obtain SOI substrates that are manufactured according to the following process. (1) An oxide film is formed on the surface of the semiconductor wafer for the support substrate, and the semiconductor wafer for the active substrate is bonded thereon, and then an oxide film is also formed on the surface of the active substrate to obtain the bonded wafer. (2) Next, by grinding or etching, the unattached portion of the peripheral portion of the bonded wafer is removed. (3) Plane grinding the surface of the active substrate to reduce its thickness. (4) The inside of the support substrate is attached to the resist film, and the surface of the active substrate is polished to reduce the thickness of the active substrate. However, the thickness of the active substrate thus polished and thinned is about 2 to 3 μm, and the SOI substrate used in the manufacture of high-speed integrated circuits must be thinned to a thickness of 0.1 μm . This thinning system uses PACE processing. That is, the surface of the active substrate polished according to the above-mentioned method is subjected to PACE processing to form a uniform thin film. However, the method of PACE processing the active substrate after the polishing is applied in this way, in order to perform the polishing, the inside of the supporting substrate must be pasted. This paper size is applicable to the Chinese National Standard (CNS) Α4 specification (210Χ297 mm)- -------- Ι 衣 ------ ΪΤ ------. ^ (please read the notes on the back first and then fill out this page) Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 ------__ B7 5. Description of the invention (2) For the resist film, as long as there are foreign objects and depressions between the surface of the resist film and the interesting surface of the support substrate, it will make the active substrate after polishing There are tiny irregularities on the surface. For example, when there is a foreign object 5 on the application surface of the resist film 4 [FIG. 2 (a)], as long as the application surface is attached to the support substrate 13, a depression 5a derived from the foreign object 5 will be generated on the support substrate W surface, This recess 5a can interpose the active substrate by interposing the oxide film 3a on the support substrate la. It is also possible to grind directly on the active substrate 2a without interposing the oxide film 3a, and an extremely thin portion 5b will be generated on the active substrate 2a [FIG. 2 (b)]. After the polishing is completed, the self-adhesive resist sheet 4 is peeled off, and after the worm 4a is removed, the support substrate la will return to the original state, so that the extremely thin portion of the active substrate 2a may remain in a recessed state [Figure 2 (c) ]. Also, when there is a recess 6 in the support substrate lb [FIG. 3 (a)], as long as the support substrate lb is attached to the resist sheet 4 and polished, the portion corresponding to the recess 6 of the oxide film 3b and the active substrate 2b A depression is formed due to the grinding pressure, and grinding is performed in this way, and an extremely thick portion 6a is formed in this portion [FIG. 3 (b)]. After the polishing is completed, after the self-adhesive resist sheet 4 is peeled off and the wax is removed, the supporting substrate 1b will return to its original state, and such an extremely thick portion remains in a state protruding from the surface of the active substrate 2b [Fig. 3 (c)]. However, if the above-mentioned minute irregularities exist locally on the surface of the support substrate, even if the PACE processing is performed, flattening cannot be achieved, so that there is a problem that an active substrate having a uniform thickness cannot be obtained. The present invention focuses on the above-mentioned problems, and its object is to provide a method for manufacturing an SOI substrate having an active substrate that is uniformly thinned. 5 The size of this paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) ------ 1T ------- ^. (Please read the precautions on the back before filling this page) Ministry of Economic Affairs A7 B7 is printed by the Consumer Cooperative of the Central Bureau of Standards. 5. Description of the invention (3) Therefore, the manufacturing method of the SOI substrate of the present invention is to use a two-side grinding device to grind both sides of the semiconductor wafer for supporting the substrate at the same time, and then grind the two sides. The semiconductor wafer for the active substrate is bonded to the support substrate to obtain the bonded wafer, and the unattached portion of the peripheral portion of the bonded wafer is removed, and the surface of the active substrate of the bonded wafer with the unbonded portion removed by planar grinding is Reducing its thickness, using rotary etching to etch the surface of the active substrate after grinding, thinning the active substrate by rotary etching using PACE processing. Also, the method of manufacturing the SOI substrate may be to use both sides of the grinding device to simultaneously grind the supporting substrate The two sides of the semiconductor wafer used, and then the semiconductor wafer for the active substrate is bonded on the support substrate ground on both sides to obtain the bonded wafer, and the bonded wafer is removed For the unattached part of the peripheral part, planar grinding removes the surface of the active substrate where the unattached portion of the bonded wafer is reduced to reduce its thickness, and a piece of one-by-one planar ground bonded wafer is passed through the top ring It supports, that is, the active substrate is polished by the blade, and the active substrate polished by the blade is thinned by PACE processing. [Examples] Hereinafter, examples of the present invention will be described based on the drawings. Fig. 1 is a side cross-sectional view of various projects related to the SOI substrate manufacturing method of the present invention, and Figs. 2 and 3 are side cross-sectional views of an SOI substrate manufactured according to a conventional manufacturing method. The SOI substrate of this embodiment is manufactured by the following method. (1) Simultaneously grind both sides of the semiconductor wafer used for the support substrate 1 using a two-side grinding device to obtain a semiconductor wafer with a flat surface and inside [Figure 6 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm ) Approved clothing line (please read the precautions on the back and fill in this page) A7 ---__ £ L_ printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs V. Description of Invention (4) 1 (a)]. The inside of the support substrate polished on both sides has no recesses that adversely affect the thinning of the active substrate of the final project, etc. = ⑺ The oxide film 3 is produced on the surface of the support substrate polished on both sides, and is adhered on it The semiconductor wafer for the active substrate 2 is then formed with the chemical film 3 on the active substrate 2 to obtain a bonded wafer [FIG. 1 (b)]. (3) Remove the unattached portion of the peripheral edge of the bonded wafer, and remove the oxide film other than the oxide film 3 between the active substrate 2 and the support substrate i and then planarly grind the upper surface of the active substrate to reduce its thickness [Figure 1 (c) ]. (4) The surface of the active substrate 2 ground by planar etching is etched by spin etching, so that the thickness of the active substrate 2 is further reduced [Fig. 2 (d)]. This rotary etching can remove the degree of about 10.0 ~ 20.0μπι, and the thickness is not all within ± 5.0% of the removed thickness, which can be removed by the subsequent pACE processing. Compared with the conventional technology, where the polishing rate is 0.8 μm / min, the etching rate using spin etching is relatively fast, 30 μm / min, so the work efficiency can be significantly improved. (5) The surface of the spin-etched active substrate is thinned by PACE processing [Figure 1 (e)]. Since the thickness unevenness produced by the rotary etching is different from the small unevenness generated by the conventional technique of attaching and polishing, it is in a smooth state, so the decomposition during the use of PACE processing can be perfectly processed, so the activity can be uniformly thinned Substrate 1. Moreover, the thickness of the active substrate 1 thinned by PACE processing is not all about ± 100 nm. In addition, in the above embodiment, the planar substrate of the active substrate 2 is thinned by rotary etching, but it is not limited to this, and it can also replace the spin + paper "standard General Chinese National Standard (CNS) A4 specification (21〇χπ? Mm I ---- installed-(please read the precautions on the back and then fill out this page) Order-line Ministry of Economic Affairs Central Standards Bureau staff elimination A7 ---------- -B7 __ 5. Remuneration for inventions (5)-Transfer etching, and the bonded wafers that have been planarly ground are supported by a top ring, which is supported by the top ring, even if the method of grinding leaves is also used. In this method, because The semiconductor wafer that has been polished on both sides is also used as a support substrate, so there is no adverse effect on the active substrate due to the discomfort in the support substrate during the polishing of the blade. Since the present invention has the above structure, it can be prevented The thickness unevenness that occurs in the process before the pACE process, so the advantages of the SOI substrate with a uniform thin-film active substrate can be obtained. In addition, because the semiconductor wafer that has been polished on both sides is used as a support substrate, it supports No inside of the substrate Discomfort and other uncomfortable conditions, so it has an excellent effect that does not produce a bad effect when the active substrate is thinned. In addition, compared with the conventional technology of paste grinding, the speed of the remaining rotation is faster, so it has good production efficiency. Excellent effect. [Brief description of the drawings] Figure 1 is a side cross-sectional view of various projects related to the SOI substrate manufacturing method of the present invention. Figure 2 is a side cross-sectional view of the SOI substrate manufactured according to the manufacturing method of the conventional technology. Figure 3 It is a side cross-sectional view of a sol substrate manufactured according to the manufacturing method of the conventional technology. [Symbol Explanation] 1 ~ support substrate, la ~ support substrate, lb ~ support substrate, 2 ~ active base 2a ~ active substrate, 2b ~ Active substrate, 3 ~ Oxide film, 3a ~ Oxide 8 national standard (CNS) A4 specification (210X297 company director) II Office clothes |, booking. (Please read the precautions on the back before filling this page) A7 B7 5 2. Description of the invention (6) Film, 3b ~ Oxide film, 4 ~ Attached resist sheet, 4a ~ Wax, 5 ~ Foreign matter, 5a ~ Depression, 5b ~ Extremely thin part, 6 ~ Depression, 6a ~ Extremely thick part. (Please first Read the notes on the back Write Page) - installed.

、1T 線 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X2.97公釐), 1T line Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs

Claims (1)

A B c D 經濟部中央標準局員工消費合作社印製 六、申請專利範圍 1. 一種SOI基板之製造方法,其特徵爲由以下之工程所 構成: (1) 兩面研磨工程,使用兩面研磨裝置同時研磨支持基 板用之半導體晶圓之兩面; (2) 貼合工程,於經兩面研磨之支持基板上面貼合活性 基板用之半導體晶圓; (3) 未接著部除去工程,除去貼合晶圓周緣部之未接著 部分; (4) 平面研削工程,平面研削經除去未接著部分之貼合 晶圓之活性基板之表面,以使其厚度減低; (5) 旋轉蝕刻工程,藉由旋轉蝕刻以蝕刻經平面研削之 活性基板表面; (6) PACE加工工程,藉由PACE加工以薄膜化經旋轉蝕 刻之活性基板。 2. —種SOI基板之製造方法,其特徵爲由以下之工程所 構成: (1 ;)兩面研磨工程,使用兩面研磨裝置同時研磨支持基 板用之半導體晶圓之兩面; (2) 貼合工程,於經兩面研磨之支持基板上面貼合活性 基板用之半導體晶圓; (3) 未接著部除去工程,除去貼合晶圓周緣部之未接著 部分; (4) 平面研削工程,平面研削經除去未接著部分之貼合 晶圓之活性基板之表面,以使其厚度減低; 10 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) ..............-........裝................-可................線 (請先閱讀背面之注意事項再填寫本頁) A8 B8 C8 D8 六、申請專利範圍 (5) 枚葉研磨工程,藉由頂環支持一牧一牧經平面研削 之貼合晶圓,以研磨活性基板; (6) PACE加工工程,藉由PACE加工以薄膜化經枚葉研 磨之活性基板。 .......................裝................-玎................線 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐)AB c D Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 6. Scope of Patent Application 1. A method for manufacturing SOI substrates, characterized by the following projects: (1) Two-side grinding process, using two-side grinding equipment for simultaneous grinding Both sides of the semiconductor wafer for the support substrate; (2) Lamination process, lamination of semiconductor wafers for active substrates on the support substrates polished on both sides; (3) Removal of unattached parts, removal of the periphery of bonded wafers The unjoined part of the part; (4) Plane grinding process, the plane grinding removes the surface of the active substrate attached to the wafer of the unjoined part to reduce its thickness; (5) Rotary etching process, etching by rotary etching The surface of the active substrate after planar grinding; (6) PACE processing engineering, by PACE processing to thin the active substrate by rotary etching. 2. A method of manufacturing SOI substrates, characterized by the following projects: (1;) two-side polishing process, using a two-side polishing device to simultaneously grind both sides of the semiconductor wafer for the support substrate; (2) bonding process , Lamination of semiconductor wafers for active substrates on the support substrates polished on both sides; (3) Removal of unbonded parts, removal of unbonded parts on the peripheral edge of bonded wafers; (4) Planar grinding process, planar grinding Remove the unattached part of the surface of the active substrate attached to the wafer to reduce its thickness; 10 paper standards are applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) ........... ...-........ installed ..........- may ................ line (please (Read the precautions on the back before filling in this page) A8 B8 C8 D8 6. Scope of patent application (5) One-blade polishing project, which supports the lamination of one animal husbandry and one animal by planar grinding by the top ring to grind the active substrate ; (6) PACE processing engineering, through PACE processing to thin the active substrate polished by the blades. ...................... Pretend ..................- 玎 ........ ........ Line (please read the precautions on the back before filling out this page) The paper standard printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm)
TW85103834A 1995-03-29 1996-04-02 TW300318B (en)

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JP10990895A JP3553196B2 (en) 1995-03-29 1995-03-29 Method for manufacturing SOI substrate

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TW300318B true TW300318B (en) 1997-03-11

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Cited By (1)

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Publication number Priority date Publication date Assignee Title
US8035962B2 (en) 2010-03-03 2011-10-11 Antec, Inc. Computer hot-plug structure

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0964321A (en) * 1995-08-24 1997-03-07 Komatsu Electron Metals Co Ltd Manufacture of soi substrate
US6090688A (en) * 1996-11-15 2000-07-18 Komatsu Electronic Metals Co., Ltd. Method for fabricating an SOI substrate
JP3672436B2 (en) 1998-05-19 2005-07-20 シャープ株式会社 Method for manufacturing solar battery cell
JP3944087B2 (en) 2003-01-21 2007-07-11 株式会社東芝 Method for manufacturing element forming substrate
KR20110099108A (en) 2008-11-19 2011-09-06 엠이엠씨 일렉트로닉 머티리얼즈, 인크. Method and system for stripping the edge of a semiconductor wafer
JP7187115B2 (en) * 2018-12-04 2022-12-12 株式会社ディスコ Wafer processing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8035962B2 (en) 2010-03-03 2011-10-11 Antec, Inc. Computer hot-plug structure

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JPH08274286A (en) 1996-10-18

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