JP2000182995A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JP2000182995A
JP2000182995A JP10354042A JP35404298A JP2000182995A JP 2000182995 A JP2000182995 A JP 2000182995A JP 10354042 A JP10354042 A JP 10354042A JP 35404298 A JP35404298 A JP 35404298A JP 2000182995 A JP2000182995 A JP 2000182995A
Authority
JP
Japan
Prior art keywords
adhesive layer
tape
wafer
adhesive
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP10354042A
Other languages
Japanese (ja)
Inventor
Toshimitsu Maki
俊光 巻
Nobuo Tashiro
伸夫 田代
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsumi Electric Co Ltd
Original Assignee
Mitsumi Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsumi Electric Co Ltd filed Critical Mitsumi Electric Co Ltd
Priority to JP10354042A priority Critical patent/JP2000182995A/en
Publication of JP2000182995A publication Critical patent/JP2000182995A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Dicing (AREA)
  • Die Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of reducing the size of a wafer by eliminating effusion of adhesive and the like. SOLUTION: A wafer 10 to be divided into a plurality of chips 14 is prepared and a tape 30 with an adhesive layer 33 formed on its tape base material 31 is prepared. The adhesive layer of the tape is bonded to the reverse side of the wafer. The wafer is cut from its surface through the adhesive layer of the tape to be divided into a plurality of chips. The divided chips 14 with the adhesive layer are detached and used for die bonding with the adhesive layer.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、多層の粘着層を有
したテープを使用することにより、ダイシングからダイ
ボンディングまでの工程を容易に実施できるようにした
半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device which can easily carry out steps from dicing to die bonding by using a tape having a multi-layered adhesive layer.

【０００２】[0002]

【従来の技術】一般的なモノリシックＩＣは、１枚の半
導体ウエハからダイシング装置で複数のチップを切り出
すダイシング工程と、切り出された個別のチップをリー
ドフレームのアイランド部に固定するダイボンディング
工程と、チップ上部の電極とインナーリードとの間を金
等の細線により配線するワイヤボンディング工程とを経
て製造される。2. Description of the Related Art A general monolithic IC includes a dicing step of cutting a plurality of chips from one semiconductor wafer by a dicing apparatus, a die bonding step of fixing the cut individual chips to an island portion of a lead frame, and It is manufactured through a wire bonding step of wiring between the electrode on the chip and the inner lead with a thin wire such as gold.

【０００３】ダイシング工程では、図２（ａ）の平面図
に示すように、１枚のウエハ１０に格子状の切断線１１
を仮想し、その一部に図２（ｂ）の拡大平面図および
（ｃ）の断面図に示すように、ダイシングブレード１２
による切断部１３を形成して個別のチップ１４に分割す
る。この場合、分割後のチップ１４を分散させないよう
に保持しておくために粘着テープ１５を予めウエハ１０
の裏面に接着しておく。In the dicing step, as shown in the plan view of FIG.
As shown in the enlarged plan view of FIG. 2B and the cross-sectional view of FIG.
And cut into individual chips 14. In this case, in order to hold the divided chips 14 so as not to be dispersed, the adhesive tape 15 is
Adhere to the back of

【０００４】[0004]

【発明が解決しようとする課題】分割されたチップ１４
はダイボンディング工程へ送られる。この工程で使用さ
れる接着材料には、銀ペースト等の接着材、共晶、粘着
テープがある。これらは装置内部において別途供給され
るが、位置精度及び接着量のばらつきによるはみ出し等
の影響を避けるために、ステージサイズを必要以上に大
きくする必要がある。The divided chip 14
Is sent to the die bonding step. The adhesive material used in this step includes an adhesive such as a silver paste, a eutectic, and an adhesive tape. These are separately supplied inside the apparatus, but it is necessary to make the stage size unnecessarily large in order to avoid the influence of protrusion or the like due to variations in positional accuracy and the amount of adhesion.

【０００５】本発明は、接着剤等のはみ出しが少なく、
搭載スペースを削減可能な半導体装置の製造方法を提供
することを目的としている。According to the present invention, there is little protrusion of an adhesive or the like,
It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of reducing a mounting space.

【０００６】[0006]

【課題を解決するための手段】本発明の上記目的は、複
数のチップに分割される１枚の半導体ウエハを準備する
工程と、テープ基材上に粘着層を形成したテープを準備
する工程と、前記テープの前記粘着層を前記ウエハの裏
面に接着する工程と、前記ウエハの表面から前記テープ
の前記粘着層まで切断して前記ウエハを前記複数のチッ
プに分割するダイシング工程と、前記分割されたチップ
を前記粘着層を付着したまま剥離する工程と、前記剥離
されたチップを前記粘着層を使用してダイボンディング
する工程とを備える半導体装置の製造方法で達成でき
る。The object of the present invention is to provide a step of preparing one semiconductor wafer divided into a plurality of chips, and a step of preparing a tape having an adhesive layer formed on a tape substrate. Bonding the adhesive layer of the tape to the back surface of the wafer; dicing the wafer into the plurality of chips by cutting from the surface of the wafer to the adhesive layer of the tape; The method can be achieved by a method of manufacturing a semiconductor device, comprising: a step of peeling off a chip with the adhesive layer attached thereto; and a step of die-bonding the peeled chip using the adhesive layer.

【０００７】本発明の実施形態では、前記粘着層は、前
記ウエハの裏面に接着される上層と、前記テープ基材に
接着されたまま残る下層とからなり、前記ダイシング工
程では前記上層および前記下層の全てとテープ基材の一
部が切断される。一例として、前記下層は、紫外線また
は熱硬化型粘着材料からなる。前記上層は、前記下層と
は異なる粘着材料から構成され得る。前記上層と前記下
層は、それぞれ複数層の粘着材料の層から構成すること
もできる。本発明の他の目的および実施の形態は、以下
の実施形態で明らかにされる。In an embodiment of the present invention, the adhesive layer includes an upper layer adhered to the back surface of the wafer and a lower layer remaining adhered to the tape substrate. In the dicing step, the upper layer and the lower layer And a part of the tape substrate are cut. For example, the lower layer is made of an ultraviolet or thermosetting adhesive material. The upper layer may be composed of an adhesive material different from the lower layer. The upper layer and the lower layer may each be composed of a plurality of layers of an adhesive material. Other objects and embodiments of the present invention will be clarified in the following embodiments.

【０００８】[0008]

【発明の実施の形態】以下、図面に示した実施形態を参
照して、本発明を詳細に説明する。図１（ａ）〜（ｃ）
は、本発明に係る半導体装置の製造方法の一実施形態を
示す工程図である。本発明では、先ず図１（ａ）に示す
ように、複数のチップに分割される１枚の半導体ウエハ
１０を準備する。一方、テープ基材３１上に粘着層３
２，３３を形成したテープ３０を準備する。本例のテー
プ３０は、２層の粘着層３２，３３を有し、上層の粘着
層３３がウエハ１０の裏面に接着される。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to embodiments shown in the drawings. 1 (a) to 1 (c)
FIG. 3 is a process chart showing one embodiment of a method for manufacturing a semiconductor device according to the present invention. In the present invention, first, as shown in FIG. 1A, one semiconductor wafer 10 divided into a plurality of chips is prepared. On the other hand, the adhesive layer 3
The tape 30 on which the tapes 2 and 33 are formed is prepared. The tape 30 of this example has two adhesive layers 32 and 33, and the upper adhesive layer 33 is adhered to the back surface of the wafer 10.

【０００９】次に、図１（ｂ）に示すように、ダイシン
グブレード１２でウエハ１０の表面からテープ３０の粘
着層３２，３３まで切断してウエハ１０を複数のチップ
１４に分割する（ダイシング工程）。１３はこの時形成
される切断部である。この時、テープ基材３１の一部が
切断されても良い。Next, as shown in FIG. 1B, the dicing blade 12 cuts the surface of the wafer 10 down to the adhesive layers 32 and 33 of the tape 30 to divide the wafer 10 into a plurality of chips 14 (dicing step). ). Reference numeral 13 denotes a cut portion formed at this time. At this time, a part of the tape base material 31 may be cut.

【００１０】更に、図１（ｃ）に示すように、分割され
たチップ１４を粘着層３３を付着したまま剥離する。こ
の時、下層の粘着層３２はテープ基材３１に付着して残
る。下層の粘着層３２は、例えば１２０℃以下で反応す
る紫外線（ＵＶ）硬化型または熱硬化型粘着材料であ
り、また上層の粘着層３３は、例えば１２０〜２００℃
で反応するＡｇペースト＋ＵＶ未反応粘着材料である。
従って、下層の粘着層３２を硬化させることにより、上
層の粘着層３３との剥離は容易になる。チップ１４のピ
ックアップには、一般に真空ピンセットが使用される。Further, as shown in FIG. 1C, the divided chips 14 are peeled off with the adhesive layer 33 attached. At this time, the lower adhesive layer 32 adheres to the tape base material 31 and remains. The lower adhesive layer 32 is, for example, an ultraviolet (UV) curable or thermosetting adhesive material that reacts at 120 ° C. or lower, and the upper adhesive layer 33 is, for example, 120 to 200 ° C.
Ag paste + UV unreacted adhesive material that reacts with
Accordingly, by curing the lower adhesive layer 32, the separation from the upper adhesive layer 33 is facilitated. In general, vacuum tweezers are used for picking up the chip 14.

【００１１】ピックアップされたチップ１４の裏面に
は、チップサイズと等しい面積の粘着層３３が付着して
いるので、これを使用してダイボンディングする。この
ようにすれば、接着剤等のはみ出しがなく、搭載基板ス
ペースを小さくできる。An adhesive layer 33 having an area equal to the chip size is attached to the back surface of the picked-up chip 14, and is used for die bonding. With this configuration, the adhesive or the like does not protrude, and the mounting substrate space can be reduced.

【００１２】ダイボンディングは、粘着層３３の接着力
で行われるので、接着剤使用時のような硬化工程が不要
になる。このため、熱ストレスの影響が少なく、また酸
化膜量が減少するため、品質が向上する。更に、生産性
が向上すると共に、接着剤の硬化用設備が不要になる利
点がある。Since the die bonding is performed by the adhesive force of the pressure-sensitive adhesive layer 33, a curing step such as when using an adhesive is not required. Therefore, the influence of thermal stress is small and the amount of oxide film is reduced, so that the quality is improved. Further, there is an advantage that productivity is improved and equipment for curing the adhesive is not required.

【００１３】加えて、接着材料の供給、硬化ステージ、
銀ペースト使用時に必要な振動付加等のオプションが一
切不要となるため、チップ搭載設備が安価になる利点も
ある。In addition, the supply of the adhesive material, the curing stage,
Since there is no need for any option such as adding vibration required when using silver paste, there is also an advantage that the chip mounting equipment is inexpensive.

【００１４】本発明は上記の実施形態に限定されず、種
々に変形することができる。例えば、上層の粘着層３３
および下層の粘着層３２は、何れも多層構造とすること
ができる。また、上層の粘着層３３に導電性を持たせ
て、チップ１４の裏面からグランドを取るようにした
り、熱放散性を向上させることも可能である。The present invention is not limited to the above embodiment, but can be variously modified. For example, the upper adhesive layer 33
Each of the lower adhesive layer 32 and the lower adhesive layer 32 may have a multilayer structure. Further, it is also possible to impart conductivity to the upper adhesive layer 33 so that a ground is formed from the back surface of the chip 14 or to improve heat dissipation.

【００１５】[0015]

【発明の効果】以上述べたように本発明によれば、接着
剤等のはみ出しが少なく、搭載基板スペースを削減可能
な半導体装置の製造方法を実現することができる。As described above, according to the present invention, it is possible to realize a method of manufacturing a semiconductor device in which an adhesive or the like does not protrude and a mounting board space can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 本発明の一実施形態に係る半導体装置の製造
方法を示す工程図である。FIG. 1 is a process chart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

【図２】 従来のダイシング工程を示す説明図である。FIG. 2 is an explanatory view showing a conventional dicing process.

【符号の説明】[Explanation of symbols]

１０ 半導体ウエハ １２ ダイシングブレード １４ チップ ３０ テープ ３１ テープ基材 ３２ 下層の粘着層 ３３ 上層の粘着層 DESCRIPTION OF SYMBOLS 10 Semiconductor wafer 12 Dicing blade 14 Chip 30 Tape 31 Tape base material 32 Lower adhesive layer 33 Upper adhesive layer

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 複数のチップに分割される１枚の半導体
ウエハを準備する工程と、 テープ基材上に粘着層を形成したテープを準備する工程
と、 前記テープの前記粘着層を前記ウエハの裏面に接着する
工程と、 前記ウエハの表面から前記テープの前記粘着層まで切断
して前記ウエハを前記複数のチップに分割するダイシン
グ工程と、 前記分割されたチップを前記粘着層を付着したまま剥離
する工程と、 前記剥離されたチップを前記粘着層を使用してダイボン
ディングする工程とを備えることを特徴とする半導体装
置の製造方法。A step of preparing a single semiconductor wafer divided into a plurality of chips; a step of preparing a tape having an adhesive layer formed on a tape base; and a step of applying the adhesive layer of the tape to the wafer. Bonding to the back surface, dicing to cut the wafer into the plurality of chips by cutting from the surface of the wafer to the adhesive layer of the tape, and peeling the divided chips with the adhesive layer attached And a step of die-bonding the separated chip using the adhesive layer. 【請求項２】 前記粘着層は、前記ウエハの裏面に接着
される上層と、前記テープ基材に接着されたまま残る下
層とからなり、前記ダイシング工程では前記上層および
前記下層の全てと前記テープ基材の一部が切断されるこ
とを特徴とする請求項１の半導体装置の製造方法。2. The pressure-sensitive adhesive layer comprises an upper layer adhered to the back surface of the wafer and a lower layer remaining adhered to the tape base. In the dicing step, all of the upper layer and the lower layer and the tape 2. The method according to claim 1, wherein a part of the base material is cut. 【請求項３】 前記下層は、紫外線または熱硬化型粘着
材料からなることを特徴とする請求項２の半導体装置の
製造方法。3. The method according to claim 2, wherein the lower layer is made of an ultraviolet or thermosetting adhesive material. 【請求項４】 前記上層は、前記下層とは異なる粘着材
料からなることを特徴とする請求項２または３の半導体
装置の製造方法。4. The method for manufacturing a semiconductor device according to claim 2, wherein said upper layer is made of an adhesive material different from said lower layer. 【請求項５】 前記上層と前記下層は、それぞれ複数層
の粘着材料の層からなることを特徴とする請求項２〜４
のいずれかの半導体装置の製造方法。5. The method according to claim 2, wherein the upper layer and the lower layer each comprise a plurality of layers of an adhesive material.
Any one of the methods for manufacturing a semiconductor device.
JP10354042A 1998-12-14 1998-12-14 Manufacture of semiconductor device Withdrawn JP2000182995A (en)

Priority Applications (1)

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JP10354042A JP2000182995A (en) 1998-12-14 1998-12-14 Manufacture of semiconductor device

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Application Number Priority Date Filing Date Title
JP10354042A JP2000182995A (en) 1998-12-14 1998-12-14 Manufacture of semiconductor device

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