JP2008041707A - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor Download PDF

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JP2008041707A
JP2008041707A JP2006210092A JP2006210092A JP2008041707A JP 2008041707 A JP2008041707 A JP 2008041707A JP 2006210092 A JP2006210092 A JP 2006210092A JP 2006210092 A JP2006210092 A JP 2006210092A JP 2008041707 A JP2008041707 A JP 2008041707A
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substrate
semiconductor device
bonding layer
semiconductor element
bonding
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JP5050440B2 (en
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Masanori Yamagiwa
正憲 山際
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Nissan Motor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To prolong the lifetime of a semiconductor device where a semiconductor element is bonded to a substrate by a bonding layer. <P>SOLUTION: Materials for forming a bonding layer 3 and a substrate 1 are selected, such that the 0.2% yield strength of the bonding layer 3 is the same as or slightly higher than the 0.2% yield strength of the substrate 1 at the same temperature. Consequently, the displacement between a semiconductor element 2 and the substrate 1 is absorbed not by the bonding layer 3, but by the substrate 1 side. Since final breakdown phenomenon takes place on the substrate 1 side, exhibiting higher toughness and higher iteration fatigue strength for a predetermined strain, as compared with the bonding layer 3, the lifetime of the semiconductor device can be markedly prolonged. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体素子と基板の接合技術に関する。   The present invention relates to a bonding technique between a semiconductor element and a substrate.

一般に、半導体素子と金属基板を接合する際にははんだが用いられる。ところが、このはんだは、半導体素子と金属基板の熱膨張係数の差のために温度差によって発生する応力を自身が歪むことによって緩和するというメリットを有する反面、その繰り返しによってCoffin-Manson則（歪と疲労寿命の関係を示す法則）で示されるような劣化が発生するというデメリットを有する。   Generally, solder is used when joining a semiconductor element and a metal substrate. However, this solder has the merit of relaxing the stress generated by the temperature difference due to the difference in temperature due to the difference in the thermal expansion coefficient between the semiconductor element and the metal substrate, but on the other hand, the Coffin-Manson rule (strain and It has a demerit that deterioration occurs as shown by the law showing the relationship of fatigue life.

具体的には、実使用時、半導体素子の発熱によって半導体装置に温度変化が加わることによって熱膨張係数が異なる半導体素子と基板との間に変位が発生するために、半導体素子と基板間に存在するはんだには熱応力と熱歪が生じる。そして半導体素子の発熱が繰り返されることによってはんだの劣化が進み、遂には疲労寿命に達してクラックが発生する。この結果、半導体素子を冷却する放熱経路が遮断され、半導体素子が高温に晒されて破壊に至る。   Specifically, during actual use, a displacement occurs between a semiconductor element having a different coefficient of thermal expansion due to a temperature change applied to the semiconductor device due to heat generation of the semiconductor element. Thermal stress and thermal strain are generated in solder. Then, the heat generation of the semiconductor element is repeated, so that the deterioration of the solder progresses, and finally the fatigue life is reached and a crack is generated. As a result, the heat dissipation path for cooling the semiconductor element is blocked, and the semiconductor element is exposed to a high temperature to be destroyed.

このような背景から、近年、半導体素子の冷却能力を向上させて半導体素子と基板間の温度差を小さくすることにより半導体素子と基板間の変位を抑制する方法、半導体素子と基板間の熱膨張係数差を小さくすることにより半導体素子と基板間の変位を抑制する方法、半導体素子と基板間に変位が生じても接合部に熱応力や熱歪が集中しないように半導体素子や基板の形状を設計する方法等、はんだの寿命を延ばすための幾つかの方法が提案されている（特許文献１参照）。
特開２００３−３１７３２号公報 Against this background, in recent years, a method for suppressing the displacement between the semiconductor element and the substrate by improving the cooling capacity of the semiconductor element to reduce the temperature difference between the semiconductor element and the substrate, and the thermal expansion between the semiconductor element and the substrate A method of suppressing the displacement between the semiconductor element and the substrate by reducing the coefficient difference, and the shape of the semiconductor element and the substrate is prevented so that thermal stress and thermal strain are not concentrated on the joint even if the displacement occurs between the semiconductor element and the substrate. Several methods for extending the life of the solder, such as a designing method, have been proposed (see Patent Document 1).
JP 2003-31732 A

しかしながら、上記方法はいずれも、半導体素子と金属基板間の変位をその接合部であるはんだの歪により吸収しようとするものであり、その繰り返しによってはんだの劣化が進み遂には疲労寿命に達しクラックが発生するという初期の問題そのものを解決してはいない。即ち、接合部で応力緩和を行う従来の半導体装置構造によれば、多少の接合部の寿命改善ができたとしても、極端に温度差が大きくなったり、接合面積が増えたりした場合においては十分な改善策とは言えない。   However, all of the above methods attempt to absorb the displacement between the semiconductor element and the metal substrate by the distortion of the solder that is the joint, and the repeated deterioration of the solder eventually reaches the fatigue life and causes cracks. It does not solve the initial problem itself. That is, according to the conventional semiconductor device structure in which the stress is relaxed at the joint, even if the life of the joint can be improved to some extent, it is sufficient when the temperature difference becomes extremely large or the joint area increases. It cannot be said that it is a serious improvement measure.

本発明は、上記課題を解決するためになされたものであり、その目的は、寿命を飛躍的に向上可能な半導体装置及びその製造方法を提供することにある。   The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device and a method for manufacturing the same capable of dramatically improving the lifetime.

上述の課題を解決するために、本発明に係る半導体装置は、半導体素子と基板の接合材料の強度特性を指定することにより、半導体素子と基板間の変位を主に接合層ではなく基板側で吸収する。即ち、本発明に係る半導体装置は、接合層の０．２％耐力の大きさを同一温度において基板の０．２％耐力の大きさと同じ若しくはそれ以上とすることにより、半導体素子と基板間の変位を主に基板側で受け止めることが可能になる。   In order to solve the above-described problems, the semiconductor device according to the present invention specifies the strength characteristics of the bonding material between the semiconductor element and the substrate, thereby causing the displacement between the semiconductor element and the substrate mainly on the substrate side, not on the bonding layer. Absorb. That is, in the semiconductor device according to the present invention, the size of the 0.2% proof stress of the bonding layer is equal to or greater than the size of the 0.2% proof strength of the substrate at the same temperature. The displacement can be received mainly on the substrate side.

本発明に係る半導体装置及びその製造方法によれば、半導体素子と基板間の変位を接合層ではなく基板側で吸収するので、最終的な破壊現象は、接合層と比較して靱性が高く、ある一定の歪に対する繰り返し疲労強度が高い基板側において発生するようになり、半導体装置の寿命を飛躍的に向上させることができる。   According to the semiconductor device and the manufacturing method thereof according to the present invention, since the displacement between the semiconductor element and the substrate is absorbed on the substrate side instead of the bonding layer, the final breakdown phenomenon has high toughness compared to the bonding layer, It occurs on the substrate side where the repeated fatigue strength against a certain strain is high, and the life of the semiconductor device can be drastically improved.

以下、図面を参照して、本発明の実施形態となる半導体装置の構成について詳しく説明する。   Hereinafter, a configuration of a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings.

［半導体装置の構成］
〔第１の実施形態〕
本発明の第１の実施形態となる半導体装置は、図１に示すように、基板１と半導体素子２とを備え、基板１と半導体素子２は接合層３によって接合されている。基板１は金属材料又は有機物材料若しくは無機物材料と金属材料との複合材料により形成されている。接合層３は半導体材料は金属材料、又は有機物材料若しくは無機物と金属材料との複合材料により形成されている。 [Configuration of semiconductor device]
[First Embodiment]
As shown in FIG. 1, the semiconductor device according to the first embodiment of the present invention includes a substrate 1 and a semiconductor element 2, and the substrate 1 and the semiconductor element 2 are bonded by a bonding layer 3. The substrate 1 is formed of a metal material, an organic material, or a composite material of an inorganic material and a metal material. The bonding layer 3 is formed of a metal material or a composite material of an organic material or an inorganic material and a metal material as a semiconductor material.

この半導体装置では、図２に示すように、接合層３の０．２％耐力（若しくは降伏強度）σｙ２が同一温度において基板１の０．２％耐力σｙ１と同じ若しくはそれ以上になるように基板１と接合層３を形成する材料が選択されている。このような構造によれば、半導体装置に熱負荷が掛かり、半導体素子２と基板１の熱膨張差によって剪断方向に変位が生じた際、接合層３と比較して靱性が高く、ある一定の歪に対する繰り返し疲労強度が高い基板１が歪むことによって応力緩和されるので、半導体装置の寿命を向上させることができる。 In this semiconductor device, as shown in FIG. 2, the 0.2% yield strength (or yield strength) σy 2 of the bonding layer 3 is equal to or higher than the 0.2% yield strength σy 1 of the substrate 1 at the same temperature. A material for forming the substrate 1 and the bonding layer 3 is selected. According to such a structure, when a thermal load is applied to the semiconductor device and displacement occurs in the shearing direction due to a difference in thermal expansion between the semiconductor element 2 and the substrate 1, the toughness is higher than the bonding layer 3, and a certain level. Since the stress is relieved when the substrate 1 having high repeated fatigue strength against strain is distorted, the life of the semiconductor device can be improved.

なお、基板１をアルミニウム（Ａｌ）又はアルミニウム合金により形成した場合には、上述の０．２％耐力の関係を満たすために、接合層３はＡｌ，銅（Ｃｕ），金（Ａｕ），銀（Ａｇ）、鉄（Ｆｅ）、マグネシウム（Ｍｇ）、ニッケル（Ｎｉ）、パラジウム（Ｐｄ）、白金（Ｐｔ）、チタン（Ｔｉ）、亜鉛（Ｚｎ）のうちのいずれか又はこれら金属のうちのいずれかを含む合金により形成することが望ましい。   When the substrate 1 is formed of aluminum (Al) or an aluminum alloy, the bonding layer 3 is made of Al, copper (Cu), gold (Au), silver in order to satisfy the above-described 0.2% proof stress relationship. (Ag), iron (Fe), magnesium (Mg), nickel (Ni), palladium (Pd), platinum (Pt), titanium (Ti), zinc (Zn), or any of these metals It is desirable to form by the alloy containing these.

また、基板１を銅（Ｃｕ）又は銅合金により形成した場合には、上述の０．２％耐力の関係を満たすために、接合層３は、Ｃｕ、Ｆｅ、Ｔｉのうちのいずれか又はこれら金属のうちのいずれかを含む合金により形成することが望ましい。   In addition, when the substrate 1 is formed of copper (Cu) or a copper alloy, the bonding layer 3 is either Cu, Fe, or Ti in order to satisfy the above-described 0.2% proof stress relationship. It is desirable to form with the alloy containing any of metals.

〔第２の実施形態〕
本発明の第２の実施形態となる半導体装置では、上記第１の実施形態となる半導体装置構造において、基板１の厚さｔ１が接合層３の厚さｔ２以上の大きさになっている（図１参照）。このような構造によれば、一定の発生変位に対して歪を分かち合う基板１の体積が増えことによって、応力や歪が基板１に局所的に集中しなくなり、基板１全体で応力や歪を吸収することができるようになるので、基板１や接合層３の疲労をさらに低減し、半導体装置の寿命をさらに向上させることができる。 [Second Embodiment]
In the semiconductor device according to the second embodiment of the present invention, in the semiconductor device structure according to the first embodiment, the thickness t1 of the substrate 1 is not less than the thickness t2 of the bonding layer 3 ( (See FIG. 1). According to such a structure, the volume of the substrate 1 that shares the strain with respect to a certain generated displacement increases, so that stress and strain are not concentrated locally on the substrate 1, and the stress and strain are reduced throughout the substrate 1. Since it can be absorbed, fatigue of the substrate 1 and the bonding layer 3 can be further reduced, and the life of the semiconductor device can be further improved.

〔第３の実施形態〕
本発明の第３の実施形態となる半導体装置では、上記第１又は第２の実施形態となる半導体装置構造において、図３に示すように、半導体素子２の引張破壊強度σｔ２の大きさが同一温度において基板１の引張破壊強度の大きさσｔ１と同じ若しくはそれ以上になるように基板１及び半導体素子２を形成する材料が選択されている。接合層を高強度に形成することによって基板１に発生する歪を極力低減するために、基板１を形成する材料として、極端に硬い金属材料を用いたり、歪の蓄積によって加工硬化することにより極端に硬くなる金属材料を用いた場合、半導体素子２自体が破壊する可能性がある。従ってこのような構造によれば、基板１に発生する応力によって半導体素子２が破壊されることを防止できるので、半導体装置の信頼性をさらに向上させることができる。 [Third Embodiment]
In the semiconductor device according to the third embodiment of the present invention, in the semiconductor device structure according to the first or second embodiment, the tensile fracture strength σt 2 of the semiconductor element 2 has a magnitude as shown in FIG. the material forming the substrate 1 and the semiconductor element 2 to be equal to or greater than the size .sigma.t 1 tensile breaking strength of the substrate 1 at the same temperature is selected. In order to reduce the distortion generated in the substrate 1 as much as possible by forming the bonding layer with high strength, an extremely hard metal material is used as the material for forming the substrate 1 or the work is hardened by accumulation of strain. When a hard metal material is used, the semiconductor element 2 itself may be destroyed. Therefore, according to such a structure, it is possible to prevent the semiconductor element 2 from being broken by the stress generated in the substrate 1, so that the reliability of the semiconductor device can be further improved.

〔第４の実施形態〕
本発明の第４の実施形態となる半導体装置では、上記第１乃至第３の実施形態となる半導体装置構造のいずれかにおいて、図４に示すように、少なくとも基板１と接合層３の界面に形成された薄膜４を有し、基板１に対する薄膜４の密着強度及び薄膜４自体の引張破壊強度の大きさが同一温度において基板１の０．２％耐力の大きさと同じ若しくはそれ以上になるように薄膜４が形成されている。このような構成によれば、薄膜４が基板１から剥離したり、薄膜４が破壊されることがないので、半導体装置の寿命をより確実に向上させることができる。 [Fourth Embodiment]
In the semiconductor device according to the fourth embodiment of the present invention, in any of the semiconductor device structures according to the first to third embodiments, at least at the interface between the substrate 1 and the bonding layer 3 as shown in FIG. The thin film 4 is formed and the adhesion strength of the thin film 4 to the substrate 1 and the tensile fracture strength of the thin film 4 itself are equal to or greater than the 0.2% proof stress of the substrate 1 at the same temperature. A thin film 4 is formed. According to such a configuration, since the thin film 4 is not peeled off from the substrate 1 or the thin film 4 is not destroyed, the life of the semiconductor device can be improved more reliably.

〔第５の実施形態〕
本発明の第５の実施形態となる半導体装置では、上記第１乃至第４の実施形態となる半導体装置構造のいずれかにおいて、図５〜図８に示すように基板１が突出面Ａを有し、接合層３は突出面Ａ上において基板１と接合している。このような構成によれば、基板１の剛性が上がることによって基板１自体の反りを抑制でき、反りによって半導体素子２，接合層３，及び基板１に新たに発生する応力を緩和することができるので、接合後の冷却によって生じる残留応力により基板１自体や半導体素子２側面や接合層３にクラックが発生することを防止できる。 [Fifth Embodiment]
In the semiconductor device according to the fifth embodiment of the present invention, in any one of the semiconductor device structures according to the first to fourth embodiments, the substrate 1 has the protruding surface A as shown in FIGS. The bonding layer 3 is bonded to the substrate 1 on the protruding surface A. According to such a configuration, warping of the substrate 1 itself can be suppressed by increasing the rigidity of the substrate 1, and stress newly generated in the semiconductor element 2, the bonding layer 3, and the substrate 1 can be relieved by the warping. Therefore, it is possible to prevent the occurrence of cracks in the substrate 1 itself, the side surface of the semiconductor element 2 and the bonding layer 3 due to residual stress generated by cooling after bonding.

なお、上記剛性とは材料に力を加えた場合にどの程度変形し難いかを示す。突出面Ａを設けた場合、一定の発生変位に対して歪を分かち合う面積（又は体積）が増えるので、その分ミクロ的に歪も応力も小さくて済むと考えられる。また、接合後の熱負荷によって基板１に発生する歪が弾性歪である場合には、基板１に与えられる熱疲労は最小限に抑えられ、特に有効で画期的な寿命向上が可能になる。加えて、最終的に塑性歪が蓄積して基板１にクラックが入ったとしても、そのクラック方向が半導体装置としての電気・熱経路に大きく影響を与えない方向になるので、半導体装置の損傷を小さく抑えられ、結果的により一層の寿命向上が望める。   The rigidity indicates how hard the material is deformed when a force is applied to the material. When the projecting surface A is provided, the area (or volume) for sharing the strain with respect to a certain generated displacement increases, so it is considered that the strain and the stress can be reduced microscopically. In addition, when the strain generated in the substrate 1 due to the thermal load after bonding is an elastic strain, the thermal fatigue applied to the substrate 1 can be minimized, and a particularly effective and epoch-making life can be improved. . In addition, even if the plastic strain eventually accumulates and cracks occur in the substrate 1, the crack direction is in a direction that does not significantly affect the electrical / thermal path of the semiconductor device. As a result, the lifetime can be further improved.

〔第６の実施形態〕
本発明の第６の実施形態となる半導体装置では、上記第５の実施形態となる半導体装置構造において、図９や図１０に示すように、突出面Ａが突出面Ａの側面部と半導体素子２の側面部との間の距離が半導体素子２の側面形状の角部において最短になるように形成されている。このような構成によれば、図１１（ａ）に示すような応力集中領域Ｒ１を図１１（ｂ）に示す領域Ｒ２のように分散させることによって、半導体素子２の角部周辺に応力が集中することを防止できる。 [Sixth Embodiment]
In the semiconductor device according to the sixth embodiment of the present invention, in the semiconductor device structure according to the fifth embodiment, as shown in FIGS. 9 and 10, the protruding surface A is a side surface portion of the protruding surface A and the semiconductor element. The distance between the two side surfaces is formed to be the shortest at the corner of the side surface shape of the semiconductor element 2. According to such a configuration, stress is concentrated around the corner of the semiconductor element 2 by dispersing the stress concentration region R1 as shown in FIG. 11A like the region R2 shown in FIG. Can be prevented.

［半導体装置の製造方法］
次に、上記半導体装置の製造方法の幾つかの実施例について説明する。 [Method for Manufacturing Semiconductor Device]
Next, several embodiments of the semiconductor device manufacturing method will be described.

〔実施例１〕
実施例１では、始めに、Ａｌとセラミックスから成るＡｌセラミックス絶縁基板により形成された基板１表面上にＡｌＳｉ系ロウ材により形成された接合層３を配置し、接合層３表面上にＳｉにより形成された高耐熱半導体素子２を配置した。次に、半導体素子２表面上に重りを配置し、６００［℃］程度の雰囲気の真空炉内で加熱することにより実施例１の半導体装置を得た。なお、接合層３を形成するＡｌＳｉ系ロウ材の融点は約５８０［℃］であるので、基板１と半導体素子２を接合する際の接合雰囲気の温度は６００［℃］程度とした。この実施例１における基板１と接合層３の０．２％耐力の大小関係、及び基板１と半導体素子２の引張破壊強度（引張強度）の大小関係を以下の表１に示す。この実施例１では、基板１はＡｌセラミックス絶縁基板により形成され、接合後の冷却時に生じるＡｌの収縮をセラミックスがある程度抑制するので、基板１の反りを抑え、製造時の残留応力を極力少なくすることができる。またこの結果、半導体素子２にクラックが入ったり、接合層３が剥離したりすることを防止できる。 [Example 1]
In Example 1, first, a bonding layer 3 formed of an AlSi brazing material is disposed on the surface of a substrate 1 formed of an Al ceramic insulating substrate made of Al and ceramics, and formed on the surface of the bonding layer 3 with Si. The high heat-resistant semiconductor element 2 was disposed. Next, a semiconductor device of Example 1 was obtained by placing a weight on the surface of the semiconductor element 2 and heating in a vacuum furnace in an atmosphere of about 600 [° C.]. Since the melting point of the AlSi brazing material forming the bonding layer 3 is about 580 [° C.], the temperature of the bonding atmosphere when bonding the substrate 1 and the semiconductor element 2 is about 600 [° C.]. Table 1 below shows the magnitude relationship between the 0.2% yield strength of the substrate 1 and the bonding layer 3 and the magnitude relationship between the tensile fracture strength (tensile strength) of the substrate 1 and the semiconductor element 2 in Example 1. In the first embodiment, the substrate 1 is formed of an Al ceramic insulating substrate, and the ceramic suppresses the Al shrinkage to some extent during cooling after bonding. Therefore, the warpage of the substrate 1 is suppressed, and the residual stress during manufacturing is minimized. be able to. As a result, it is possible to prevent the semiconductor element 2 from cracking and the bonding layer 3 from peeling off.

〔実施例２〕
実施例２では、始めに、図１２（ａ）に示すように、Ｃｕにより形成された基板１と半導体素子２の少なくとも一方の接合面に粒径１０［ｎｍ］前後のＣｕナノ粒子粉末（又はＣｕナノ合金粒子粉末）５を吹き付けた。一般に、金属をナノレベルまで小さくすると、表面エネルギーが増加することによってバルク本来の融点以下の温度でも溶解するようになる。また、ナノ粒子の融点は粒径が小さい程低く、粒径が大きくなるにつれてバルク本来の融点に近づくことが知られている。このため、室温でＣｕナノ粒子を塗布し、図１２（ｂ）に示すように基板１と半導体素子２の接合面を重ねて３００［℃］程度に加熱し、図１２（ｃ）に示すように基板１と半導体素子２を接合することで実施例２の半導体装置を得た。なお、この時、より安定した接合層３を形成するために加圧してもよい。この実施例２における基板１と接合層３の０．２％耐力の大小関係、及び基板１と半導体素子２の引張破壊強度（引張強度）の大小関係を以下の表１に示す。この実施例２では、接合層３の耐熱温度はバルクのＣｕと同様１０００［℃］以上になるので、半導体素子２として高耐熱素子等を用いた場合であっても高い接合信頼性を得することができる。なお、この実施例２では、表１に示すように接合層３の０．２％耐力は同一温度において基板１の０．２％耐力と同じ大きさであるが、接合層３をＣｕ合金ナノ粒子により形成することにより、接合層３の０．２％耐力は同一温度において基板１の０．２％耐力以上の大きさになるので、接合層３をＣｕにより形成した場合よりも接合層３に発生する歪を更に低減することができる。 [Example 2]
In Example 2, first, as shown in FIG. 12 (a), Cu nanoparticle powder having a particle size of around 10 [nm] on the bonding surface of at least one of the substrate 1 and the semiconductor element 2 formed of Cu (or Cu nanoalloy particle powder) 5 was sprayed. In general, when the metal is reduced to the nano level, the surface energy increases, so that the metal melts even at a temperature lower than the original melting point of the bulk. Further, it is known that the melting point of the nanoparticles is lower as the particle size is smaller, and approaches the original melting point of the bulk as the particle size increases. For this reason, Cu nanoparticles are applied at room temperature, and the bonding surfaces of the substrate 1 and the semiconductor element 2 are overlapped and heated to about 300 [° C.] as shown in FIG. 12B, as shown in FIG. The semiconductor device of Example 2 was obtained by bonding the substrate 1 and the semiconductor element 2 to each other. At this time, pressure may be applied to form a more stable bonding layer 3. Table 1 below shows the magnitude relationship between the 0.2% yield strength of the substrate 1 and the bonding layer 3 in Example 2 and the magnitude relationship between the tensile fracture strength (tensile strength) of the substrate 1 and the semiconductor element 2. In Example 2, since the heat resistance temperature of the bonding layer 3 is 1000 [° C.] or more like bulk Cu, high bonding reliability can be obtained even when a high heat resistance element or the like is used as the semiconductor element 2. Can do. In Example 2, as shown in Table 1, the 0.2% yield strength of the bonding layer 3 is the same as the 0.2% yield strength of the substrate 1 at the same temperature. By forming with the particles, the 0.2% proof stress of the bonding layer 3 is greater than the 0.2% proof stress of the substrate 1 at the same temperature. Therefore, the bonding layer 3 is more than the case where the bonding layer 3 is formed of Cu. Can be further reduced.

〔実施例３〕
実施例３では、始めに、Ａｌにより形成された基板１の接合面にＡｇめっき処理を施した。なお、Ａｇめっき界面の密着強度及びＡｇめっき自体の引張破壊強度は基板１（Ａｌ）の０．２％耐力よりも大きくする。Ａｇめっき密着強度を向上させるためには、Ａｇめっき前に基板１の接合面に表面処理を施す方法が有効である。例えば、脱脂やエッチング等によって基板１表面を洗浄したり、下地めっきを改善したりすることによって、Ａｇめっきの密着性を格段に向上することができる。また、一般的に電解めっきは無電解めっきに比べて緻密で高強度であり且つ母材への密着性が高いと言われているので、併せて利用できる。また、めっきはＡｇに限らず、ＣｕやＡｕ等であってもよい。次に、接合層３としてペースト化したＣｕＳｎ系ろう材をＡｇめっき処理が施された基板１に塗布した後、半導体素子２をＡｇめっき上に配置して２５０〜３００［℃］程度の温度範囲で加熱接合することにより、実施例３の半導体装置を得た。この実施例３における基板１と接合層３の０．２％耐力の大小関係、基板１と半導体素子２の引張破壊強度（引張強度）の大小関係、及びＡｇめっきの密着強度を以下の表１に示す。この実施例３では、比較的柔らかく靭性の高く、ある一定の歪に対する繰り返し疲労強度が高い基板１側の純Ａｌによる応力緩和が可能となり、接合層３の寿命が大幅に向上する。なお、基板１は純Ａｌではなく、Ａｌ合金や純Ｃｕであっても構わない。特に純Ｃｕの基板でＣｕＳｎ系ろう材を用いる場合はめっきは不要である。また、ＣｕＳｎろう材とは、溶融したＳｎがＣｕへ拡散することで合金化し融点が上がることを応用したものである。また、Ａｇめっきの強度は、Ａｇめっきが形成された基板１と試験用の治具とをＣｕＳｎ系ろう材で接合したもの、又はＡｇめっきが形成された基板１と半導体素子２とをＣｕＳｎ系ろう材で接合し、その後改めてどちらか一方を試験用の治具と接合又は固定したものを用いて引張試験を行い、Ａｇめっき中またはＡｇめっき界面に亀裂が入る前に基板１が変形し始めたらＡｇめっき自体の引張破壊強度及び密着強度は基板１の０．２％耐力より高いとすることにより、評価することができる。

Figure 2008041707
Example 3
In Example 3, first, Ag plating treatment was performed on the bonding surface of the substrate 1 formed of Al. The adhesion strength at the Ag plating interface and the tensile fracture strength of the Ag plating itself are made larger than the 0.2% proof stress of the substrate 1 (Al). In order to improve the Ag plating adhesion strength, it is effective to perform a surface treatment on the bonding surface of the substrate 1 before Ag plating. For example, the adhesion of Ag plating can be remarkably improved by cleaning the surface of the substrate 1 by degreasing, etching, or the like, or by improving the base plating. In general, it is said that electrolytic plating is denser and higher in strength than electroless plating and has high adhesion to a base material, and thus can be used together. Further, the plating is not limited to Ag, but may be Cu, Au, or the like. Next, after pasting the CuSn brazing material pasted as the bonding layer 3 onto the substrate 1 that has been subjected to the Ag plating treatment, the semiconductor element 2 is placed on the Ag plating and a temperature range of about 250 to 300 [° C.]. Thus, the semiconductor device of Example 3 was obtained. Table 1 below shows the magnitude relationship between the 0.2% yield strength of the substrate 1 and the bonding layer 3, the magnitude relationship between the tensile fracture strength (tensile strength) of the substrate 1 and the semiconductor element 2, and the adhesion strength of Ag plating. Shown in In Example 3, stress relaxation by the pure Al on the substrate 1 side that is relatively soft and high in toughness and has high repeated fatigue strength against a certain strain is possible, and the life of the bonding layer 3 is greatly improved. The substrate 1 may be Al alloy or pure Cu instead of pure Al. In particular, when a CuSn brazing material is used on a pure Cu substrate, plating is unnecessary. Further, the CuSn brazing material is an application of the fact that molten Sn diffuses into Cu to form an alloy and raise the melting point. In addition, the strength of Ag plating is such that a substrate 1 on which Ag plating is formed and a test jig are joined with a CuSn brazing material, or a substrate 1 on which Ag plating is formed and a semiconductor element 2 are CuSn based. A tensile test is conducted using a brazing material and either one of them is joined or fixed to a test jig, and the substrate 1 begins to deform during the Ag plating or before the Ag plating interface cracks. Then, the tensile fracture strength and adhesion strength of the Ag plating itself can be evaluated by making them higher than the 0.2% proof stress of the substrate 1.
Figure 2008041707

［シミュレーションによる検討］
最後に、本発明の効果を検証するために、接合層３がＰｂＳｎにより形成された従来の半導体装置構造と接合層３がＡｇにより形成された本願発明の半導体装置構造それぞれについて、接合層３及び基板１のMises応力，Max応力，及びMax歪をシミュレーションにより評価した結果を以下の表２，３に示す。なお、シミュレーションにおいては、半導体素子２のヤング率を４００［ＧＰａ］に設定し、基板１としてＡｌ基板を用いた。また、ＰｂＳｎ，Ａｇ，及びＡｌには公知の材料特性を設定し、熱負荷として１５０［℃］から−５０［℃］に冷却する負荷を半導体装置に与えた。

Figure 2008041707
Figure 2008041707
 [Study by simulation]
Finally, in order to verify the effect of the present invention, the conventional semiconductor device structure in which the bonding layer 3 is formed of PbSn and the semiconductor device structure of the present invention in which the bonding layer 3 is formed of Ag, respectively, The results of evaluating the Mises stress, Max stress, and Max strain of the substrate 1 by simulation are shown in Tables 2 and 3 below. In the simulation, the Young's modulus of the semiconductor element 2 was set to 400 [GPa], and an Al substrate was used as the substrate 1. Also, known material characteristics were set for PbSn, Ag, and Al, and a load for cooling from 150 [° C.] to −50 [° C.] was given to the semiconductor device as a heat load.
Figure 2008041707
Figure 2008041707

表２，３に示すように、従来の半導体装置構造の場合、温度変化によって受ける損傷は接合層３のＰｂＳｎに集中し、１サイクルで９．４［％］の歪量が発生した。これに対して、本願発明の半導体装置構造の場合には、基板１のＡｌと接合層３のＡｇとが温度変化によって受ける損傷を分かち合い、１サイクルで発生した歪量はそれぞれ０．５［％］と０．６［％］であった。以上の結果と一定の歪に対する繰り返し疲労強度がＰｂＳｎに比べＡｌの方が高いことから、本願発明の半導体装置構造によれば、半導体装置の寿命を向上できることが証明される。   As shown in Tables 2 and 3, in the case of the conventional semiconductor device structure, the damage caused by the temperature change was concentrated on the PbSn of the bonding layer 3 and a strain amount of 9.4 [%] was generated in one cycle. On the other hand, in the case of the semiconductor device structure of the present invention, the damage of the Al of the substrate 1 and the Ag of the bonding layer 3 caused by temperature change is shared, and the amount of strain generated in one cycle is 0.5 [ %] And 0.6 [%]. From the above results and the fact that the repeated fatigue strength for a certain strain is higher in Al than in PbSn, it is proved that the life of the semiconductor device can be improved according to the semiconductor device structure of the present invention.

以上、本発明者によってなされた発明を適用した実施の形態について説明したが、この実施の形態による本発明の開示の一部をなす論述及び図面により本発明は限定されることはない。すなわち、この実施の形態に基づいて当業者等によりなされる他の実施の形態、実施例及び運用技術等は全て本発明の範疇に含まれることは勿論であることを付け加えておく。   As mentioned above, although the embodiment to which the invention made by the present inventor is applied has been described, the present invention is not limited by the description and the drawings that form part of the disclosure of the present invention according to this embodiment. That is, it should be added that other embodiments, examples, operation techniques, and the like made by those skilled in the art based on this embodiment are all included in the scope of the present invention.

本発明の第１の実施形態となる半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device used as the 1st Embodiment of this invention. 接合層の０．２％耐力と基板の０．２％耐力の関係を説明するための応力−歪曲線である。It is a stress-strain curve for demonstrating the relationship between the 0.2% yield strength of a joining layer, and the 0.2% yield strength of a board | substrate. 基板の引張破壊強度と半導体素子の引張破壊強度の関係を説明するための応力−歪曲線である。It is a stress-strain curve for demonstrating the relationship between the tensile fracture strength of a board | substrate and the tensile fracture strength of a semiconductor element. 本発明の第４の実施形態となる半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device used as the 4th Embodiment of this invention. 本発明の第５の実施形態となる半導体装置の一構成例を示す断面図である。It is sectional drawing which shows one structural example of the semiconductor device which becomes the 5th Embodiment of this invention. 本発明の第５の実施形態となる半導体装置の一構成例を示す断面図である。It is sectional drawing which shows one structural example of the semiconductor device which becomes the 5th Embodiment of this invention. 本発明の第５の実施形態となる半導体装置の一構成例を示す断面図である。It is sectional drawing which shows one structural example of the semiconductor device which becomes the 5th Embodiment of this invention. 本発明の第５の実施形態となる半導体装置の一構成例を示す断面図である。It is sectional drawing which shows one structural example of the semiconductor device which becomes the 5th Embodiment of this invention. 本発明の第６の実施形態となる半導体装置の一構成例を示す断面図である。It is sectional drawing which shows one structural example of the semiconductor device which becomes the 6th Embodiment of this invention. 本発明の第６の実施形態となる半導体装置の一構成例を示す断面図である。It is sectional drawing which shows one structural example of the semiconductor device which becomes the 6th Embodiment of this invention. 図９及び図１０に示す半導体装置の構成による技術的効果を説明するための図である。It is a figure for demonstrating the technical effect by the structure of the semiconductor device shown in FIG.9 and FIG.10. 本発明の実施形態となる半導体装置の製造方法を示す断面工程図である。It is sectional process drawing which shows the manufacturing method of the semiconductor device used as embodiment of this invention.

符号の説明Explanation of symbols

１：基板
２：半導体素子
３：接合層
４：薄膜
５：Ｃｕナノ粉末（又はＣｕナノ合金粉末） 1: Substrate 2: Semiconductor element 3: Bonding layer 4: Thin film 5: Cu nano powder (or Cu nano alloy powder)

Claims (10)

半導体素子と基板を有し、半導体素子と基板が接合層によって接合されている半導体装置において、前記接合層の０．２％耐力の大きさが同一温度において前記基板の０．２％耐力の大きさと同じ若しくはそれ以上であることを特徴とする半導体装置。   In a semiconductor device having a semiconductor element and a substrate, and the semiconductor element and the substrate are bonded together by a bonding layer, the bonding layer has a 0.2% proof stress of 0.2% proof strength of the substrate at the same temperature. A semiconductor device characterized by being equal to or higher than 請求項１に記載の半導体装置において、前記基板はアルミニウム又はアルミニウム合金により形成され、前記接合層はアルミニウム、銅、金、銀、鉄、マグネシウム、ニッケル、パラジウム、白金、チタン、亜鉛のうちのいずれか又はこれら金属のうちのいずれかを含む合金により形成されていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the substrate is formed of aluminum or an aluminum alloy, and the bonding layer is any one of aluminum, copper, gold, silver, iron, magnesium, nickel, palladium, platinum, titanium, and zinc. Or an alloy containing any of these metals. 請求項１に記載の半導体装置において、前記基板は銅又は銅合金により形成され、前記接合層は銅、鉄、チタンのうちのいずれか又はこれら金属のうちのいずれかを含む合金により形成されていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the substrate is made of copper or a copper alloy, and the bonding layer is made of copper, iron, titanium, or an alloy containing any of these metals. A semiconductor device characterized by comprising: 請求項１乃至請求項３のうち、いずれか１項に記載の半導体装置において、前記基板の厚さは前記接合層の厚さ以上の大きさであることを特徴とする半導体装置。   4. The semiconductor device according to claim 1, wherein a thickness of the substrate is greater than or equal to a thickness of the bonding layer. 5. 請求項１乃至請求項４のうち、いずれか１項に記載の半導体装置において、前記半導体素子の引張破壊強度の大きさが同一温度において前記基板の引張破壊強度の大きさと同じ若しくはそれ以上であることを特徴とする半導体装置。   5. The semiconductor device according to claim 1, wherein the tensile strength of the semiconductor element is equal to or greater than the tensile strength of the substrate at the same temperature. 6. A semiconductor device. 請求項１乃至請求項５のうち、いずれか１項に記載の半導体装置において、少なくとも前記基板と前記接合層の界面に形成された薄膜を有し、基板に対する薄膜の密着強度及び薄膜自体の引張破壊強度の大きさが同一温度において基板の０．２％耐力の大きさと同じ若しくはそれ以上であることを特徴とする半導体装置。   6. The semiconductor device according to claim 1, further comprising a thin film formed at least at an interface between the substrate and the bonding layer, the adhesion strength of the thin film to the substrate, and the tensile strength of the thin film itself. A semiconductor device characterized in that the magnitude of the breaking strength is equal to or greater than the magnitude of the 0.2% proof stress of the substrate at the same temperature. 請求項１乃至請求項６のうち、いずれか１項に記載の半導体装置において、前記基板は突出面を有し、前記接合層は突出面において基板と接合していることを特徴とする半導体装置。   7. The semiconductor device according to claim 1, wherein the substrate has a protruding surface, and the bonding layer is bonded to the substrate at the protruding surface. . 請求項７に記載の半導体装置において、前記突出面は突出面の側面部と前記半導体素子の側面部との間の距離が半導体素子の側面形状の角部において最短になるように形成されていることを特徴とする半導体装置。   8. The semiconductor device according to claim 7, wherein the protruding surface is formed such that the distance between the side surface portion of the protruding surface and the side surface portion of the semiconductor element is the shortest at the corner portion of the side surface shape of the semiconductor element. A semiconductor device. 請求項１乃至請求項８のうち、いずれか１項に記載の半導体装置において、前記接合層の融点は前記基板の融点よりも高いことを特徴とする半導体装置。   9. The semiconductor device according to claim 1, wherein a melting point of the bonding layer is higher than a melting point of the substrate. 請求項１乃至請求項９のうち、いずれか１項に記載の半導体装置の製造方法であって、前記半導体素子の接合面と前記基板の接合面の少なくとも一方に金属ナノ粒子を積層した後、半導体素子と基板の接合面を重ねて加熱接合する工程を有することを特徴とする半導体装置の製造方法。   The method for manufacturing a semiconductor device according to any one of claims 1 to 9, wherein metal nanoparticles are stacked on at least one of a bonding surface of the semiconductor element and a bonding surface of the substrate, A method for manufacturing a semiconductor device, comprising a step of heating and bonding a bonding surface between a semiconductor element and a substrate.
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