JPS61156824A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61156824A
JPS61156824A JP59276077A JP27607784A JPS61156824A JP S61156824 A JPS61156824 A JP S61156824A JP 59276077 A JP59276077 A JP 59276077A JP 27607784 A JP27607784 A JP 27607784A JP S61156824 A JPS61156824 A JP S61156824A
Authority
JP
Japan
Prior art keywords
layer
semiconductor device
element chip
lead frame
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59276077A
Other languages
Japanese (ja)
Inventor
Momoko Takemura
竹村　モモ子
Michihiko Inaba
道彦 稲葉
Toshio Tetsuya
鉄矢　俊夫
Mitsuo Kobayashi
三男 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59276077A priority Critical patent/JPS61156824A/en
Priority to US06/804,617 priority patent/US4954870A/en
Priority to DE8585309170T priority patent/DE3581905D1/en
Priority to EP85309170A priority patent/EP0186411B1/en
Priority to KR1019850009521A priority patent/KR900008971B1/en
Priority to CN85109419A priority patent/CN85109419B/en
Publication of JPS61156824A publication Critical patent/JPS61156824A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H01L23/4924—Bases or plates or solder therefor characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/001—Interlayers, transition pieces for metallurgical bonding of workpieces
    • B23K2035/008—Interlayers, transition pieces for metallurgical bonding of workpieces at least one of the workpieces being of silicium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0104—Zirconium [Zr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01041—Niobium [Nb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To obtain a low-cost semiconductor device which is unliable to incur imperfect contact, peeling and other deterioration of electric characteristics by interlaying a particular metal layer between the soldering member and the semiconductor device chip. CONSTITUTION:Three metal layers: a V layer 12; a layer 13 comprizing one of Ti, Cr, Zr and Nb; an Sn-Cu alloy layer 14 -soldering material- are succes sively evaporated onto the bottom side of an Si substrate 11 on the other side of which plural NPN transistors, 11a, 11b,... are formed. Then each transistor chip dissected is firmly connected to a Cu lead frame 15 at the temperature of 450 deg.C.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置に係り、特に素子チ、ツブをリード
フレームのような配設台に固定する部分の改良を図った
装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and more particularly to a device with an improved portion for fixing element chips and tabs to a mounting base such as a lead frame.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

トランジスタ等の半導体素子チップをリードフレームに
接合した様子を第４図に示すｅｌが素子チップ、２がリ
ードフレームであり、３．３′はボンディングワイヤで
ある。FIG. 4 shows how a semiconductor element chip such as a transistor is bonded to a lead frame. El is the element chip, 2 is the lead frame, and 3.3' is a bonding wire.

従来第４図のように、半導体素子チップをリードフレー
ムなどに配設する場合、予め素子チップ底面にバナジウ
ム（Ｖ）層を被着し、更にこのＶ層に重ねてニッケル（
Ｎｉ）！ｌを被着して、Ｎ１層とリードフレームの間を
金・ゲルマニウム（Ａｕ−Ｇｅ）合金からなるろう材に
より接合する構造が知られている（特願昭５３−９１４
１５号。Conventionally, as shown in Fig. 4, when a semiconductor element chip is placed on a lead frame or the like, a vanadium (V) layer is deposited on the bottom surface of the element chip in advance, and then a nickel (V) layer is applied on top of this V layer.
Ni)! There is a known structure in which the N1 layer and the lead frame are bonded using a brazing filler metal made of a gold-germanium (Au-Ge) alloy (Japanese Patent Application No. 53-914).
No. 15.

特願昭５３−９１４１６号等）。(Japanese Patent Application No. 53-91416, etc.)

しかしこの構造には次のような欠点があった。However, this structure had the following drawbacks.

第１に、素子チップをリードフレームに接合する際に３
２０℃以上に加熱すると、Ｎｉ層と素子チップのシリコ
ン（Ｓ　ｉ　）とが反応してニッケルシリサイドを形成
し易い。Ｎｉｌ！ｌと素子チップめＳｉとの間にはＶ層
があるが、通常素子チップ底面は接合層との接着性向上
のため平滑ではなくミクロンオーダーの凹凸が形成され
ており、またＶ層の厚みにもバラツキがあって、加熱し
た時にＮｉが素子チップ底面まで容易に拡散するからで
ある。First, when bonding the element chip to the lead frame, 3
When heated to 20° C. or higher, the Ni layer and silicon (S i ) of the element chip tend to react and form nickel silicide. Nil! There is a V layer between L and the Si element chip, but normally the bottom surface of the element chip is not smooth but has micron-order irregularities to improve adhesion with the bonding layer, and the thickness of the V layer This is because there are also variations, and when heated, Ni easily diffuses to the bottom surface of the element chip.

ニッケルシリサイドはそれ自体脆く、しかもその生成過
程で密度変化に伴う体積収縮が大きく、多量の空孔が発
生して接触不良やはがれ等、信頼性を低下させる原因と
なる。第２に、ろう材は主成分が金であるため高価であ
り、半導体装置のコスト高の原因となっている。Nickel silicide itself is brittle, and moreover, during its formation process, its volumetric shrinkage is large due to changes in density, and a large number of pores are generated, causing poor contact, peeling, and other problems that reduce reliability. Second, since the brazing filler metal is mainly composed of gold, it is expensive and is a cause of high costs for semiconductor devices.

一方、半導体素子チップ底面にＶ層を被着し、更にＮｉ
層を被着して、これを錫・銅（Ｓｎ−ＣＵ）合金からな
るろう材でリードフレームに接合する構造も知られてい
る（特願昭５８−６６３４０号）。On the other hand, a V layer is deposited on the bottom surface of the semiconductor element chip, and a Ni
A structure is also known in which a layer is deposited and then bonded to a lead frame using a brazing filler metal made of a tin-copper (Sn-CU) alloy (Japanese Patent Application No. 58-66340).

この構造では、ろう材が先の例に比べて安価であるが、
先の例での第１の欠点は解決されず残っている。またこ
の構造の場合、Ｃｕの半導体素子チップへの拡散により
例えばｎｐｎトランジスタではＶｃＥ（ｓａｔなどの電
気的特性が劣化する、という問題がある。これは、Ｎｉ
中のＣｕの拡散係数が小さいにも拘らず、４００℃付近
ではＮｉとＣＵの相互拡散がおこり、Ｎｉ！！がＣｕ拡
散の障壁としての機能を果たさなくなるためと考えられ
ている。Ｎｉと素子チップの間にはｖ層があるがこれも
厚さが２００〜１０００人程度であり、定押拡散の障壁
としては十分ではない。In this structure, the filler metal is cheaper than in the previous example, but
The first drawback of the previous example remains unresolved. In addition, with this structure, there is a problem that the electrical characteristics such as VcE (sat) of an npn transistor deteriorate due to the diffusion of Cu into the semiconductor element chip.
Although the diffusion coefficient of Cu inside is small, mutual diffusion between Ni and CU occurs at around 400°C, and Ni! ! It is thought that this is because it no longer functions as a barrier to Cu diffusion. Although there is a V layer between the Ni and the element chip, the thickness of this layer is about 200 to 1000 layers, which is not sufficient as a barrier to constant diffusion.

〔発明の目的〕[Purpose of the invention]

本発明は上記した点に鑑みなされたもので、素子の電気
的特性を劣化させることなく、接触不良やはがれ等も生
じ難く、かつ低コスト化が可能なチップ配設構造をもっ
た半導体装置を提供することを目的とする。The present invention has been made in view of the above points, and provides a semiconductor device having a chip arrangement structure that does not deteriorate the electrical characteristics of the element, is less likely to cause poor contact or peeling, and can reduce costs. The purpose is to provide.

〔発明の概要〕[Summary of the invention]

本発明は、錫・銅合金からなるろう材により半導体素子
チップを配設台に接合して固定する構造において、ろう
材と半導体素子チップの間に、チタニウム（Ｔｉ）、ク
ロム（Ｃｒ）、ジルコニウム（Ｚｒ）、ニオブ（Ｎｂ）
の中から選ばれた１の金属層またはこれを主成分とする
合金層を介在させたことを特徴とする。The present invention has a structure in which a semiconductor element chip is bonded and fixed to a mounting base using a brazing material made of a tin-copper alloy, and titanium (Ti), chromium (Cr), and zirconium are placed between the brazing material and the semiconductor element chip. (Zr), niobium (Nb)
It is characterized by interposing a layer of one metal selected from the following or an alloy layer containing this metal as a main component.

ちなみに、７ｉ、ｚｒへのＣｕの拡散係数（４００℃）
は１Ｑ−１３程度であり、ＮｂへのＣｕの拡散係数（４
００℃）は１Ｏ−ｚｓ程度であって非常に小さい。また
ＣｒへのＣｕの拡散係数はＮｉへのそれより大きいが、
現実に拡散距離を測定した結果ではＮｉにおけるより小
さいものとなっている。By the way, the diffusion coefficient of Cu to 7i, zr (400℃)
is about 1Q-13, and the diffusion coefficient of Cu into Nb (4
00°C) is about 1O-zs, which is very small. Also, the diffusion coefficient of Cu into Cr is larger than that into Ni,
The results of actually measuring the diffusion distance show that it is smaller than that of Ni.

また本発明は、半導体素子チップ底面に第１層金属層と
してＶＷ４またはＶ合金層が被着されている場合は勿論
、これがない場合にも有効である。Furthermore, the present invention is effective not only when a VW4 or V alloy layer is deposited as a first metal layer on the bottom surface of a semiconductor element chip, but also when this layer is not provided.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、Ｔｉなどが従来のＮｉに比べてＣｕ拡
散に対する障壁として有効に機能する結果、素子特性を
劣化させることがなくなる。また加速試験や熱！！ｉ撃
試験等においても接触不良やはがれが生しにくく、信頼
性の高い半導体装置が得られる。ろう材が安価であるた
め、半導体装置を低コストで製造することができる。According to the present invention, Ti and the like function more effectively as a barrier to Cu diffusion than conventional Ni, and as a result, device characteristics are not degraded. Also accelerated testing and heat! ! A highly reliable semiconductor device that is less likely to cause contact failure or peeling even in an i-impact test or the like can be obtained. Since the brazing filler metal is inexpensive, semiconductor devices can be manufactured at low cost.

〔発明の実ｍ例〕[Example of invention]

以下本発明の実施例を図面を参照して説明する。 Embodiments of the present invention will be described below with reference to the drawings.

（実施例１） 第１図に示すように、複数個のｎｏｎトランジスタ１１
ａ、ｌｌｂ、・・・が形成された３ｉ基板１１の底面に
、Ｖｌｌ　２．　Ｔ　ｉ　ＩＦ！１３．５ｎ−Ｃｕ（２
６ｗｔ％）層１４を順次蒸着した。７層１２は６９０人
、Ｔｔｌ！１３は２７００人であり、５ｎ−Ｃｕ唐１４
は１．５μｍとした。また図では省略したが、ろう材で
ある５ｎ−ＣｕＪｌｌ　４の表面に酸化防止のためにＡ
ｕ層を２０００人蒸着した。(Example 1) As shown in FIG. 1, a plurality of non-transistors 11
On the bottom surface of the 3i substrate 11 on which Vll2. T i IF! 13.5n-Cu(2
6 wt%) layer 14 was deposited sequentially. 7th layer 12 has 690 people, Ttl! 13 is 2700 people, 5n-Cu Tang 14
was set to 1.5 μm. Although not shown in the figure, the surface of the brazing material 5n-CuJll 4 has A
2000 people deposited the u layer.

この後ダイヤモンド・スクライブ法により個々のトラン
ジスタ・チップに分割した。Thereafter, it was divided into individual transistor chips using the diamond scribing method.

そしてトランジスタ・チップを第２図に示すように、Ｃ
ｕリードフレーム１５上に４５０℃の温度で接合した。Then, as shown in Figure 2, the transistor chip is
It was bonded onto the u-lead frame 15 at a temperature of 450°C.

５ｎ−Ｃｕｌ１１４が加熱、押圧により融解して冷却後
は再び固化することにより、チップはリードフレーム１
５との間で強固に固着される。5n-Cul114 is melted by heating and pressing and solidified again after cooling, so that the chip is attached to the lead frame 1.
5 and is firmly fixed.

（実施例２） 実施例１のＴｉＦｌに代わり、２５００人のＣｒ暦を形
成した。ろう材は、Ｓｎ−Ｃｕ（３０ｗｔ％）とした。(Example 2) Instead of TiFl in Example 1, Cr calendars for 2500 people were formed. The brazing material was Sn-Cu (30 wt%).

その他実施例１と同様の条件でトランジスタ・チップを
リードフレーム上に接合した。Otherwise, the transistor chip was bonded onto the lead frame under the same conditions as in Example 1.

以上の二つの実施例につき、Ｖｃ　Ｅ　（ｓａｔ　）試
験結果を第３図に示す。測定条件は、Ｉｃ＝１００ｍＡ
、Ｉｅ＝１０ｍＡである。第３図には比較例として、ｖ
Ｗｌと３ｎ−ｃｕｓの間ニＮ　ｉ　層ｔｒ　８２けた場
合のデータを併せて示した。図から明らかなように、比
較例のＶｅｘ（Ｓａｔ）が２７０ｍＶと要求水準１８０
ｍＶに対して著しく高いのに対し、実施例１．２ではい
ずれも要求水準を満足している。FIG. 3 shows the Vc E (sat) test results for the above two examples. The measurement conditions are Ic=100mA
, Ie=10mA. Figure 3 shows v as a comparative example.
Data for the case where there is a Ni layer tr of 82 digits between Wl and 3n-cus are also shown. As is clear from the figure, Vex (Sat) of the comparative example is 270 mV, which is the required level of 180 mV.
mV, whereas Examples 1 and 2 both satisfy the required level.

また実施例１．２のものは、３５０℃、３ｓｅｃのハン
ダ耐熱試験において殆ど不良の発生が見られず、熱衝撃
に対して十分な耐性を有するものであった。さらに、２
気圧の下で約３００時間のプレッシャー・クツカー・テ
スト（ＰＣＴ）を行なったところ電気的特性の劣化は全
く現われず、チップの剥離も生じなかった。Further, in Example 1.2, almost no defects were observed in the solder heat resistance test at 350° C. for 3 seconds, and it had sufficient resistance to thermal shock. Furthermore, 2
When a pressure test (PCT) was carried out for about 300 hours under atmospheric pressure, no deterioration of the electrical characteristics appeared at all, and no peeling of the chip occurred.

従ってこれらの実施例によれば、ろう材が安価であるこ
とと歩留り向上の効果が相まつ℃半導体装置の大幅な低
コスト化が図られる。Therefore, according to these embodiments, the low cost of the brazing material and the effect of improving yield can be achieved, resulting in a significant cost reduction of the °C semiconductor device.

具体的なデータは示さないが、Ｔｉ、Ｃｒの代わりにＺ
ｒ、Ｎｂを用いた場合、またこれらを主成分とする合金
を用いた場合にも同様の効果が得られることが確認され
ている。Although specific data is not shown, Z instead of Ti and Cr
It has been confirmed that similar effects can be obtained when r and Nb are used, or when an alloy containing these as main components is used.

またろう材としての５ｎ−ｃｕＷ４は、３ｎが３８〜９
２．４ｗｔ％の範囲で適宜選択することができる。In addition, 5n-cuW4 as a brazing material has 3n of 38 to 9
It can be appropriately selected within the range of 2.4 wt%.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の実施例におけるＳｉ基板のろう層形成
の状態を示す図、第２図は同じく素子チップをリードフ
レームに接合した状態を示す図、第３図は本発明の実施
例によるトランジスタの特性を従来例と比較して示す図
、第４図はリードフレームに半導体素子チップを接合し
た状態の一般的な構造を示す図である。FIG. 1 is a diagram showing a state in which a solder layer is formed on a Si substrate according to an embodiment of the present invention, FIG. 2 is a diagram showing a state in which an element chip is similarly bonded to a lead frame, and FIG. 3 is a diagram according to an embodiment of the present invention. FIG. 4 is a diagram showing the characteristics of a transistor in comparison with a conventional example. FIG. 4 is a diagram showing a general structure in which a semiconductor element chip is bonded to a lead frame.

Claims (3)

【特許請求の範囲】[Claims] （１）錫・銅合金からなるろう材により半導体素子チッ
プを配設台に固定してなる半導体装置において、前記ろ
う材と半導体素子チップとの間に、チタニウム、クロム
、ジルコニウム、ニオブの中から選ばれた１の金属層ま
たはこれを主成分とする合金層を介在させたことを特徴
とする半導体装置。(1) In a semiconductor device in which a semiconductor element chip is fixed to a mounting base by a brazing material made of a tin-copper alloy, a material selected from among titanium, chromium, zirconium, and niobium is used between the brazing material and the semiconductor element chip. A semiconductor device characterized by interposing a selected metal layer or an alloy layer containing the selected metal as a main component. （２）半導体素子チップは底面にバナジウムまたはバナ
ジウム合金が被着されている特許請求の範囲第１項記載
の半導体装置。(2) The semiconductor device according to claim 1, wherein the semiconductor element chip has vanadium or a vanadium alloy deposited on the bottom surface. （３）配設台はリードフレームである特許請求の範囲第
１項記載の半導体装置。(3) The semiconductor device according to claim 1, wherein the mounting base is a lead frame.
JP59276077A 1984-12-28 1984-12-28 Semiconductor device Pending JPS61156824A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP59276077A JPS61156824A (en) 1984-12-28 1984-12-28 Semiconductor device
US06/804,617 US4954870A (en) 1984-12-28 1985-12-05 Semiconductor device
DE8585309170T DE3581905D1 (en) 1984-12-28 1985-12-16 SEMICONDUCTOR ARRANGEMENT WHERE A SEMICONDUCTOR CHIP IS FIXED ON A BASE.
EP85309170A EP0186411B1 (en) 1984-12-28 1985-12-16 Semiconductor device in which a semiconductor chip is fixed to a base
KR1019850009521A KR900008971B1 (en) 1984-12-28 1985-12-18 Semiconductor device
CN85109419A CN85109419B (en) 1984-12-28 1985-12-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59276077A JPS61156824A (en) 1984-12-28 1984-12-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS61156824A true JPS61156824A (en) 1986-07-16

Family

ID=17564478

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59276077A Pending JPS61156824A (en) 1984-12-28 1984-12-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61156824A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01318236A (en) * 1988-06-17 1989-12-22 Sanyo Electric Co Ltd Semiconductor device and manufacture thereof
JP2008041707A (en) * 2006-08-01 2008-02-21 Nissan Motor Co Ltd Semiconductor device and manufacturing method therefor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01318236A (en) * 1988-06-17 1989-12-22 Sanyo Electric Co Ltd Semiconductor device and manufacture thereof
JP2008041707A (en) * 2006-08-01 2008-02-21 Nissan Motor Co Ltd Semiconductor device and manufacturing method therefor

Similar Documents

Publication Publication Date Title
US4908685A (en) Magnetoelectric transducer
KR900008971B1 (en) Semiconductor device
US4042951A (en) Gold-germanium alloy contacts for a semiconductor device
EP0460785B1 (en) Semiconductor device having a heat sink
EP0880801B1 (en) DIE ATTACHED SiC AND DIE ATTACH PROCEDURE FOR SiC
JPH06501816A (en) Synthetic hybrid semiconductor structures
GB2138633A (en) Bonding semiconductor chips to a lead frame
JPS61156824A (en) Semiconductor device
JPS59159583A (en) Semiconductor light emitting device
JPS61294838A (en) Electrode and wiring of semiconductor device
JPS592175B2 (en) semiconductor equipment
JPH03252155A (en) Semiconductor package
JPS62163335A (en) Semiconductor device
CA1153128A (en) Electrical circuit assemblies
JPS61156823A (en) Semiconductor device
JPS61156825A (en) Semiconductor device
JPS60110127A (en) Semiconductor device having laminated metal electrode
JPH0864799A (en) Semiconductor chip, semiconductor device using it and manufacture thereof
JPS6129142B2 (en)
US3401316A (en) Semiconductor device utilizing an aual2 layer as a diffusion barrier that prevents "purple plague"
JPS6057221B2 (en) semiconductor equipment
JPS592174B2 (en) semiconductor equipment
JPS6057219B2 (en) semiconductor equipment
JPS63289956A (en) Manufacture of schottky barrier diode
JPS60143636A (en) Electronic component parts