JPS62163335A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the diffusion of Cu into an element chip, and to improve electrical characteristics while obviating the peeling of a junction section by fixing the semiconductor chip to a disposal base by an alloy solder material, which is composed of tin, copper and zinc and the contents of tin and zinc therein are specified. CONSTITUTION:A semiconductor chip 1 is disposed and fixed 5 to a disposal base by a solder material consisting of an Sn-Cu-Zn alloy through a first metallic layer 2, which is applied on the base of the chip 1 and made up of one kind of Ti, Cr, Zn, Nb, V or an alloy mainly comprising the element, and a second metallic layer 3 composed of either of Ni or Co or an alloy mainly comprising the element. The thickness of said first metallic layer is made thicker than that of the second metallic layer, and the contents of Sn and Zn as the solder material are brought to 0.33-6.52 and 0-0.53 at atomicity ratios to Cu.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and in particular, the present invention relates to a semiconductor device in which an element chip is 8n-C.
The present invention relates to a semiconductor device characterized in that it is fixed to a mounting base such as a lead frame using a brazing material made of a u-Zn alloy.

[Technical background of the invention and its problems]

Conventionally, when placing a semiconductor element chip on a lead frame etc., TI, Cr, Zr was applied to the bottom of the element chip in advance.
.

A metal layer made of one of Nb and V or an alloy containing at least one of these as a main component is entirely deposited, and the layer and the lead frame are bonded to the gold using a brazing filler metal made of an fSn-Cu alloy. structure is known.

Although there are almost no problems with such a four-structure semiconductor device during normal operation, it has been confirmed that defects such as peeling of the bonded portion occur during reliability tests under strict conditions. In 5n-Cu alloy bonding, this is due to the heating during bonding.
Diffusion movement of u occurs, and ε phase intermetallic compound Cu3s n
However, as shown in FIG. 2, this Cu3an exhibits high electrical resistance and low thermal conductivity. Especially C.L.L.
Bonded to the lead frame 77: Pigeon house I (tl Due to Cu diffusion from the lead frame, the entire 5n-Cu wax layer becomes Cu3Sn. Therefore, b) Reliability tests such as bathing tests etc. , the joint temperature rises markedly and is likely to lead to delamination. In the case of a Cu J7 lead frame, a 1 temperature rise causes a vicious cycle in which C and U diffusion progresses and the thermal opening further increases. It peels off near the boundary with the material. For this reason, 5n-Cu alloy soldered semiconductor devices have been used only in devices with relatively low reliability requirements.

[Purpose of the invention]

The present invention has been made in view of the above points, and its entire purpose is to provide a highly reliable semiconductor device.

[Summary of the invention]

In the present invention, a semiconductor chip has a first metal layer made of one of T r t Cr t Zr + Nb, V, or an alloy containing these as a main component, and Ni.

A second gold layer made of an alloy whose main component is Co, and a brazing filler metal made of a 5n-Cu-Zn alloy are placed and fixed on the placement table Q. .

In addition, the base metal layer of the first layer is thicker than that of the second gold 55 scrap, and the brazing filler metal Sn (Zn content is 0.0. 33-6.52 and 0
~0.53.

〔Effect of the invention〕

According to the present invention, it is possible to obtain a base conductor device with excellent reliability and a connection that reduces the reduction in air-fuel conductivity due to the formation of C13Sn with Zn. Between the fc and the element chip, the first paper, t
The effect of reducing Δti is the same as the conventional example,
By preventing Cu in 8n-Cu-Zn from diffusing into the element chip shell and improving electrical characteristics, the second metal layer also has the effect of alleviating stress caused by thermal shock, which is the same as in the conventional example. It is.

[Embodiments of the invention]

An actual game example of the present invention will be explained below with reference to all the drawings.

FIG. 1 shows the structure of one embodiment. In the figure, 1 is a semiconductor element chip, 2 is T' i , Cr, and Zr.

The metal layer of the ear 1 is made of one of Nb and V or an alloy containing these as a main component, and its thickness is 200 OA or more. 3 is a second gold 4 layer made of either Ni or Co or an alloy mainly composed of these, and its thickness is 1500A or less.

4 is a 5n-Cu-Zn alloy metal as a brazing material, and its thickness is about 2 μm. 5 is a mounting base such as a Cu IJ-de frame.

This :gg structure is manufactured as follows. First, a first
1/2 sip of metal to a thickness of 200 OA or more '4. Then, on the surface of the first gold layer 2, a second gold layer of 3kl 50
It is coated to a thickness of 0A or less, and the surface is coated with 5n-Cu-
A Zn alloy layer 4 is deposited by vapor deposition. The wafer having three metal layers formed thereon is divided into each element chip 1. Then, by heating the mounting table 5 to 415° C. or higher and pressing the entire 5n-Cu-Zn alloy layer 4 of the element chip 1 onto the mounting table 5, the 5n-Cu-Zn alloy is melted, and after cooling, By solidifying again, the element chip 1 and the mounting base 5 are fixed to each other.

Specifically, an npn small signal transistor (
The results of reliability evaluation when the present invention was implemented for Tφ-92) are shown in the table below together with comparative examples.

Example 1 in the table shows that the V layer is 250OA as the first metal layer.
, N i a Th1OOOA as the second gold layer.

Contains 50at% of Cu and 5at% of Zn, and the remaining Sn is 5n-
A 2 μm thick Cu-ZnIAt film was formed and bonded to the mounting table. In Example 2, the first gold If4 layer is a Ti layer totaling 300OA2g2(7) and the Ni layer t=lso as a total of 4 layers.
oX.

Contains Cu45at% and Zn2Qat% and the remaining Sn is 5n
-Cu-Zn layer was formed to a thickness of 1.5 μm and bonded to the mounting table.

In addition, in the ratio example 1 of the table, ■N is 270 as the 10th gold layer.
OA 2nd gold, -1500N i 11N as 4th layer
The ASn--Cu layer was formed to have a total thickness of 2 μm and was bonded to the mounting table. Comparative example 2 is the first gold! -4) Ti layer f: 300OA as $, Ni layer f: 150 as 20th gold layer
0 A, S n -Cu N k 1.5 it
m is formed and joined to the installation stand.

As is clear from the above table, both Examples 1 and 2 failed after 168 hours of the current test (B'l") (here, VoX
It was confirmed that there were almost no occurrences of (defective sat) values, and that the method was superior in terms of authenticity compared to conventional methods.

In addition to these Examples, in Example 1 Cu2
5at%, Znlat% remainder S n O5n-Cu-Z
A similar test was conducted for an example in which all n alloy layers were used*? The result was that the number of defects was 1/20.

As described above, according to the present invention, a highly economical semiconductor device can be obtained by using 5n-Cu-Zn solder metal.

[Brief explanation of drawings]

Fig. 1 shows a 7sF'r state in which a semiconductor element is bonded to a mounting base in an embodiment of the present invention, and Fig. 2 shows changes in electrical resistance of a 5n-Cu alloy depending on the composition, and shows poor reliability in the conventional example. Here is a diagram to explain. 1...Semiconductor element chip, 2...5f↓1 metal'
n13... Second metal layer, 4... S n-Cu layer (brazing material), 5... Installation stand.

Claims (3)

[Claims] (1) Contains tin, copper, and zinc, and the contents of tin and zinc are atomic ratios of 0.33 to 6.52 and 0 to 6.52, respectively.
1. A semiconductor device, characterized in that a semiconductor element chip is fixed to a mounting table using an alloy brazing material having a brazing strength of 0.53. (2) T between Sn-Cu-Zn and semiconductor element chip
A first metal layer made of a metal selected from i, Cr, V, Zr, and Nb or an alloy containing at least one of these as a main component is interposed with a thickness of 2000 Å to 3 μm. A semiconductor device according to claim 1. (3) A second metal layer made of a metal selected from Ni or Co, or an alloy containing at least one of these as a main component, is placed between the first metal layer and the brazing material layer. 2. The semiconductor device according to claim 1, wherein the semiconductor device is thinner than the layer.