CN100452372C - Semiconductor device having tin-based solder layer and method for manufacturing the same - Google Patents
Semiconductor device having tin-based solder layer and method for manufacturing the same Download PDFInfo
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- CN100452372C CN100452372C CNB2005100999098A CN200510099909A CN100452372C CN 100452372 C CN100452372 C CN 100452372C CN B2005100999098 A CNB2005100999098 A CN B2005100999098A CN 200510099909 A CN200510099909 A CN 200510099909A CN 100452372 C CN100452372 C CN 100452372C
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04026—Bonding areas specifically adapted for layer connectors
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- H01L2924/01042—Molybdenum [Mo]
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- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Abstract
A semiconductor device includes: a semiconductor substrate; a base member; a tin-based solder layer; a first metal layer; and a first alloy layer. The semiconductor substrate is bonded to the base member through the first metal layer, the first alloy layer and the tin-based solder layer in this order. The first alloy layer is made of a first metal in the first metal layer and tin in the tin-based solder layer. The first metal layer is made of at least one of material selected from the group consisting of titanium, aluminum, iron, molybdenum, chromium, vanadium and iron-nickel-chromium alloy.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof with tin-based solder layer.
Background technology
Routinely, use Lead-tin alloy (Pb-Sn alloy) scolder with Semiconductor substrate as IC chip join with semiconductor device on substrate parts such as heat abstractor and lead frame.Yet, consider environmental protection such as safety and low infringement, the scolder that needs to use Pb-free solder or contain low Pb.One of them is tin solder for a Pb-free solder.
Japanese Patent Application Publication No.2003-347487 discloses with the dorsal part of tin solder with Semiconductor substrate and has joined on the substrate parts.Substrate comprises backside electrode.Electrode is made up of titanium layer, nickel dam and gold or silver layer, and they are stacked on the substrate in order.Substrate parts is a heat radiation part.With tin solder substrate is assemblied on the heat radiation part.Tin solder is made by gold and ashbury metal, so that scolder provides low-melting scolder.
The semiconductor device that following manufacturing is above.At first, the dorsal part of polishing and cleaning substrate.Then, on the polished surface of substrate, form backside electrode.Then, tin solder is clipped between heat radiation member and the backside electrode.Then, tin solder is heated to the solidus temperature of scolder.Thereby, make solder reflow, so that substrate is welded on the heat radiation member.
In this structure of backside electrode, the Ti layer provides the viscosity and the ohmic contact of the Semiconductor substrate of being made by silicon.By making the Ni layer in the scolder become alloy, make the Ni layer that the joint character of scolder is provided with tin.Thereby substrate and substrate parts and scolder are electrically, thermally and mechanically engage.
At this, on the Ti layer, form passivating film easily, as oxide-film, and be difficult to remove.In atmosphere, form passivating film with ordinary temp and usual pressure.Therefore, be difficult to the Ti layer is directly joined on the scolder.Therefore, it is enough thick to form the Ni layer on the Ti layer.And, need control welding condition with pinpoint accuracy.Therefore, manufacturing cost becomes higher.
Summary of the invention
In view of the above problems, the object of the present invention is to provide a kind of semiconductor device with tin-based solder layer.Another object of the present invention is to provide a kind of manufacture method with semiconductor device of tin-based solder layer.
A kind of semiconductor device comprises: Semiconductor substrate; Substrate parts; Tin-based solder layer; The first metal layer; With first alloy-layer.Through the first metal layer, first alloy-layer and tin-based solder layer, Semiconductor substrate is joined on the substrate parts successively.First alloy-layer is made by first metal in the first metal layer and the tin in the tin-based solder layer.The first metal layer is made by at least a material that is selected from titanium, aluminium, iron, molybdenum, chromium, vanadium and the Fe-Ni-Cr-alloy.
In this device, by utilizing the metal level of tin-based solder layer and minimum number, the dorsal part of substrate is joined on the substrate parts.Thus, manufacturing process becomes simply, and the manufacturing cost of device becomes lower.
And, a kind of manufacture method of semiconductor device is provided.This device comprises Semiconductor substrate and joins substrate parts on the substrate to tin-based solder layer.This method comprises the steps: to form the first metal layer on substrate; On the first metal layer, form second metal level; On substrate parts, pile up substrate via solder layer, wherein solder layer is arranged between the substrate parts and second metal level; And heated substrate and substrate parts, so that second metal level is diffused in the solder layer, and the first metal layer and solder layer are reacted to form first alloy-layer.First alloy-layer is made by first metal in the first metal layer and the tin in the solder layer.First alloy-layer is arranged between the first metal layer and the solder layer.The first metal layer is made by at least a material that is selected from titanium, aluminium, iron, molybdenum, chromium, vanadium and the Fe-Ni-Cr-alloy.Before heating steps, second metal level has the original depth in the scope between 50nm and 750nm.
By utilizing the metal level of tin-based solder layer and minimum number, the dorsal part of substrate is joined on the substrate parts.Thus, manufacturing process becomes simply, and the manufacturing cost of device becomes lower.
Preferably, this method further comprises the steps: the heated substrate and first and second metal levels, so that form the intermediate alloy layer between first and second metal levels.The intermediate alloy layer is made by first metal in the first metal layer and second metal in second metal level.In the heating steps of substrate and substrate parts, intermediate alloy layer, the first metal layer and solder layer react to form second alloy-layer, so that first alloy-layer becomes second alloy-layer.Second alloy-layer is made by second metal in second metal level, first metal in the first metal layer and the tin in the solder layer.Second alloy-layer is arranged between the first metal layer and the solder layer.
Description of drawings
The following detailed description of carrying out with reference to the accompanying drawings, above and other purpose of the present invention, feature and advantage will become more apparent.In the drawings:
Figure 1A and 1B are the schematic sections that illustrates according to the manufacture method of the semiconductor device of first embodiment of the invention;
Fig. 2 is the figure that illustrates according to the percentage of defects of the device with different-thickness Ni film of first embodiment;
Fig. 3 is the figure that illustrates according to the tensile strength of the device with different-thickness Ni film of first embodiment;
Fig. 4 is the figure that illustrates according to the tensile strength of the device of the Au film with different-thickness of first embodiment;
Fig. 5 is the depth profile according to the elementary analysis of first embodiment;
Fig. 6 A to 6C is the schematic section that illustrates according to the manufacture method of the semiconductor device of second embodiment of the invention;
Fig. 7 A is the time variation diagram that is illustrated in according to the Ti film thickness under durability test in the device of first embodiment, and Fig. 7 B is the time variation diagram that illustrates according to the Ti film thickness under durability test in the device of second embodiment;
Fig. 8 A and 8B are the schematic sections that illustrates according to the manufacture method of the semiconductor device of first embodiment variant;
Fig. 9 A to 9C is the schematic section that illustrates according to the manufacture method of the semiconductor device of second embodiment variant; And
Figure 10 illustrates according to first and second embodiment variant at the silicon substrate of P conduction type and the figure of the contact resistance between Al film or the Ti film.
Embodiment
(first embodiment)
At first, on the front side of substrate 1, form electronic unit.On the dorsal part of substrate 1, form the first metal layer M and the second metal level N successively.Thus, formed semiconductor chip 10.Then, the solder layer S by between the second metal level N that is clipped in substrate parts 2 and chip 10 is assemblied in chip 10 on the substrate parts 2.Thus, prepared the laminated construction that constitutes chip 10 and substrate parts 2.Heat this laminated construction, so that second metal level is diffused among the solder layer S.And the first metal layer M and solder layer S directly react, and the result has formed alloy-layer T1 between the first metal layer M and solder layer S.Alloy-layer T1 is made by the alloy of the first metal layer M and solder layer S.Particularly, alloy-layer T1 is made by first metal among the first metal layer M and the tin among the solder layer S.After the welding, device 100 is made up of substrate 1, the first metal layer M, alloy-layer T1, solder layer S and substrate parts 2.At this, alloy-layer T1 is as the knitting layer between chip 10 and the substrate parts 2.Though the first metal layer M is formed directly on the substrate 1, can between substrate 1 and the first metal layer M, form another metal level or insulating barrier.
In device 100,, the dorsal part of substrate 1 is joined on the substrate parts 2 by metal level and the tin-based solder layer S that utilizes minimum number.Therefore, the manufacturing process of device 100 is simple, and the low cost of manufacture of device 100.
First metal among the first metal layer M for example is that (that is, Ti), (that is, Al), (that is, Fe), (that is, Mo), (that is, Cr), vanadium (that is, V) or Fe-Ni-Cr-alloy (that is Fe-Ni-Cr alloy) for chromium for molybdenum for iron for aluminium for titanium.First metal have with silicon substrate good engage character and good ohmic contact.And first metal and tin form alloy in solder layer S.Preferred first metal is made by Ti.Ti is as the conventional material of the metallization material of silicon in Semiconductor substrate.Therefore, Ti and silicon substrate have good character and the good ohmic contact of engaging.Yet, on the Ti film, form passivating film easily, as oxide-film.Thereby, usually, be difficult to the Ti layer is directly joined on the solder layer.Yet, in above device 100, on the first metal layer M, form the second metal level N, so that the second metal level N is as the sacrifice layer of welding.Thereby, between the first metal layer M and solder layer S, formed alloy-layer T1.Alloy-layer T1 has enough strong joint character.
The thickness of alloy-layer T1 preferably equals 3nm or thicker than 3nm.More preferably, the thickness of alloy-layer T1 equals 10nm or thicker than 10nm.When the average thickness of alloy-layer T1 is equal to or greater than 10nm, and when at the interface the minimum thickness of alloy-layer T1 is equal to or greater than 3nm between the first metal layer M and solder layer S, obtained enough strong joint character.And, when the thickness of alloy-layer T1 during greater than 10nm, the situation that has obtained to equal 10nm with average thickness much at one engage character.
The second metal level N is a thin layer, is used to protect the surface of the first metal layer M so that do not form passivating film on the surface of the first metal layer M.Heat treatment by welding can be diffused among the solder layer S the second metal level N, so that the second metal level N is disappeared.Thus, can easily control the thickness of the second metal level N.And, the welding condition of control device 100 easily.Thus, the manufacturing cost of device 100 becomes relatively low.
The thickness of the second metal level N is preferably in the scope between 50nm and 750nm, and is as described below.When the thickness of the second metal level N during less than 50nm, the second metal level N can not protect the surface of not oxidation of the first metal layer M the first metal layer M fully, that is, avoid forming passivating film on the surface of the first metal layer M.Therefore, in this case, the scolder wettability of solder layer S during heating treatment becomes littler, as a result the bond strength step-down between substrate 1 and the substrate parts 2.When the thickness of the second metal level N during greater than 50nm, the bond strength between substrate 1 and the substrate parts 2 becomes strong and constant.When the thickness of the second metal level N during, after welding, retained the second metal level N greater than 750nm.Therefore, unnecessary second metal level can increase the manufacturing cost of device 100.
Preferably (that is, PVD) method as vacuum deposition method and sputtering method, forms the first and second metal level M, N in proper order in vacuum chamber by utilizing physical vapor deposition.And preferably the vacuum degree before deposition is equal to or less than 5 * 10
-4Pa.This is because prevent that the first metal layer M's is surperficial oxidized.
Second metal among the second metal level N can be made by any metal.Preferred second metal is that (that is, Ni), (that is, Cu), (that is, Ag), (that is, Au), (that is, Pt), (that is (that is, Ag-Pd) alloy or palladium be (that is, Pd), Ag-Pt) to close gold, silver-palladium for silver-platinum for platinum for gold for silver for copper for nickel.More preferably, second metal is nickel or gold.These two kinds of metals can form alloy with first metal or the tin among the solder layer S among the first metal layer M.The second metal level N can be made up of multilayer film, and it is made by above metal.In Technology for Heating Processing, promptly in welding procedure, second metal can be diffused among the solder layer S.And second metal can be contained among the alloy-layer T1, and alloy-layer becomes the second alloy-layer T2 as a result, shown in Fig. 6 A and 6B.
Tin-based solder layer S can be made by Pb-free solder, and it does not comprise lead (that is, Pb).Therefore, can make device 100 harmless and safely, so that obtain environmental protection.The mass content of tin is equal to or greater than 95wt.% among the preferred solder layer S.(that is, Sn), (that is, Sn-Cu) alloy, tin-silver-copper be (promptly for tin-copper by tin for preferred solder layer S, Sn-Ag-Cu) alloy, tin-copper-nickel (that is, Sn-Cu-Ni) alloy, tin-antimony (that is, Sn-Sb) alloy, tin-indium be (promptly, Sn-In) (that is, Sn-Zn) alloy is made for alloy or tin-zinc.More preferably, solder layer S is made by pure Sn, Sn-(0.7wt.%Cu) alloy, Sn-(3.5wt.%Ag) alloy, Sn-(1wt.% to 3.9wt.%Ag)-(0.3wt.% to 1.5wt.%Cu) alloy or Sn-(0.7wt.%Cu)-(0.06wt.%Ni) alloy.Preferably, solder layer S can comprise additive, as phosphorus (that is, P) and germanium (that is, Ge).
Next, for example, following manufacturing device 100.
At first, on the dorsal part of substrate 1, form Ti film, so that on substrate 1, form the first metal layer M with 250nm thickness.Then, on the first metal layer M, form the second metal level N that forms by Ni film with 50nm and 1000nm ranges of thicknesses and Au film with 50nm thickness.At this, the second metal level N is made by multilayer film.Next, on substrate parts 2, form the solder layer S that makes by (99.24wt.%Sn)-(0.7wt.%Cu)-(0.06wt.%Ni) alloy.Substrate parts 2 is made of metal.The semiconductor chip 10 that will comprise the substrate 1 with the first and second metal level M, N via solder layer S is assemblied on the substrate parts 2.Then, assembling chip 10 and substrate parts 2 in the hydrogen reducing atmosphere stove.In stove, chip 10 and substrate parts 2 are heated to 270 ℃, it is than the solidus temperature height of solder layer S.At this, solidus temperature is about 220 ℃.Thus, in 20 seconds, make chip 10 and substrate parts 2 be heated to 270 ℃ peak temperature, so that solder layer S is refluxed.In this Technology for Heating Processing, that is, in this welding procedure, chip 10 is welded on the substrate parts 2.
After welding, study the cross section of device 100.As a result, when the thickness of Ni film was equal to or less than 750nm, the second metal level N that is made up of Ni film and Au film had been diffused among the solder layer S, made to have formed the first alloy-layer T1 that is made up of Ti and Sn.Yet when the thickness of Ni film during greater than 750nm, the Ni film among the second metal level N remains.This unreacted Ni film is to not contribution of the joint between chip 10 and the substrate parts 2.Therefore, in order to reduce the manufacturing cost of device 100, the thickness of preferred Ni film is equal to or less than 750nm.
Fig. 2 shows the percentage of defects of the device 100 of the Ni film with different-thickness.Caused the defective of device 100 by the solder of defective.Fig. 3 shows the tensile strength of the device 100 of the Ni film with different-thickness.At this, ten samples of the device 100 in the Ni film of having studied at every kind of thickness.
Shown in Fig. 2 and 3, when the thickness of Ni film was 50nm, 100% the solder of defective occurred.Therefore, the bond strength between substrate 1 and the substrate parts 2 is very weak.This is the very thin thickness because of the Ni film, so that the second metal level N can not protect the first metal layer M to avoid oxidized.In this case, the Ti film of the first metal layer M is surperficial oxidized.Therefore, need the Ni film to become thicker more oxidized to prevent the Ti film than 50nm.When the thickness of Ni film during, obtained enough strong bond strength greater than 50nm.
Fig. 4 shows the tensile strength of the device 100 of the Au film with different-thickness.In this case, the second metal level N of device 100 only is made up of the Au film.Therefore, in the second metal level N, do not form the Ni film.At this, ten samples of the device 100 in the Au film of having studied at every kind of thickness.When the thickness of Au film was 50nm, the solder of defective had appearred.Yet,, obtained enough strong bond strength when the thickness of Au film during greater than 50nm.
Fig. 5 shows the results of elemental analyses in the knitting layer cross section in device 100.In this case, device 100 has by molybdenum (that is the first metal layer M that, Mo) makes and the second metal level N that is made by Ni.In the enterprising row element analysis of thickness direction.Thus, Fig. 5 shows the depth profile of elementary analysis.As shown in Figure 5, the Ni among the second metal level N has been diffused among the solder layer S, and the result has formed the first alloy-layer T1 by the Mo-Sn alloy composition.
(second embodiment)
Following manufacturing device 101.At first, on the dorsal part of substrate 1, form the first metal layer M and the second metal level N successively, so that preparation semiconductor chip 10.At first heating chip 10, so that form intermediate alloy layer O.Intermediate alloy layer O is made up of first metal and second metal alloy.Intermediate alloy layer O is arranged between the first and second metal level M, the N.After this first heat treatment, chip 10 is assemblied on the substrate parts 2 via solder layer S.Then, post bake chip 10 and substrate parts 2 are so that be welded on chip 10 on the substrate parts 2.Particularly, the second metal level N is diffused among the solder layer S, and, intermediate alloy layer O and solder layer S reaction, the result has formed the second alloy-layer T2.The second alloy-layer T2 is made up of second metal among first metal among the first metal layer M, the second metal level N and the Sn among the solder layer S.After second heat treatment, that is, after welding, device 101 comprises substrate parts 2, solder layer S, the second alloy-layer T2, the first metal layer M and substrate 1.At this, the second alloy-layer T2 is as the knitting layer between chip 10 and the substrate parts 2.
In device 101, metal level by utilizing minimum number and tin-based solder layer S join the dorsal part of substrate 1 on the substrate parts 2 to.Therefore, the manufacturing process of device 101 is simple, and the low cost of manufacture of device 101.
Preferably, second metal among the second metal level N is Ni, Cu, Ag, Au, Pt, Ag-Pt alloy, Ag-Pd alloy or Pd.More preferably, second metal is Ni or Au.Under the situation that the first metal layer is made by Ti, second metal can form alloy with Ti.
Next, for example, following manufacturing device 101.
At first, on the dorsal part of substrate 1, form by having the first metal layer M that the thick Ti film of 250nm is made.Then, on the first metal layer M, form the second metal level N that forms by Ni film with thickness in 50nm and the 600nm scope and Au film with 50nm thickness.Here, the second metal level N is made by multilayer film.Thus, prepared chip 10, then, in three minutes at 380 ℃ of heating chips.Then, the cross section of research chip 10.As a result, between the first metal layer M and the second metal level N, formed intermediate alloy layer O with 20nm thickness.
Then, on the substrate parts 2 that is made of metal, form the solder layer S that makes by (99.24wt.%Sn)-(0.7wt.%Cu)-(0.06wt.%Ni) alloy.Then, via solder layer S chip 10 is assemblied on the substrate parts 2.Then, assembling chip 10 and substrate parts 2 in the hydrogen reducing atmosphere stove.In stove, chip 10 and substrate parts 2 are heated to 270 ℃, it is than the solidus temperature height of solder layer S.At this, solidus temperature is about 220 ℃.Thus, in 20 seconds, make chip 10 and substrate parts 2 be heated to 270 ℃ peak temperature, so that solder layer S is refluxed.In this second Technology for Heating Processing, that is, in this welding procedure, chip 10 is welded on the substrate parts 2.After welding, formed the second alloy-layer T2.The second alloy-layer T2 is made by the Ti-Sn-Ni alloy.
Fig. 7 A shows under the device shown in Figure 1B 100 comprises situation by the first alloy-layer T1 of Ti-Sn alloy composition, and the time of the Ti film thickness of the first metal layer M changes.Fig. 7 B shows under device 101 shown in Fig. 6 C comprises situation by the second alloy-layer T2 of Ti-Sn-Ni alloy composition, and the time of the Ti film thickness of the first metal layer M changes.At this, in 0 hour, 1000 hours or 2000 hours, under 150 ℃, device 100,101 is carried out durability test.At this, do not refer in 0 hour device 100,101 is carried out durability test.In Fig. 7 A, line VIIA is illustrated in the device 100 that welding has the Ni film of 600nm original depth before, line VIIB is illustrated in the device 100 that welding has the Ni film of 200nm original depth before, and line VIIC is illustrated in the device 100 that welding has the Ni film of 50nm original depth before.In Fig. 7 B, line VIID is illustrated in the device 101 that welding has the Ni film of 600nm original depth before, line VIIE is illustrated in the device 101 that welding has the Ni film of 200nm original depth before, and line VIIF is illustrated in the device 101 that welding has the Ni film of 50nm original depth before.
Shown in Fig. 7 A and 7B, in device 101, to compare with device 100 with first alloy-layer T1 with second alloy-layer T2, the time of the thickness of Ti film changes relatively little.Therefore, in device 101, compare with device 100, at the high temperature durability test period, the Sn among Ti among the first metal layer M and the solder layer S reacts lentamente.
(modified example)
Substrate 1 can be made by any semi-conducting material.When substrate 1 is made by the Semiconductor substrate 1p of P conduction type, preferably between the first metal layer M and substrate 1p, form the 3rd metal level L, shown in Fig. 8 A to 9C.The 3rd metal level L is made by alumina-base material.Preferably, the 3rd metal level L by fine aluminium (that is, Al), aluminium-silicon (that is, Al-Si) alloy or aluminium-silicon-copper (that is, Al-Si-Cu) alloy is made.
Though in the hydrogen reducing atmosphere stove, chip 10 is joined on the substrate parts 2 by the solder reflow method, but can be by utilizing other welding method, as with the solder die bonding method of lead-in wire scolder with the air or the inert gas atmosphere circumfluence method of solder cream, chip 10 is joined on the substrate parts 2.
Though described the present invention with reference to the preferred embodiments of the present invention, it being understood that the present invention is not limited to preferred embodiment and structure.The present invention refers to and covers various modification and equivalent structure.In addition, it is preferred various combinations and structure, comprises other combination more, a still less or only simple components and structure also within the spirit and scope of the present invention.
Claims (26)
1. semiconductor device comprises:
Semiconductor substrate (1,1p);
Substrate parts (2);
Tin-based solder layer (S);
The first metal layer (M); With
First alloy-layer (T1), wherein
Successively through the first metal layer (M), first alloy-layer (T1) and tin-based solder layer (S), Semiconductor substrate (1,1p) is joined on the substrate parts (2);
First alloy-layer (T1) is made by the tin in first metal in the first metal layer (M) and the tin-based solder layer (S), and
The first metal layer (M) is made by a kind of material that is selected from titanium, aluminium, iron, molybdenum, chromium, vanadium and the Fe-Ni-Cr-alloy.
2. according to the device of claim 1, wherein
The first metal layer (M) is made of titanium.
3. according to the device of claim 1, wherein
First alloy-layer (T1) has the average thickness that is equal to or greater than 3nm.
4. according to the device of claim 3, wherein
First alloy-layer (T1) has the average thickness that is equal to or greater than 10nm.
5. according to any one device among the claim 1-4, wherein
First alloy-layer (T1) further comprises second metal.
6. according to the device of claim 5, wherein
Second metal is made by a kind of material that is selected from nickel, copper, silver, gold, platinum, silver-platinum alloy, silver-palladium alloy and the palladium.
7. according to the device of claim 6, wherein
Second metal is made by nickel or gold.
8. according to any one device among the claim 1-4, wherein
Tin-based solder layer (S) is made by lead-free solder.
9. device according to Claim 8, wherein
The mass content of tin is equal to or greater than 95wt.% in the tin-based solder layer (S).
10. device according to Claim 8, wherein
Tin-based solder layer (S) is made by a kind of material that is selected from tin, tin-copper alloy, tin-silver alloy, tin-silver-copper alloy, tin-copper-nickel alloy, tin-antimony alloy, Sn-In alloy and the tin-zinc alloy.
11. according to the device of claim 10, wherein
Tin-based solder layer (S) is made by being selected from pure tin, Sn-0.7wt.%Cu alloy, Sn-3.5wt.%Ag alloy, Sn-1wt.% to 3.9wt.%Ag-0.3wt.% to a kind of material in 1.5wt.%Cu alloy and the Sn-0.7wt.%Cu-0.06wt.%Ni alloy.
12., further comprise according to any one device among the claim 1-4:
Be arranged on the 3rd metal level (L) between substrate (1,1p) and the first metal layer (M), wherein
The 3rd metal level (L) is made by alumina-base material.
13. according to the device of claim 12, wherein
The 3rd metal level (L) is made by being selected from fine aluminium, aluminium-silicon alloys and the al-si-cu alloy a kind of material.
14. the manufacture method of a semiconductor device, this semiconductor device comprise Semiconductor substrate (1,1p) and join the substrate parts (2) of substrate (1,1p) to tin-based solder layer (S) that this method comprises the steps:
Go up at substrate (1,1p) and to form the first metal layer (M);
Go up formation second metal level (N) at the first metal layer (M);
On substrate parts (2), pile up substrate (1,1p) through solder layer (S), wherein solder layer (S) is arranged between substrate parts (2) and second metal level (N); And
Heated substrate (1,1p) and substrate parts (2), so that second metal level (N) is diffused in the solder layer (S), and the first metal layer (M) and solder layer (S) are reacted to form first alloy-layer (T1), wherein first alloy-layer (T1) is made by the tin in first metal in the first metal layer (M) and the solder layer (S), wherein
First alloy-layer (T1) is arranged between the first metal layer (M) and the solder layer (S),
The first metal layer (M) is made by a kind of material that is selected from titanium, aluminium, iron, molybdenum, chromium, vanadium and the Fe-Ni-Cr-alloy, and
Before heating steps, second metal level (N) has the original depth in the scope between 50nm and 750nm.
15. according to the method for claim 14, wherein
The first metal layer (M) is made of titanium.
16. according to the method for claim 14, wherein
Form first and second metal levels (M, N) by physical vapor deposition methods order in vacuum chamber.
17. according to the method for claim 16, wherein
Forming first and second metal levels (M, N) before, vacuum chamber has and is equal to or less than 5 * 10
-4The initial depression of Pa.
18., further comprise the steps: according to any one method among the claim 14-17
Heated substrate (1,1p) and first and second metal levels (M, N) are so that form intermediate alloy layer (O), wherein between first and second metal levels (M, N)
Intermediate alloy layer (O) is made by second metal in first metal in the first metal layer (M) and second metal level (N),
In the step of heated substrate (1,1p) and substrate parts (2), intermediate alloy layer (O), the first metal layer (M) and solder layer (S) react to form second alloy-layer (T2), so that first alloy-layer (T1) becomes second alloy-layer (T2), wherein second alloy-layer (T2) is made by first metal in second metal in second metal level (N), the first metal layer (M) and the tin in the solder layer (S), and
Second alloy-layer (T2) is arranged between the first metal layer (M) and the solder layer (S).
19. according to the method for claim 18, wherein
Second metal is made by a kind of material that is selected from nickel, copper, silver, gold, platinum, silver-platinum alloy, silver-palladium alloy and the palladium.
20. according to the method for claim 19, wherein
Second metal is made by nickel or gold.
21. according to any one method among the claim 14-17, wherein
Tin-based solder layer (S) is made by lead-free solder.
22. according to the method for claim 21, wherein
The mass content of tin is equal to or greater than 95wt.% in the tin-based solder layer (S).
23. according to the method for claim 21, wherein
Tin-based solder layer (S) is made by a kind of material that is selected from tin, tin-copper alloy, tin-silver alloy, tin-silver-copper alloy, tin-copper-nickel alloy, tin-antimony alloy, Sn-In alloy and the tin-zinc alloy.
24. according to the method for claim 23, wherein
Tin-based solder layer (S) is made by being selected from pure tin, Sn-0.7wt.%Cu alloy, Sn-3.5wt.%Ag alloy, Sn-1wt.% to 3.9wt.%Ag-0.3wt.% to a kind of material in 1.5wt.%Cu alloy and the Sn-0.7wt.%Cu-0.06wt.%Ni alloy.
25., further comprise the steps: according to any one method among the claim 14-17
The 3rd metal level (L) is arranged between substrate (1,1p) and the first metal layer (M), wherein
The 3rd metal level (L) is made by alumina-base material.
26. according to the method for claim 25, wherein
The 3rd metal level (L) is made by being selected from fine aluminium, aluminium-silicon alloys and the al-si-cu alloy a kind of material.
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| EP2713684A3 (en) * | 2012-10-01 | 2014-12-03 | Robert Bosch Gmbh | Method for creating a soldered connection and circuit component |
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| JP5273101B2 (en) * | 2010-06-23 | 2013-08-28 | 株式会社デンソー | Semiconductor module and manufacturing method thereof |
| US20120000964A1 (en) * | 2010-07-01 | 2012-01-05 | Gm Global Technology Operations, Inc. | Battery tab joints and methods of making |
| CN104245203B (en) * | 2012-03-05 | 2016-10-12 | 株式会社村田制作所 | Joint method, the manufacture method of electronic installation and electronic unit |
| DE102013218423A1 (en) * | 2012-10-01 | 2014-04-17 | Robert Bosch Gmbh | Method of making a solder joint and circuit component |
| KR102311677B1 (en) * | 2014-08-13 | 2021-10-12 | 삼성전자주식회사 | Semiconductor device and method of manufacturing the same |
| US10115688B2 (en) | 2015-05-29 | 2018-10-30 | Infineon Technologies Ag | Solder metallization stack and methods of formation thereof |
| CN105906222B (en) * | 2016-07-05 | 2018-08-31 | 洛阳兰迪玻璃机器股份有限公司 | A kind of toughened vacuum glass |
| KR102335720B1 (en) * | 2017-03-27 | 2021-12-07 | 삼성전자주식회사 | Metal unit for smd and electric device with the same |
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