WO2008050251A1 - Backside wafer contact structure and method of forming the same - Google Patents

Backside wafer contact structure and method of forming the same Download PDF

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Publication number
WO2008050251A1
WO2008050251A1 PCT/IB2007/054035 IB2007054035W WO2008050251A1 WO 2008050251 A1 WO2008050251 A1 WO 2008050251A1 IB 2007054035 W IB2007054035 W IB 2007054035W WO 2008050251 A1 WO2008050251 A1 WO 2008050251A1
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WO
WIPO (PCT)
Prior art keywords
layer
contact structure
alloyed
solder
metal layer
Prior art date
Application number
PCT/IB2007/054035
Other languages
French (fr)
Inventor
Hans-Joerg Klammer
Bengt Philippsen
Original Assignee
Nxp B.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp B.V. filed Critical Nxp B.V.
Publication of WO2008050251A1 publication Critical patent/WO2008050251A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4827—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode

Definitions

  • the invention relates generally to a method of manufacturing a contact structure and a contact structure of a wafer with backside metallization.
  • Common wafer backside metallization as described above can exhibit substantial electrical contact resistance between the un-alloyed adhesion layer and the silicon substrate, so that the overall series resistance of the device is increased. This causes additional power losses and excessive heat generation during application of the device. Thus reduces the power handling capability of the device in general. Especially in the case of power semiconductors even premature degradation of the solder joint may be a further consequence.
  • US 4,451,972 discloses a method of manufacturing electronic chips with metallised back including a surface stratum of solder.
  • a first layer of titanium or chromium is deposited which are known to bond well on silicon.
  • the thickness of the first layer is about 5000 nm.
  • a second layer is applied.
  • the second layer is made of an alloy of the metal of the first layer, e.g. titanium or chromium and an other metal e.g. silver or nickel.
  • the thickness of the second layer is about 5000 nm.
  • a third layer is made of a further un-alloyed metal.
  • the surface is made of a layer of a tin or lead base solder. Unfortunately the back of this chip shows the same drawbacks as described above.
  • US 4,480,261 disclose a contact structure for a semiconductor substrate on a mounting body.
  • a multiple layer metal electrode is formed on the surface of the semiconductor.
  • the multiple layer electrodes consist of a first chromium layer, a second chromium- nickel alloy layer, a third nickel layer and a noble metal layer.
  • the nobel metal layer is bonded to a solder layer.
  • the first chromium layer serves to strengthen the bonding force between the substrate and the electrode
  • the second layer serves to bond the first layer and the third layer
  • the third layer serves as a metal which wets well with the solder and hardly melts into the solder.
  • US 5,175,609 disclose a structure for corrosion and stress-resistant interconnecting metallurgy comprising sequential layers of chromium, nickel and noble metals.
  • the invention relates generally to a method of manufacturing a contact structure and a contact structure of a wafer with a backside metallization according to claims 1 and 7.
  • Fig. 1 shows a layered structure according to the prior art
  • Fig. 2 an inventive layered structure.
  • Figure 1 shows a layered structure 1 according to the prior art.
  • a substrate 2 of silicon serves as a basis.
  • the substrate is the backside of a wafer.
  • a first layer 3 of titanium is applied on the substrate 2 .
  • This layer is an un-alloyed adhesion layer to serve as adhesive between the substrate 2 and the successive layers.
  • On top of the first layer an other layer 4 made of nickel is applied.
  • the nickel layer 4 is a solder metal layer.
  • a final top metal layer 5 e.g. made of silver.
  • the top layer serves as a wetting layer and as protection against oxidation.
  • the above described wafer backside metallization according to Figure 1 can exhibit substantial electrical contact resistance between the un-alloyed adhesion layer 3 and the silicon substrate 2. This may cause a high overall series resistance of the device 1. This causes additional power losses and heat generation during device application and thus reduces the power handling capability of the device. Especially in the case of power semiconductors even premature degradation of the solder joint may be a further consequence.
  • Figure 2 shows a device according to the invention.
  • the proposed inventive reverse alloyed wafer backside metallization allows soft solder die attach on the leadframe with negligible contact resistance to the silicon substrate. Thus the power losses and heat generation due to the wafer backside metallization are minimized. This causes an optimised power handling capability and the reliability of the device is increased.
  • an alloyed contact layer 12 is applied instead of an unalloyed adhesion layer.
  • the alloyed layer 12 is e.g. made of eutectically alloyed Gold-Silicon Au: Si.
  • the alloyed contact layer 12 serves to offer a low ohmic electrical contact to the Silicon substrate 11.
  • an additional layer 14, e.g. silver, is introduced between the alloyed contact layer 12 and the solder metal layer 15. The additional layer 14 serves to prevent the melting and liquefaction of the alloyed contact layer 12 during the soft solder die attach.
  • Gold is chosen for the alloyed contact layer and Silver is chosen for the additional layer:
  • an eutectic gold- silicon (Au: Si) phase 12 is formed at the interface between wafer backside metallization and silicon substrate 11.
  • the Au: Si eutectic alloy 12 is an almost ideal ohmic contact with negligible contact resistance, thus the contribution of the wafer backside metallization to the overall series resistance of the semiconductor device is very low or can no longer be detected.
  • the final metal layer 16, serving as wetting layer and a protection against oxidation may comprise various metals, such as e.g. silver or gold.
  • the above mentioned method and device may be for discrete semiconductor devices in wireless, e.g. lead clamp connector type SMD plastic packages, e.g. power rectifier or Schottky barrier (SBD) diodes or power Zener (PZ) diodes.
  • SBD Schottky barrier
  • PZ power Zener

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention relates to a method of manufacturing a contact structure and a respective contact structure of a wafer with a backside metallization consisting of a base (11) material with a first alloyed layer (12), a second metal layer (14) on top of the first layer, a third solder layer (15) on top of the second layer and a fourth metal layer (IS) on top of the third layer. The alloyed layer (12) is formed in the embodiment by applying gold to a silicon substrate (11) and performing a thermal alloying step to form a gold-silicon eutectic as said alloyed layer (12). The Au: Si autectic alloy (12) has negligible contact resistance.

Description

BACKSIDE WAFER CONTACT STRUCTURE AND METHOD OF FORMING THE SAME
FIELD OF THE INVENTION
The invention relates generally to a method of manufacturing a contact structure and a contact structure of a wafer with backside metallization.
During the assembly of discrete semiconductor devices in e.g. wireless (lead clamp connector type) SMD plastic packages the die attach on the lead frame is performed by means of a soft solder reflow process. The wafer backside metallization commonly employed for this process comprise an un-alloyed adhesive layer to the Silicon substrate, subsequently the solder metal layer itself and on top a final metal layer serving as wetting layer and as protection layer against oxidation. A sandwich structure as above described is shown in Figure 1.
BACKGROUND OF THE INVENTION
Common wafer backside metallization as described above can exhibit substantial electrical contact resistance between the un-alloyed adhesion layer and the silicon substrate, so that the overall series resistance of the device is increased. This causes additional power losses and excessive heat generation during application of the device. Thus reduces the power handling capability of the device in general. Especially in the case of power semiconductors even premature degradation of the solder joint may be a further consequence.
US 4,451,972 discloses a method of manufacturing electronic chips with metallised back including a surface stratum of solder. On the back a first layer of titanium or chromium is deposited which are known to bond well on silicon. The thickness of the first layer is about 5000 nm. On top of the first layer a second layer is applied. The second layer is made of an alloy of the metal of the first layer, e.g. titanium or chromium and an other metal e.g. silver or nickel. The thickness of the second layer is about 5000 nm. A third layer is made of a further un-alloyed metal. The surface is made of a layer of a tin or lead base solder. Unfortunately the back of this chip shows the same drawbacks as described above.
US 4,480,261 disclose a contact structure for a semiconductor substrate on a mounting body. On the surface of the semiconductor a multiple layer metal electrode is formed. The multiple layer electrodes consist of a first chromium layer, a second chromium- nickel alloy layer, a third nickel layer and a noble metal layer. The nobel metal layer is bonded to a solder layer. The first chromium layer serves to strengthen the bonding force between the substrate and the electrode, the second layer serves to bond the first layer and the third layer and the third layer serves as a metal which wets well with the solder and hardly melts into the solder.
US 5,175,609 disclose a structure for corrosion and stress-resistant interconnecting metallurgy comprising sequential layers of chromium, nickel and noble metals.
SUMMARY OF THE INVENTION
It is an object of the invention to mitigate the drawbacks of the prior art and it is an other object of the invention to create a backside metallization of a wafer with a very low ohmic resistance.
The invention relates generally to a method of manufacturing a contact structure and a contact structure of a wafer with a backside metallization according to claims 1 and 7.
The above-mentioned and other objects are fulfilled by a structure according to claim 1. The above-mentioned and other objects are fulfilled by a method according to claim 7.
BRIEF DESCRIPTION OF THE DRAWINGS
The above and other features and advantages of the invention will be apparent from the following description of an exemplary embodiment of the invention with reference to the accompanying drawings, in which:
Fig. 1 shows a layered structure according to the prior art; and
Fig. 2 an inventive layered structure.
DETAILED DESCRIPTION OF THE DRAWINGS
Figure 1 shows a layered structure 1 according to the prior art. A substrate 2 of silicon serves as a basis. The substrate is the backside of a wafer. On the substrate 2 a first layer 3 of titanium is applied. This layer is an un-alloyed adhesion layer to serve as adhesive between the substrate 2 and the successive layers. On top of the first layer an other layer 4 made of nickel is applied. The nickel layer 4 is a solder metal layer. On top of the nickel layer 4 is a final top metal layer 5 e.g. made of silver. The top layer serves as a wetting layer and as protection against oxidation.
The above described wafer backside metallization according to Figure 1 can exhibit substantial electrical contact resistance between the un-alloyed adhesion layer 3 and the silicon substrate 2. This may cause a high overall series resistance of the device 1. This causes additional power losses and heat generation during device application and thus reduces the power handling capability of the device. Especially in the case of power semiconductors even premature degradation of the solder joint may be a further consequence.
Figure 2 shows a device according to the invention. The proposed inventive reverse alloyed wafer backside metallization allows soft solder die attach on the leadframe with negligible contact resistance to the silicon substrate. Thus the power losses and heat generation due to the wafer backside metallization are minimized. This causes an optimised power handling capability and the reliability of the device is increased.
On top of the silicon substrate 11 an alloyed contact layer 12 is applied instead of an unalloyed adhesion layer. The alloyed layer 12 is e.g. made of eutectically alloyed Gold-Silicon Au: Si. The alloyed contact layer 12 serves to offer a low ohmic electrical contact to the Silicon substrate 11. Furthermore an additional layer 14, e.g. silver, is introduced between the alloyed contact layer 12 and the solder metal layer 15. The additional layer 14 serves to prevent the melting and liquefaction of the alloyed contact layer 12 during the soft solder die attach.
For the following description it is assumed that Gold is chosen for the alloyed contact layer and Silver is chosen for the additional layer:
Owing to a thermal alloying step during the gold deposition process of the layer 13 or afterwards an eutectic gold- silicon (Au: Si) phase 12 is formed at the interface between wafer backside metallization and silicon substrate 11. The Au: Si eutectic alloy 12 is an almost ideal ohmic contact with negligible contact resistance, thus the contribution of the wafer backside metallization to the overall series resistance of the semiconductor device is very low or can no longer be detected. On the other hand, by introducing an additional silver layer 14 between the eutectically alloyed Au: Si 12,13 contact layer and the subsequent solder metal layer 15, e.g. nickel, or NiX compounds, where X could be e.g. chromium, iron or vanadium, the melting and liquefaction of the Au:Si eutectic alloy during the soft solder die attach process is impeded at least up to 4000C reflow process temperature. Thus a broad process window is available for the soft solder process. The final metal layer 16, serving as wetting layer and a protection against oxidation, may comprise various metals, such as e.g. silver or gold.
The above mentioned method and device may be for discrete semiconductor devices in wireless, e.g. lead clamp connector type SMD plastic packages, e.g. power rectifier or Schottky barrier (SBD) diodes or power Zener (PZ) diodes.
REFERENCES
1 backside metallization of a wafer according to prior art
2 base
3 first non-alloyed
4 solder metal layer
5 metal layer
10 backside metallization of a wafer according to prior art
11 base
12 alloyed layer
13 layer
14 metal layer
15 solder material layer
16 metal layer

Claims

1. Contact structure of a wafer with a backside metallization (10) consisting of a base material (11) with a first alloyed layer(12), a second metal layer (14) on top of the first layer (12), a third solder layer (15) on top of the second layer (14) and a fourth metal layer (16) on top of the third layer (15).
2. Contact structure according to claim 1 , wherein the base (11) is made of silicon.
3. Contact structure according to claim 1 or 2, wherein the alloyed first layer (12) consists of an eutectic gold-silicon (Au:Si) phase.
4. Contact structure according to claim one of claims 1 to 3, wherein the second metal layer (14) is made of silver.
5. Contact structure according to claim one of claims 1 to 4, wherein the third solder layer (15) is made of nickel or NiX compounds, where X is chromium, iron or vanadium.
6. Contact structure according to claim one of claims 1 to 5, wherein the fourth metal layer (16) is made of silver or gold.
7. Method of manufacturing a contact structure on the backside of a wafer comprising the steps of applying a first layer (12) on top of the backside of the base (11) material and alloying it, applying a second metal layer (14) on top of the first layer, applying a third solder layer (15) on top of the second layer (14) and applying a fourth metal layer (16) on top of the third layer.
PCT/IB2007/054035 2006-10-23 2007-10-04 Backside wafer contact structure and method of forming the same WO2008050251A1 (en)

Applications Claiming Priority (2)

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EP06122724.5 2006-10-23
EP06122724 2006-10-23

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104409379A (en) * 2014-11-20 2015-03-11 上海华虹宏力半导体制造有限公司 Method for improving color abnormity of wafer hotspot testing on the back of silicone chip
CN104733418A (en) * 2013-12-24 2015-06-24 恩智浦有限公司 Die Substrate Assembly And Method
DE102014114982A1 (en) * 2014-10-15 2016-04-21 Infineon Technologies Ag Method of forming a chip package and chip package
WO2016130690A1 (en) * 2015-02-10 2016-08-18 Revera, Incorporated Systems and approaches for semiconductor metrology and surface analysis using secondary ion mass spectrometry
US9728412B2 (en) 2010-10-25 2017-08-08 Stmicroelectronics S.R.L Integrated circuits with backside metalization and production method thereof

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JPS60110127A (en) * 1983-11-18 1985-06-15 Sony Corp Semiconductor device having laminated metal electrode
US4737839A (en) * 1984-03-19 1988-04-12 Trilogy Computer Development Partners, Ltd. Semiconductor chip mounting system
JPH01220439A (en) * 1988-02-29 1989-09-04 Nec Corp Manufacture of semiconductor device

Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
JPS60110127A (en) * 1983-11-18 1985-06-15 Sony Corp Semiconductor device having laminated metal electrode
US4737839A (en) * 1984-03-19 1988-04-12 Trilogy Computer Development Partners, Ltd. Semiconductor chip mounting system
JPH01220439A (en) * 1988-02-29 1989-09-04 Nec Corp Manufacture of semiconductor device

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10796918B2 (en) 2010-10-25 2020-10-06 Stmicroelectronics S.R.L. Integrated circuits with backside metalization and production method thereof
US9728411B2 (en) 2010-10-25 2017-08-08 Stmicroelectronics S.R.L. Integrated circuits with backside metalization and production method thereof
US9728412B2 (en) 2010-10-25 2017-08-08 Stmicroelectronics S.R.L Integrated circuits with backside metalization and production method thereof
CN104733418A (en) * 2013-12-24 2015-06-24 恩智浦有限公司 Die Substrate Assembly And Method
EP2889903A1 (en) * 2013-12-24 2015-07-01 Nxp B.V. Die with a multilayer backside interface layer for solder bonding to a substrate and corresponding manufacturing method
US9324674B2 (en) 2013-12-24 2016-04-26 Ampleon Netherlands B.V. Die substrate assembly and method
DE102014114982A1 (en) * 2014-10-15 2016-04-21 Infineon Technologies Ag Method of forming a chip package and chip package
US9837381B2 (en) 2014-10-15 2017-12-05 Infineon Technologies Ag Method of forming a chip assembly with a die attach liquid
DE102014114982B4 (en) 2014-10-15 2023-01-26 Infineon Technologies Ag Method of forming a chip package
CN104409379A (en) * 2014-11-20 2015-03-11 上海华虹宏力半导体制造有限公司 Method for improving color abnormity of wafer hotspot testing on the back of silicone chip
CN104409379B (en) * 2014-11-20 2017-06-23 上海华虹宏力半导体制造有限公司 Improve the method that silicon chip back side wafer focus tests color exception
WO2016130690A1 (en) * 2015-02-10 2016-08-18 Revera, Incorporated Systems and approaches for semiconductor metrology and surface analysis using secondary ion mass spectrometry
US10403489B2 (en) 2015-02-10 2019-09-03 Nova Measuring Instruments Inc. Systems and approaches for semiconductor metrology and surface analysis using secondary ion mass spectrometry
US10910208B2 (en) 2015-02-10 2021-02-02 Nova Measuring Instruments, Inc. Systems and approaches for semiconductor metrology and surface analysis using secondary ion mass spectrometry
US11430647B2 (en) 2015-02-10 2022-08-30 Nova Measuring Instruments, Inc. Systems and approaches for semiconductor metrology and surface analysis using Secondary Ion Mass Spectrometry
US10056242B2 (en) 2015-02-10 2018-08-21 Nova Measuring Instruments Inc. Systems and approaches for semiconductor metrology and surface analysis using secondary ion mass spectrometry
US11764050B2 (en) 2015-02-10 2023-09-19 Nova Measuring Instruments Inc. Systems and approaches for semiconductor metrology and surface analysis using secondary ion mass spectrometry

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