JP2526434B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2526434B2 JP2526434B2 JP3060653A JP6065391A JP2526434B2 JP 2526434 B2 JP2526434 B2 JP 2526434B2 JP 3060653 A JP3060653 A JP 3060653A JP 6065391 A JP6065391 A JP 6065391A JP 2526434 B2 JP2526434 B2 JP 2526434B2
- Authority
- JP
- Japan
- Prior art keywords
- plating layer
- semiconductor device
- copper
- manufacturing
- nickel plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3473—Plating of solder
Landscapes
- Wire Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、樹脂モールドされたＩ
Ｃチップから引き出された外部リードを有する半導体装
置の製造方法に係り、特には、フィルムキャリア(ＴＡ
Ｂ)方式に基づいてパッケージ化された半導体装置の外
部リードのめっき処理技術の改善に関する。BACKGROUND OF THE INVENTION The present invention relates to a resin-molded I
The present invention relates to a method of manufacturing a semiconductor device having an external lead drawn from a C chip, and more particularly, to a film carrier (TA
B) The present invention relates to improvement of plating technology for external leads of a semiconductor device packaged based on the method.
【０００２】[0002]
【従来の技術】図２は、フィルムキャリア(ＴＡＢ)方式
に基づいてパッケージ化された半導体装置をプリント基
板に実装した状態を示す断面図である。同図において、
１はＴＡＢパッケージされた半導体装置、２はプリント
基板、３はＩＣチップ、４は樹脂モールド、５は外部リ
ード、６はＩＣチップ３と外部リード５とを接続するた
めのバンプ、７は外部リード５と接続するためにプリン
ト基板２上に形成された導体である。2. Description of the Related Art FIG. 2 is a sectional view showing a state in which a semiconductor device packaged based on a film carrier (TAB) system is mounted on a printed circuit board. In the figure,
1 is a semiconductor device packaged in a TAB package, 2 is a printed circuit board, 3 is an IC chip, 4 is a resin mold, 5 is an external lead, 6 is a bump for connecting the IC chip 3 and the external lead 5, and 7 is an external lead. 5 is a conductor formed on the printed circuit board 2 in order to connect with 5.
【０００３】上記の構成において、外部リード５は電気
伝導性に優れ、かつ、プリント基板２上の導体７に十分
な密着性を保って接続される必要があるので、従来は、
図３(a)に示すように、銅箔１０の上にはんだ(錫−鉛合
金)めっき層１２を直接形成する製造方法が採られてい
る。In the above structure, the external lead 5 is excellent in electrical conductivity and needs to be connected to the conductor 7 on the printed circuit board 2 with sufficient adhesion.
As shown in FIG. 3A, a manufacturing method is employed in which a solder (tin-lead alloy) plating layer 12 is directly formed on a copper foil 10.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、従来の
ように、銅箔１０の上にはんだめっき層１２を直接形成
すると、たとえ室内に放置した状態においても、時間経
過に伴って、いわゆるカーケンドール効果による相互拡
散が起こり、その結果、図３(b)に示すように、銅箔１
０とはんだめっき層１２との間に合金層１４が形成され
る。However, when the solder plating layer 12 is directly formed on the copper foil 10 as in the conventional case, the so-called Kirkendall effect is obtained with time even if the solder plating layer 12 is left indoors. Interdiffusion occurs due to the copper foil 1 and, as a result, as shown in FIG.
An alloy layer 14 is formed between 0 and the solder plating layer 12.
【０００５】この合金層１４は、銅−錫からなる金属間
化合物であって、硬くて脆い。しかも、長時間の内に
は、相互拡散により銅箔１０を含めて外部リード５の全
てが合金化してしまう。たとえば、めっき直後(図３(a)
の状態)における外部リード５の全体の厚さを４０μm、
銅箔１０の厚さを２０μmとすると、最終的には４０μm
の合金層１４が形成される。The alloy layer 14 is an intermetallic compound composed of copper-tin and is hard and brittle. Moreover, all the external leads 5 including the copper foil 10 are alloyed due to mutual diffusion within a long time. For example, immediately after plating (Fig. 3 (a)
State), the total thickness of the outer lead 5 is 40 μm,
If the thickness of the copper foil 10 is 20 μm, the final thickness is 40 μm.
The alloy layer 14 is formed.
【０００６】このため、半導体装置１の搬送時やプリン
ト基板２に実装する際のハンドリング時において、この
外部リード５に外部応力が加わると、合金層１４からク
ラックが入り、外部リード５が破断したり、電気抵抗が
増加するなどの不具合を生じていた。Therefore, when external stress is applied to the external leads 5 during the handling of the semiconductor device 1 during transportation or mounting on the printed board 2, the alloy layer 14 is cracked and the external leads 5 are broken. And problems such as an increase in electrical resistance occurred.
【０００７】[0007]
【課題を解決するための手段】本発明は、上述した課題
を解決するためになされたものであって、外部リードの
めっき処理に伴う合金層の成長を抑制し、外部リードの
破断や電気抵抗の増加などの不具合発生を回避するよう
にするものである。The present invention has been made in order to solve the above-mentioned problems, and suppresses the growth of an alloy layer due to the plating treatment of the outer leads, thereby breaking the outer leads or causing the electrical resistance. This is to avoid the occurrence of problems such as increase in
【０００８】そのため、第１発明に係る半導体装置で
は、銅箔の上にニッケルめっき層を、さらに、このニッ
ケルめっき層の上に銅めっき層を、この銅めっき層の上
にはんだめっき層を順次形成して構成されている。第２
発明に係る半導体装置は、第１発明の装置において、ニ
ッケルめっき層の形成に代えて、パラジウムめっき層が
形成されている。 Therefore, in the semiconductor device according to the first invention ,
Add a nickel plating layer on the copper foil, and
On the copper plating layer, and on top of this copper plating layer
And a solder plating layer is sequentially formed on it. Second
The semiconductor device according to the invention is the device of the first invention, wherein
Instead of forming a nickel plating layer, a palladium plating layer
Has been formed.
【０００９】第３発明に係る半導体装置の製造方法で
は、外部リードは、銅箔の上にニッケルめっき層を、さ
らに、このニッケルめっき層の上に銅めっき層を、この
銅めっき層の上にはんだめっき層を順次形成して構成す
る。 [0009] In the method of manufacturing a semiconductor device according to a third shot bright, the external lead, a nickel plating layer on the copper foil, and
In addition, a copper plating layer on this nickel plating layer
Solder plating layer is sequentially formed on the copper plating layer.
It
【００１０】第４発明に係る半導体装置の製造方法で
は、第３発明の方法において、ニッケルめっき層の形成
に代えて、パラジウムめっき層を形成する。 [0010] In the method of manufacturing a semiconductor device according to a fourth shot bright, in the method of the third aspect of the present invention, the formation of the nickel plating layer
Instead of this, a palladium plating layer is formed.
【００１１】[0011]
【作用】はんだめっき層の下層にニッケルめっき層ある
いはパラジウムめっき層が形成されているので、銅箔中
の銅とはんだめっき層中の錫との相互拡散による合金層
の成長が抑制される。そのため、銅箔の細りがなく、機
械的強度および電気抵抗も良好なものとなる。Since the nickel plating layer or the palladium plating layer is formed below the solder plating layer, the growth of the alloy layer due to the mutual diffusion of copper in the copper foil and tin in the solder plating layer is suppressed. Therefore, the copper foil does not become thin, and the mechanical strength and electric resistance are good.
【００１２】さらに、ニッケルめっき層あるいはパラジ
ウムめっき層の上に銅めっき層を形成するようにすれ
ば、次のはんだめっき層を形成する際の密着性が改善さ
れ、はんだめっき層の剥離等もなくすことができる。Further, if the copper plating layer is formed on the nickel plating layer or the palladium plating layer, the adhesion at the time of forming the next solder plating layer is improved and the peeling of the solder plating layer is eliminated. be able to.
【００１３】[0013]
【実施例】図１は本発明の製造方法に係る半導体装置の
外部リードの断面図であり、図３に対応する部分には同
一の符号を付す。1 is a cross-sectional view of an external lead of a semiconductor device according to a manufacturing method of the present invention, in which parts corresponding to those in FIG. 3 are designated by the same reference numerals.
【００１４】この半導体装置の製造方法では、図１(a)
に示すように、外部リード５の作成に際して、銅箔１０
の上にニッケルめっき層１６をたとえば０.１〜１.５μ
m程度の厚さに形成する。次に、このニッケルめっき層
１６の上に銅めっき層１８をたとえば０.５〜５μm程度
の厚さに形成する。さらに、この銅めっき層１８の上に
はんだ(錫−鉛合金)めっき層１２をたとえば１０μm程
度の厚さに形成する。In this method of manufacturing a semiconductor device, as shown in FIG.
As shown in FIG.
A nickel plating layer 16 is formed on the surface of, for example, 0.1 to 1.5 μm.
It is formed to a thickness of about m. Next, a copper plating layer 18 is formed on the nickel plating layer 16 to have a thickness of, for example, about 0.5 to 5 μm. Further, a solder (tin-lead alloy) plating layer 12 is formed on the copper plating layer 18 to have a thickness of, for example, about 10 μm.
【００１５】上記のめっき処理をした後にこれを室内に
放置した場合、図１(b)に示すように、銅箔１０とニッ
ケルめっき層１６との間では、殆ど合金層は形成されず
(合金層の厚さは数Å程度で無視できる)、ニッケルめっ
き層１６がそのまま残存する。また、銅めっき層１８と
はんだめっき層１２との間では、銅と錫の相互拡散によ
り銅−錫合金層２２が形成されるが、銅めっき層１６は
最初から薄肉に形成されているから、銅−錫合金層２２
も薄肉のものとなる。また、ニッケルめっき層１６と銅
めっき層１８との間では殆ど合金層は形成されない。When the above plating treatment is allowed to stand indoors, an alloy layer is hardly formed between the copper foil 10 and the nickel plating layer 16 as shown in FIG. 1 (b).
(The thickness of the alloy layer is a few Å and can be ignored), and the nickel plating layer 16 remains. Further, between the copper plating layer 18 and the solder plating layer 12, a copper-tin alloy layer 22 is formed by mutual diffusion of copper and tin, but since the copper plating layer 16 is formed thin from the beginning, Copper-tin alloy layer 22
Is also thin. Further, almost no alloy layer is formed between the nickel plating layer 16 and the copper plating layer 18.
【００１６】したがって、めっき直後(図１(a)の状態)
における外部リード５の全体の厚さを４０μm、銅めっ
き層１８の厚が０.５〜５μm程度とした場合には、銅−
錫合金層２２の厚さも最大でも５μm程度となり、外部
リード５の全体の厚さに比べて薄肉であるため、クラッ
クは発生しない。Therefore, immediately after plating (state of FIG. 1 (a))
In the case where the total thickness of the outer lead 5 in the above is 40 μm and the thickness of the copper plating layer 18 is about 0.5 to 5 μm, copper-
The maximum thickness of the tin alloy layer 22 is about 5 μm, which is thinner than the total thickness of the external leads 5, and therefore no cracks occur.
【００１７】なお、上記の実施例においては、ニッケル
めっき層１６の上に銅めっき層１８を形成するので、次
のはんだめっき層１２を形成する際の密着性が改善さ
れ、はんだめっき層１２の剥離等もなくすことができ
る。In the above embodiment, since the copper plating layer 18 is formed on the nickel plating layer 16, the adhesion at the time of forming the next solder plating layer 12 is improved and the solder plating layer 12 is It is possible to eliminate peeling and the like.
【００１８】さらに、上記の実施例のニッケルめっき層
１６に代えてパラジウムめっき層をたとえば０.０５〜
１.５μm程度の厚さに形成しても、上記と同様の効果が
得られる。Further, in place of the nickel plating layer 16 of the above embodiment, a palladium plating layer is used, for example, 0.05 to 5.
Even if it is formed to a thickness of about 1.5 μm, the same effect as above can be obtained.
【００１９】[0019]
【発明の効果】本発明によれば、外部リードのめっき処
理に伴う合金層の成長が抑制されるので、外部リードの
破断や電気抵抗の増加などの不具合発生が回避される。According to the present invention, since the growth of the alloy layer due to the plating treatment of the external leads is suppressed, the occurrence of defects such as breakage of the external leads and increase of electric resistance can be avoided.
【００２０】特に、ニッケルめっき層あるいはパラジウ
ムめっき層の上に直接にはんだめっき層を形成するので
なく、両者の間に銅めっき層を形成するようにすれば、
はんだめっき層の密着性が改善され、はんだめっき層の
剥離等の発生も有効に防止することができる。Particularly, if the solder plating layer is not directly formed on the nickel plating layer or the palladium plating layer, but the copper plating layer is formed between them,
The adhesiveness of the solder plating layer is improved, and the occurrence of peeling of the solder plating layer can be effectively prevented.
【図面の簡単な説明】[Brief description of drawings]
【図１】本発明の製造方法に係る半導体装置の外部リー
ドの断面図で、図１(a)はめっき処理した直後の状態、
図１(b)はめっき処理後の経時変化により合金層が形成
された状態をそれぞれ示す。FIG. 1 is a cross-sectional view of an external lead of a semiconductor device according to a manufacturing method of the present invention, FIG. 1 (a) shows a state immediately after a plating process,
FIG. 1 (b) shows a state in which an alloy layer is formed due to a change with time after the plating treatment.
【図２】半導体装置をプリント基板に実装した状態を示
す断面図である。FIG. 2 is a cross-sectional view showing a state in which a semiconductor device is mounted on a printed board.
【図３】従来の製造方法に係る半導体装置の外部リード
の断面図で、図３(a)はめっき処理した直後の状態、図
３(b)はめっき処理後の経時変化により合金層が形成さ
れた状態をそれぞれ示す。FIG. 3 is a cross-sectional view of an external lead of a semiconductor device according to a conventional manufacturing method, FIG. 3 (a) shows a state immediately after a plating treatment, and FIG. 3 (b) shows an alloy layer formed by a change with time after the plating treatment. The respective states are shown.
１…半導体装置、３…ＩＣチップ、４…樹脂モールド、
５…外部リード、１０…銅箔、１２…はんだめっき層、
１６…ニッケルめっき層(パラジウムめっき層)、１８…
銅めっき層。1 ... Semiconductor device, 3 ... IC chip, 4 ... Resin mold,
5 ... External lead, 10 ... Copper foil, 12 ... Solder plating layer,
16 ... Nickel plating layer (palladium plating layer), 18 ...
Copper plating layer.
Claims (4)
に、このＩＣチップをプリント基板等に電気的に接続す
るための外部リードが前記樹脂モールドから引き出され
ているフィルムキャリア(ＴＡＢ)方式に基づいてパッケ
ージ化された半導体装置であって、 前記外部リードは、銅箔の上にニッケルめっき層を、さ
らに、このニッケルめっき層の上に銅めっき層を、この
銅めっき層の上にはんだめっき層を順次形成して構成さ
れていることを特徴とする半導体装置。 1. An IC chip is molded with resin.
To electrically connect this IC chip to a printed circuit board, etc.
External leads for pulling out from the resin mold
Based on the existing film carrier (TAB) method
And a nickel plating layer on the copper foil.
In addition, a copper plating layer on this nickel plating layer
A solder plating layer is sequentially formed on the copper plating layer.
A semiconductor device characterized in that
ッケルめっき層の形成に代えて、パラジウムめっき層が
形成されていることを特徴とする半導体装置。 2. The semiconductor device according to claim 1, wherein
Instead of forming a nickel plating layer, a palladium plating layer
A semiconductor device characterized by being formed.
に、このＩＣチップをプリント基板等に電気的に接続す
るための外部リードが前記樹脂モールドから引き出され
ているフィルムキャリア(ＴＡＢ)方式に基づいてパッケ
ージ化された半導体装置の製造方法であって、 前記外部リードは、銅箔の上にニッケルめっき層を、さ
らに、このニッケルめっき層の上に銅めっき層を、この
銅めっき層の上にはんだめっき層を順次形成して構成す
ることを特徴とする半導体装置の製造方法。3. A package based on a film carrier (TAB) method in which an IC chip is resin-molded and external leads for electrically connecting the IC chip to a printed circuit board or the like are pulled out from the resin mold. In the method for manufacturing a semiconductor device, the external lead comprises a nickel plating layer on a copper foil, and a copper plating layer on the nickel plating layer.
A method for manufacturing a semiconductor device, comprising forming a solder plating layer on a copper plating layer in order.
おいて、ニッケルめっき層の形成に代えて、パラジウム
めっき層を形成することを特徴とする半導体装置の製造
方法。 4. A method of manufacturing a semiconductor device according to claim 3.
In place of forming the nickel plating layer, palladium
Manufacturing of a semiconductor device characterized by forming a plating layer
Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3060653A JP2526434B2 (en) | 1991-03-26 | 1991-03-26 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3060653A JP2526434B2 (en) | 1991-03-26 | 1991-03-26 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04312937A JPH04312937A (en) | 1992-11-04 |
| JP2526434B2 true JP2526434B2 (en) | 1996-08-21 |
Family
ID=13148513
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3060653A Expired - Lifetime JP2526434B2 (en) | 1991-03-26 | 1991-03-26 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2526434B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5650661A (en) * | 1993-12-27 | 1997-07-22 | National Semiconductor Corporation | Protective coating combination for lead frames |
| US5436082A (en) * | 1993-12-27 | 1995-07-25 | National Semiconductor Corporation | Protective coating combination for lead frames |
| US5728285A (en) * | 1993-12-27 | 1998-03-17 | National Semiconductor Corporation | Protective coating combination for lead frames |
| JP7324665B2 (en) * | 2019-09-13 | 2023-08-10 | シチズンファインデバイス株式会社 | submount |
-
1991
- 1991-03-26 JP JP3060653A patent/JP2526434B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04312937A (en) | 1992-11-04 |
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