KR100427827B1 - semiconductor installed board using Au wire connection - Google Patents

semiconductor installed board using Au wire connection Download PDF

Info

Publication number
KR100427827B1
KR100427827B1 KR10-2001-0012042A KR20010012042A KR100427827B1 KR 100427827 B1 KR100427827 B1 KR 100427827B1 KR 20010012042 A KR20010012042 A KR 20010012042A KR 100427827 B1 KR100427827 B1 KR 100427827B1
Authority
KR
South Korea
Prior art keywords
mounting substrate
semiconductor mounting
semiconductor
barrier layer
layer
Prior art date
Application number
KR10-2001-0012042A
Other languages
Korean (ko)
Other versions
KR20020072069A (en
Inventor
이규한
Original Assignee
이규한
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이규한 filed Critical 이규한
Priority to KR10-2001-0012042A priority Critical patent/KR100427827B1/en
Publication of KR20020072069A publication Critical patent/KR20020072069A/en
Application granted granted Critical
Publication of KR100427827B1 publication Critical patent/KR100427827B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 Au 와이어 본딩(wire bonding)으로 반도체 칩과 결합되어, 외부회로와 반도체 칩이 전기적으로 연결될 수 있도록 레이 아웃(layout) 하는 반도체 실장기판의 적층 구조에 관한 것으로, 상기 반도체 실장기판의 최상층에 적층되어 Au 와이어가 접합되는 Au를 가진 접합층과, 상기 Au를 가진 접합층의 직하에 위치하고, Ag를 포함하는 재질로 이루어진 장벽층을 포함하는 반도체실장기판을 제공하여 보다 개선된 반도체 패키지를 구현 가능하게 한다.The present invention relates to a laminated structure of a semiconductor mounting substrate coupled to a semiconductor chip by Au wire bonding, and laid out so that external circuits and the semiconductor chip can be electrically connected to each other. An improved semiconductor package is provided by providing a semiconductor mounting substrate comprising a bonding layer having Au laminated to and bonded to an Au wire, and a barrier layer made of a material containing Ag, which is located directly below the bonding layer having Au. Make it implementable.

Description

금 와이어를 통하여 결합되는 반도체 실장기판 {semiconductor installed board using Au wire connection}Semiconductor boards bonded via gold wires {semiconductor installed board using Au wire connection}

본 발명은 반도체 실장기판에 관한 것으로, 좀 더 자세하게는 Au 와이어 본딩(wire bonding)을 통하여 반도체 칩과 결합되어, 외부회로와 상기 반도체 칩이 전기적으로 연결될 수 있도록 레이아웃(layout) 하는 반도체 실장기판의 적층 구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor mounting substrate, and more particularly, to a semiconductor mounting substrate which is coupled to a semiconductor chip through Au wire bonding and layouts such that an external circuit and the semiconductor chip can be electrically connected. It relates to a laminated structure.

반도체 패키지(semiconductor package)란 반도체 칩을 포함하는 상용화된 기능성 부품소자의 명칭으로, 이는 다른 전기적 소자와 더불어 PCB(Printed Circuit Board)등의 회로기판에 체결되어 전자 회로를 구성하는 중요한 부품의 하나이다.A semiconductor package is a name of a commercially available functional component including a semiconductor chip, which is one of important components that are connected to a circuit board such as a printed circuit board (PCB) together with other electrical components to form an electronic circuit.

이러한 반도체 패키지는 그 구성에 있어서, 크게 반도체 칩과, 이러한 반도체 칩이 실장되어 이와 전기적으로 연결되는 반도체 실장기판으로 이루어진다. 이러한 반도체 실장기판은 외부회로와 반도체 칩을 전기적으로 연결시키는 역할을 하며 리드 프레임, BGA(Ball Gride Array), PGA(Pin Grid Array) , 또는 Tape-BGA 등 그 종류가 매우 다양한데, 이러한 반도체 실장기판과 반도체칩은 통상 Au 와이어를 통하여 서로 전기적으로 연결된다.Such a semiconductor package is largely composed of a semiconductor chip and a semiconductor mounting substrate on which the semiconductor chip is mounted and electrically connected thereto. Such a semiconductor mounting board serves to electrically connect an external circuit and a semiconductor chip, and a variety of types such as a lead frame, a ball grid array (BGA), a pin grid array (PGA), or a tape-BGA are various. And the semiconductor chip are usually electrically connected to each other through Au wire.

이와 같이 반도체 칩과, Au와이어를 통하여 반도체칩과 전기적으로 연결되는 반도체 실장기판으로 구성되는 반도체 패키지의 일례로, 상기 반도체 실장기판이 리드프레임인 반도체 패키지를 통하여 이를 설명하면, 도 1은 리드프레임(20 : 도 2 참조)을 사용하는 반도체 패키지(1)의 분해 사시도로서, 이러한 반도체패키지(1)는 크게 기억소자인 반도체 칩(10)과, 이러한 반도체 칩(10)이 장착되는 반도체 실장기판인 리드프레임(20)으로 이루어진다.As an example of a semiconductor package including a semiconductor chip and a semiconductor mounting substrate electrically connected to the semiconductor chip through Au wire, the semiconductor mounting substrate will be described through a semiconductor package which is a lead frame. 2 is an exploded perspective view of a semiconductor package 1 using (see FIG. 2), wherein the semiconductor package 1 is largely a semiconductor chip 10 which is a storage element and a semiconductor mounting substrate on which the semiconductor chip 10 is mounted. The lead frame 20 is formed.

이때, 반도체 칩(10)이란 웨이퍼 상에 여러 가지 물질의 적층 및 이의 패터닝을 통하여 완성되는 반도체 기판의 기본 셀로서, 그 상부에는 외부회로와 연결되는 부분인 다수의 게이트 영역(미도시)을 가지고 있으며, 리드프레임(20)에는 반도체 칩(10)의 게이트 영역과 각각 전기적으로 연결되는 다수의 내부리드(12)와, 외부회로와 전기적으로 연결되는 다수의 외부리드(13)를 가지고 있어, 외부회로와 반도체 칩(10)이 전기적으로 연결될 수 있도록 레이 아웃(layout)하는 역할을 한다.In this case, the semiconductor chip 10 is a basic cell of a semiconductor substrate that is completed by stacking and patterning various materials on a wafer, and has a plurality of gate regions (not shown), which are connected to external circuits, on top thereof. The lead frame 20 has a plurality of internal leads 12 electrically connected to gate regions of the semiconductor chip 10, and a plurality of external leads 13 electrically connected to external circuits. It serves to layout the circuit and the semiconductor chip 10 to be electrically connected.

또한 이와 같이 반도체 칩(10)이 실장된 리드프레임(20)은 통상 온도 변화 또는 불순물 등의 외부 요소로부터의 보호를 위하여, 외부회로와 연결되는 외부리드(13) 일부를 제외한 모든 부분에 EMC(50 : Epoxy Mold Compound)등의 물질이 코팅되어 이루어진다.In addition, the lead frame 20 in which the semiconductor chip 10 is mounted in this manner is generally used in all parts except the part of the external lead 13 connected to the external circuit for protection from external elements such as temperature change or impurities. 50: Epoxy Mold Compound)

참고로 리드프레임(20)에 대하여 좀 더 자세히 설명하면, 이는 통상 구리(Cu)또는 철(Fe) 등의 물질로 이루어지는 판 상의 물질로 도 2와 같이 반도체 칩(도 1의 10)이 안착되는 패드부(11)와, 이러한 패드부(11)를 지지하는 타이바(14)와, 상기 패드부(11)에 안착되는 반도체 칩의 게이트 영역과 각각 연결되는 다수의 내부 리드(12) 및 외부회로와 각각 연결되는 다수의 외부리드(13)를 포함하고 있다.For reference, the lead frame 20 will be described in more detail. This is a plate-like material made of a material such as copper (Cu) or iron (Fe), and the semiconductor chip (10 of FIG. 1) is seated as shown in FIG. 2. A pad portion 11, a tie bar 14 supporting the pad portion 11, a plurality of inner leads 12 and an outer portion respectively connected to the gate region of the semiconductor chip seated on the pad portion 11; A plurality of external leads 13 are respectively connected to the circuit.

미설명 부호 (15)는 공정 중에 가해지는 물리적 충격으로부터 외부리드(13)의 변형을 막기 위하여, 다수의 외부리드(13)를 하나로 연결하는 바아(bar)로서 이는 반도체 패키지(도 1의 1)의 제조 공정 중에 절단된다.Reference numeral 15 is a bar connecting a plurality of external leads 13 to one in order to prevent deformation of the external leads 13 from physical shocks applied during the process, which is a semiconductor package (1 in FIG. 1). Is cut during the manufacturing process.

이와 같은 구성을 가지는 반도체 패키지의 제조방법을 도 1 및 도 2를 통하여 간략히 설명하면, 먼저 반도체 칩(10)은 리드 프레임(20)의 패드부(11)에 장착된 후, 와이어 본딩(wire bonding)에 의하여 내부리드(12)와 서로 연결되는데, 이러한 와이어로는 통상 저항이 작은 금(Au)으로 이루어진 Au와이어(40)가 사용되며, 이를 통하여 반도체 칩(10)과 리드프레임(20)은 전기적으로 연결된다.A method of manufacturing a semiconductor package having such a configuration will be briefly described with reference to FIGS. 1 and 2. First, the semiconductor chip 10 is mounted on the pad portion 11 of the lead frame 20, and then wire bonding. It is connected to the inner lead 12 by a), as the wire is usually used Au wire 40 made of gold (Au) of low resistance, through which the semiconductor chip 10 and the lead frame 20 Electrically connected.

이때 특히 Au 와이어(40)와 내부 리드(12)간의 신뢰성 있는 접합을 위하여, 통상 리드 프레임(20) 상에는 Au 와이어(40)와의 접합 특성이 뛰어난 연결매체 금속의 도금과정이 더욱 필요하게 되는데 , 이러한 금속층의 도금 후 통상 275℃ 정도의 고온환경에서 1분 정도 소자를 노출시켜 Au 와이어(40)와 도금층 금속의 원자이동(확산)을 통한 재결정으로 접합하게 된다.In this case, in particular, in order to reliably bond between the Au wire 40 and the inner lead 12, a plating process of a connection medium metal having excellent bonding properties with the Au wire 40 is usually required on the lead frame 20. After plating of the metal layer, the device is exposed for about 1 minute in a high temperature environment of about 275 ° C., thereby bonding the Au wire 40 and the recrystallization through atomic transfer (diffusion) of the plating layer metal.

이 후 전술한 Au 와이어(40)를 사용하여 반도체 칩(10)과 리드프레임의 내부리드(12)가 연결되면, 통상 175℃ 정도의 고온환경에서 수분 동안 반도체 칩(10)과, 리드프레임(20)의 외부 리드(13)를 제외한 전면에 EMC(Epoxy Mold Compound)등의 물질이 코팅되어 반도체 패키지(1)가 완성된다.Then, when the semiconductor chip 10 and the inner lead 12 of the lead frame are connected using the Au wire 40 described above, the semiconductor chip 10 and the lead frame (for a few minutes in a high temperature environment of about 175 ° C.) The semiconductor package 1 is completed by coating a material such as an epoxy mold compound (EMC) on the entire surface except the external lead 13 of FIG.

전술한 반도체패키지의 제조공정은 다른 종류의 반도체 실장기판을 사용하는 경우에도 동일하게 적용되는데 즉, BGA(Ball Gride Array), PGA(Pin Grid Array) , 또는 Tape-BGA 등의 여러 가지 종류의 반도체실장기판 역시 반도체 칩과 연결되는 내부연결부과, 외부회로와 연결되는 외부연결부을 각각 가지고 있고, 또한 반도체 칩과 내부연결부의 전기적 연결을 위하여 Au 와이어를 사용하여, 고온에서 열적이력에 의한 접합 방법을 사용하게 된다.The above-described manufacturing process of the semiconductor package is similarly applied to the case of using a different type of semiconductor mounting substrate, that is, various kinds of semiconductors such as ball grid array (BGA), pin grid array (PGA), or tape-BGA. The mounting board also has an internal connection part connected to the semiconductor chip and an external connection part connected to the external circuit, and also uses an Au wire for the electrical connection of the semiconductor chip and the internal connection, using a thermal bonding method at high temperature. Done.

또한 이러한 반도체 칩이 실장된 반도체실장기판은 외부의 충격으로부터 보호하기 위하여, 고온의 환경에서 전술한 EMC등의 물질로 이루어진 몰딩 소재로 그 표면을 코팅하여 이루어진다.In addition, the semiconductor mounting substrate on which the semiconductor chip is mounted is formed by coating the surface with a molding material made of a material such as EMC in a high temperature environment in order to protect it from external impact.

이때 특히 전술한 Au 와이어를 통한 반도체 칩과 반도체 실장기판의 결합을 위하여, 이의 단면을 도시한 도3과 같이, 반도체 실장기판(30)의 표면에는, 전술한 리드프레임과 동일하게, Au 와이어(40)와의 접합 특성을 개선하기 위한 도금층(30a)이 적층되는데 이러한 도금 적층 금속으로는, 통상 Au와 접합특성이 뛰어난 Ag 또는 Au등의 금속이 사용된다.At this time, in particular, in order to couple the semiconductor chip and the semiconductor mounting substrate through the above-described Au wire, as shown in Figure 3, the surface of the semiconductor mounting substrate 30, the same as the above-described lead frame, Au wire ( A plating layer 30a is laminated to improve the bonding property with 40). As the plating laminated metal, a metal such as Ag or Au having excellent bonding properties is usually used.

그러나 이들 Ag 또는 Au 금속을 사용하여 반도체 실장기판의 표면을 도금 적층할 경우에 몇 가지 문제점이 나타나게 되는데, 먼저 도 4과 같이 Ag 금속재질의 도금층(30a-1)을 가진 반도체실장기판(30)을 사용할 경우에, Au 와이어와의 접합 특성은 우수하나 후속 공정에서 몰딩되는 EMC와의 결합특성이 나쁜 단점을 가지고 있다.However, when the surface of the semiconductor mounting substrate is plated and laminated using these Ag or Au metals, some problems appear. First, as shown in FIG. 4, the semiconductor mounting substrate 30 having the Ag metal plated layer 30a-1 is formed. In the case of using, the bonding property with the Au wire is excellent, but the bonding property with the EMC molded in a subsequent process has a disadvantage.

따라서 반도체 실장기판 위에 코팅되는 몰딩이 파손되거나 떨어져 나가는 현상이 빈번하게 발생하여 소자의 신뢰성을 해치는 문제점을 가지고 있는데, 이러한 문제를 해결하기 위하여 Au 와이어가 접합되는 부분인 내부 연결부분의 일부분에만 Ag 금속을 부분 도금하는 방법이 개발되기도 하였으나, 이는 부분도금을 위한 또 다른 장치를 필요로 하여 소자의 가격을 상승시키고 제조공정을 복잡하게 만든다.Therefore, the molding coated on the semiconductor mounting substrate is often damaged or dropped, which causes a problem of deteriorating the reliability of the device. In order to solve the problem, Ag metal is formed only in a part of the internal connection portion where the Au wire is bonded. Although a method of partial plating of the was developed, this requires another device for partial plating, which increases the price of the device and complicates the manufacturing process.

또한 Au 금속을 반도체 실장기판(30)의 전면 또는 부분에 도금할 경우에 Au 와이어와의 접합특성은 가장 우수하나, 이러한 Au 금속을 반도체 실장기판 상에 직접 도금할 경우에, Au 금속의 고유 특성인 다공성(porosity)에 의하여 Au 도금층(30a-2)의 내부에 다수의 세공(micro-hole)이 형성되는데, 이러한 세공은 구리, 철 등과 같이 실장기판을 이루는 금속물질이 표면에 확산되는 원인이 된다. 이를 방지하기 위하여 도 5와 같이 이러한 Au 도금층(30a-2)과 반도체 실장기판(30)의 사이에 Ni등의 장벽층(30a-3)을 더욱 개재하기도 하나, 이 역시 하지금속의 표면확산을 충분히 방지하지 못한다.In addition, when Au metal is plated on the entire surface or part of the semiconductor mounting substrate 30, the bonding property with Au wire is the best, but when the Au metal is directly plated on the semiconductor mounting substrate, the intrinsic properties of the Au metal are A large number of micro-holes are formed in the Au plating layer 30a-2 due to phosphorus porosity, which causes the metal material forming the mounting substrate, such as copper and iron, to diffuse to the surface. do. In order to prevent this, as shown in FIG. 5, a barrier layer 30a-3 such as Ni is further interposed between the Au plating layer 30a-2 and the semiconductor mounting substrate 30. Not enough to prevent

이러한 하지 금속, 즉 반도체 실장기판물질의 표면확산은 Au와이어와의 접합특성과, EMC와의 접합특성을 크게 해치게 되고, 이러한 표면확산을 방지하기 위해서는 Au 금속을 2500Å이상의 두께로 적층하여야 하나, 이는 고가의 금속인 Au를 다량 사용하게 되므로 소자의 가격상승을 야기하는 문제점이 있다.The surface diffusion of the base metal, ie, the semiconductor mounting substrate material, greatly degrades the bonding property with Au wire and the bonding property with EMC, and in order to prevent such surface diffusion, the Au metal should be laminated to a thickness of 2500Å or more, which is expensive. Since a large amount of Au is used, there is a problem of causing an increase in the price of the device.

본 발명은 상기와 같은 문제점을 해결하기 위한 것으로, 반도체실장기판의 표면에 Au 와이어와 가장 우수한 접합특성을 가지는 Au 금속을 포함하는 도금층을 얇게 적층하여 소자의 가격을 종래보다 저렴하게 하면서도, 하지 금속의 확산을 효과적으로 방지할 수 있는, 보다 개선된 도금층을 가지는 반도체 실장기판을 제공하는데 그 목적이 있다.The present invention is to solve the above problems, by laminating a thin layer of a plating layer containing Au metal having the most excellent bonding properties with the Au wire on the surface of the semiconductor mounting substrate, while lowering the price of the device than conventional, the base metal SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor mounting substrate having a more improved plating layer, which can effectively prevent diffusion of metal.

도 1은 일반적인 리드프레임을 반도체 실장기판으로 사용하는 반도체 패키지의 내부구조를 도시한 분해 사시도1 is an exploded perspective view showing the internal structure of a semiconductor package using a general lead frame as a semiconductor mounting substrate

도 2는 일반적인 반도체 실장기판의 하나인 리드프레임의 평면도2 is a plan view of a lead frame as one of general semiconductor mounting substrates;

도 3은 반도체 실장기판과 반도체 칩이 Au 와이어에 의해 결합된 구조를 도시한 단면도3 is a cross-sectional view showing a structure in which a semiconductor mounting substrate and a semiconductor chip are joined by Au wires;

도 4 및 도5 는 각각 Au 와이어가 접합되는 일반적인 반도체 실장기판의 적층 구조를 도시한 단면도4 and 5 are cross-sectional views showing a laminated structure of a general semiconductor mounting substrate to which Au wires are bonded, respectively.

도 6 내지 도 8은 각각 본 발명에 따른 반도체실장기판의 적층 구조를 도시한 단면도6 to 8 are cross-sectional views each showing a laminated structure of a semiconductor mounting substrate according to the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

30 : 반도체실장기판 100 : Au를 가진 접합층30: semiconductor mounting substrate 100: bonding layer with Au

110 : Ag를 포함하는 장벽층110: barrier layer containing Ag

본 발명은 상기와 같은 목적을 달성하기 위하여, 반도체 칩이 실장되고, 상기 반도체 칩과 Au 와이어를 통하여 전기적으로 연결되어, 외부회로와 상기 반도체 칩의 전기적 연결을 레이아웃하는 반도체 실장기판으로서,In order to achieve the above object, the present invention provides a semiconductor mounting substrate in which a semiconductor chip is mounted, electrically connected through the semiconductor chip and Au wire, and layouts electrical connection between an external circuit and the semiconductor chip.

상기 반도체 실장기판의 표면 최상층에 적층되어, 상기 Au 와이어와 접합되는, Au를 가진 접합층과; 상기 접합층과 반도체 실장기판의 표면사이에, 상기 접합층의 직 하단에 적층되어 하지금속의 표면확산을 방지하는 역할을 하는 Ag를 포함하는 장벽층을 포함하는 반도체 실장기판을 제공한다.여기서 Au를 가진 접합층은 Au를 조금이라도 포함하는 모든 합금을 의미하는 것이나, Au 와이어와의 접합특성을 고려하여 Au 성분 함량이 50% 이상인 것이 바람직하며, Au 성분함량이 증가할 수록 Au 와이어와의 접합특성도 좋아지게 된다.A bonding layer having Au, laminated on the top layer of the surface of the semiconductor mounting substrate and bonded to the Au wire; There is provided a semiconductor mounting substrate comprising a barrier layer comprising Ag between the bonding layer and the surface of the semiconductor mounting substrate, which is stacked directly below the bonding layer and serves to prevent surface diffusion of the underlying metal. The bonding layer having the term "a" means all alloys containing at least Au, but it is preferable that the Au content is 50% or more in consideration of the bonding properties with the Au wire, and the bonding with the Au wire increases as the Au content increases. The characteristics will also improve.

한편 상기 Ag를 포함하는 장벽층도 Ag를 조금이라도 포함하는 모든 합금을 의미하므로, Ag-백금 합금 또는 Ag-파라듐 합금 등 여러 종류의 합금을 예상할 수 있으나, 하지금속의 표면확산을 방지하기 위해서는 Ag 성분함량이 50% 이상인 것이 바람직하다. 후술하는 바와 같이 본 발명에서는 Ag를 포함하는 장벽층에 대해 3가지의 실시예를 설명하고 있으나, 이는 실시예일 뿐이므로 이와 같이 Ag를 포함하는 모든 합금도 본 발명에 포함됨은 물론이다.본 발명의 실시예에서는 상기 Ag를 포함하는 장벽층이 500Å 이상의 두께를 가지는 Ag 단원소로 이루어지거나, 500Å이하의 두께를 가지는 Ag-Au 또는 Au-Ag 합금으로 이루어지는 것을 특징으로 한다.On the other hand, since the barrier layer containing Ag also means all alloys containing even a small amount of Ag, various kinds of alloys such as Ag-platinum alloy or Ag-paradium alloy can be expected, but the surface diffusion of the underlying metal is prevented. In order to achieve this, the Ag component content is preferably 50% or more. As will be described later in the present invention, three embodiments of the barrier layer containing Ag have been described. However, this is only an example, and thus, all alloys containing Ag are also included in the present invention. In an embodiment, the barrier layer including Ag is made of Ag single element having a thickness of 500 GPa or more, or is made of Ag-Au or Au-Ag alloy having a thickness of 500 mPa or less.

또한 본 발명은 500Å이하의 두께를 가지며, 각각 수십 Å이하의 Ag 단원소 박막과, Au 단원소 박막이, 상기 순서로 2층 이상 반복하여 적층된 장벽층을 가지는 반도체 실장기판을 제공한다.The present invention also provides a semiconductor mounting substrate having a thickness of 500 mW or less, each having a tens of mW or less Ag single small film and an Au single small thin film having a barrier layer in which two or more layers are repeatedly stacked in the above order.

이하 본 발명에 따른 올바른 실시예를 첨부된 도면을 참조하여 상세히 설명한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명에 따른 반도체 실장기판은 도 6 내지 도 8에 도시된 것 처럼, Au 와이어 및 EMC등의 몰딩소재와의 접합특성의 개선을 위해서 반도체 실장기판(30)의 최상층, 즉 Au 와이어 및 몰딩소재가 접합되는 표면층에, 상술한 바와 같이 Au를 가진 접합층(100)을 500Å 이하의 두께로 적층하는 것을 특징으로 하는데, 이러한 Au를 가진 접합층(100)의 직하단에는 Ag금속을 포함하는 도금층이 적재되어 본 발명의 목적을 가능하게 한다.6 to 8, the semiconductor mounting substrate according to the present invention, in order to improve the bonding characteristics with the molding material such as Au wire and EMC, that is, the uppermost layer of the semiconductor mounting substrate 30, that is, Au wire and molding material To the surface layer to be bonded, as described above, the bonding layer 100 having Au is laminated to a thickness of 500 kPa or less, and the plating layer containing Ag metal is directly below the bonding layer 100 having Au. This is loaded to enable the object of the present invention.

이러한 Au를 가진 접합층(100)의 직하단에 도금 적층되는, Ag를 포함하는 도금층은 반도체 실장기판(30)을 이루는 하지금속의 표면확산을 방지하는 장벽층의 역할을 하게 되는데, 이러한 Ag를 포함하는 장벽층의 실시예를 설명하면 다음과 같다.The plating layer including Ag, which is plated and laminated at the lower end of the bonding layer 100 having Au, serves as a barrier layer for preventing the surface diffusion of the underlying metal constituting the semiconductor mounting substrate 30. An embodiment of a barrier layer including will be described below.

제 1실시예First embodiment

본 발명에 따른 제 1 실시예는 최상층에 도금 적층되는 Au를 가진 접합층(100)의 직하단에 Ag 단원소로 이루어진 Ag 장벽층이 도금 적층되는 것을 특징으로 하는데, 이러한 Au를 가진 접합층(100) 및 그 직하단에 Ag 단원소 장벽층(110)이 적층된 반도체 실장기판(30)의 단면구조가 도 6에 도시되어 있다.The first embodiment according to the present invention is characterized in that the Ag barrier layer made of Ag single element is plated and laminated at the lower end of the bonding layer 100 having Au deposited on the top layer. ) And a cross-sectional structure of the semiconductor mounting substrate 30 having the Ag single element barrier layer 110 stacked thereon is shown in FIG. 6.

이때 반도체 실장기판(30)의 최상층에 적층되는 Au를 가진 접합층(100)은 전술한 바와 같이 500Å이하의 두께를 가지며, 그 직하단에 적층되는 Ag 단원소 장벽층(110)은 500Å 이상의 두께를 가지는 것이 바람직하다.특히 이와 같이 최상단의 Au를 가진 접합층(100)과 그 직하단에 적층 도금된 500Å이상의 Ag 단원소 장벽층(110)이 적층된 구조를 가지는 반도체 실장기판(30)을 사용하여 반도체 패키지를 제조할 경우에, 제조 공정중에 포함되는 고온공정 즉, Au 와이어의 접합 공정 및 EMC등의 소재를 사용한 몰딩공정에 있어서 두 층의(100, 110) 경계면에서 자연스럽게 열적 이력에 의한 확산 현상이 발생한다.At this time, the bonding layer 100 having Au stacked on the uppermost layer of the semiconductor mounting substrate 30 has a thickness of 500 kPa or less as described above, and the Ag single element barrier layer 110 stacked on the lower end thereof has a thickness of 500 kPa or more. Particularly, the semiconductor mounting substrate 30 having the structure in which the bonding layer 100 having the uppermost Au and the Ag single element barrier layer 110 of 500 Å or more laminated on the lower end thereof is laminated is laminated. In the case of manufacturing a semiconductor package, the thermal history naturally occurs at the interface between the two layers (100, 110) in the high temperature process included in the manufacturing process, that is, the Au wire bonding process and the molding process using materials such as EMC. Diffusion occurs.

이를 통하여 표면의 Au를 가진 접합층(100)과 그 직하단의 Ag 단원소 장벽층(110)의 경계에는 얇은 Au-Ag 또는 Ag-Au 합금층이 형성되고, 이러한 Au-Ag 또는 Ag-Au 합금층은 매우 안정한 금속이므로 반도체 실장기판(30)을 이루는 하지금속의 확산현상을 더욱 방지할 수 있는 효과를 가져온다.As a result, a thin Au-Ag or Ag-Au alloy layer is formed at the boundary between the bonding layer 100 having the surface Au and the Ag single element barrier layer 110 directly below the Au-Ag or Ag-Au layer. Since the alloy layer is a very stable metal, it brings about an effect that can further prevent the diffusion phenomenon of the base metal of the semiconductor mounting substrate 30.

제 2 실시예Second embodiment

본 발명에 따른 제 2 실시예는 최상층에 도금 적층되는 Au를 가진 접합층(100)의 직 하단에 Ag 단원소로 이루어진 Ag 도금층과, Au 단원소로 이루어진 Au 도금층이 순차적을 반복하여 적층되어 장벽층을 이루고 있는 것을 특징으로 하는데, 이러한 구성을 가지는 반도체 실장기판의 단면구조를 도 7에 도시하였다.According to the second embodiment of the present invention, an Ag plating layer made of Ag single element and an Au plated layer made of Au single element are sequentially and repeatedly stacked at the bottom of the bonding layer 100 having Au plated and stacked on the uppermost layer to form a barrier layer. A cross-sectional structure of a semiconductor mounting substrate having such a configuration is shown in FIG. 7.

이에 따르면 반도체 실장기판(30)의 최상층에, 전술한 바와 같이 500Å이하의 두께를 가지는 Au를 가진 접합층(100)이 적층되고, 이러한 Au 접합층(100)의 직하단에 Ag 단원소 도금층(112a)과, Au 단원소 도금층(112b)이 상기 순서로 2층 이상 반복하여 적층됨으로써, 장벽층(112)을 구성하게 되는데, 이때 장벽층(112)의 두께는 500Å 이하로 하는 것이 바람직하다. 이는 위와 같은 적층구조를 통해 하지금속의 확산이 대부분 제어되기 때문이다.As a result, a bonding layer 100 having Au having a thickness of 500 GPa or less is laminated on the uppermost layer of the semiconductor mounting substrate 30, and an Ag single-small plating layer (directly below the Au bonding layer 100) is laminated. 112a) and the Au single-small plating layer 112b are repeatedly laminated in the above order to form the barrier layer 112, and the thickness of the barrier layer 112 is preferably 500 Pa or less. This is because most of the base metal diffusion is controlled through the laminated structure as described above.

또한 후속되는 와이어본딩 및 EMC 몰딩 등과 같은 고온공정에서 장벽층(112)을 이루는 각각의 Ag 단원소층(112a) 및 Au 단원소층(112b)의 경계면과, 이러한 장벽층(112)과 최 상단의 Au를 가진 접합층(100)의 경계면에서 각각 Au-Ag 또는 Ag-Au 합금을 이루게 되어, 전술한 바와 같이 500Å이하의 두께로 장벽층(112)이 적층되어도, 반도체 실장기판(30)을 이루는 하지금속의 확산이 충분히 제어되는 효과를 가지게 된다.In addition, the interface between the respective Ag single layer 112a and Au single layer 112b forming the barrier layer 112 in a high temperature process such as wire bonding and EMC molding, and the barrier layer 112 and the top Au The Au-Ag or Ag-Au alloy is formed at the interface of the bonding layer 100 having the same, and as described above, even when the barrier layer 112 is laminated to a thickness of 500 kPa or less, the semiconductor mounting substrate 30 may not be formed. The diffusion of the metal is sufficiently controlled.

이때 장벽층(112)을 구성하는 Ag 또는 Au 단원소 도금층(112a, 112b)은 각각 수십 Å이하의 두께를 가지는 것이 바람직하다.At this time, it is preferable that the Ag or Au single-small plating layers 112a and 112b constituting the barrier layer 112 have a thickness of several tens of Pa or less, respectively.

제 3 실시예Third embodiment

본 발명에 따른 제 3 실시예는 최상층에 도금 적층되는 500Å 이하의 두께를 가지는 Au를 가진 접합층의 직 하단에, Ag- Au 또는 Au-Ag 합금으로 이루어진 장벽층이 도금 적층되는 것을 특징으로 하는데, 이러한 Au를 가진 접합층(100)과, 그 직하단의 Ag-Au 또는 Au-Ag 합금 장벽층이 적층된 반도체 실장기판의 단면은 도 8 에 도시되어 있다.A third embodiment according to the present invention is characterized in that a barrier layer made of Ag-Au or Au-Ag alloy is plated and laminated at the lower end of a bonding layer having Au having a thickness of 500 m or less, which is plated and laminated on the top layer. 8 is a cross-sectional view of a semiconductor mounting substrate in which a bonding layer 100 having Au and an Ag-Au or Au-Ag alloy barrier layer directly below it are stacked.

이에 따르면 반도체 실장기판의 최상층에, 전술한 바와 같이 500Å이하의 두께를 가지는 Au를 가진 접합층(100)이 적층되고, 그 직 하단에는 Ag-Au 또는 Au-Ag 합금으로 이루어진 장벽층(114)이 적층되어 반도체 실장기판(30)을 이루는 하지금속의 Au를 가진 접합층(100) 표면으로의 확산을 막는 장벽의 역할을 하게된다.여기서 Ag-Au 또는 Au-Ag 합금도 역시 Ag를 조금이라도 포함하는 경우를 의미하며, 하지금속의 표면확산방지를 위해서는 Ag의 성분함량이 50% 이상인 것이 바람직하다.According to this, a bonding layer 100 having Au having a thickness of 500 kPa or less is laminated on the uppermost layer of the semiconductor mounting substrate, and a barrier layer 114 made of an Ag-Au or Au-Ag alloy is disposed directly below. The stacked layer serves as a barrier to prevent the diffusion of the underlying metal Au to the surface of the bonding layer 100 having Au. The Ag-Au or Au-Ag alloy may also contain a small amount of Ag. Means to include, it is preferable that the Ag content of 50% or more in order to prevent the surface diffusion of the underlying metal.

이때 바람직하게는 Au-Ag 또는 Ag-Au 합금층(114)은 500Å이하의 두께를 가지는데, 이는 Au-Ag 또는 Ag-Au 합금은 매우 안정한 합금이므로 500Å이하의 두께로 적층하여도 반도체 실장기판(30)을 이루는 하지금속의 확산은 충분히 제어되기 때문이다.At this time, preferably, the Au-Ag or Ag-Au alloy layer 114 has a thickness of 500 kW or less. This is because the Au-Ag or Ag-Au alloy is a very stable alloy. This is because the diffusion of the base metal constituting (30) is sufficiently controlled.

이상에서 설명한, 본 발명에 따른 반도체 실장기판의 도금구조에 있어서 최상층의 Au를 가진 접합층 및 그 직하단의 Ag 금속을 포함하는 장벽층과, 반도체 실장기판의 사이에는 목적에 따라 Ni등의 금속으로 이루어진 보조장벽층이 더욱 포함되어, 하지금속의 확산을 방지하는 보조 장벽층의 역할을 할 수 있음은 당업자에게는 자명한 사실이다.In the plating structure of the semiconductor mounting substrate according to the present invention described above, a barrier layer including the bonding layer having Au at the uppermost layer and Ag metal at the lower end thereof, and a metal such as Ni, depending on the purpose, between the semiconductor mounting substrate It is apparent to those skilled in the art that the auxiliary barrier layer is further comprised, and may serve as an auxiliary barrier layer to prevent the diffusion of the base metal.

또한 본 발명에 따른 반도체 실장기판은, 반도체 칩 Au 와이어를 통하여 전기적으로 연결되는 구성을 가지는 모든 반도체 실장기판 즉, 리드프레임, BGA, PGA, Tape-BGA등에 적용되는 것이 가능하다.In addition, the semiconductor mounting substrate according to the present invention can be applied to all semiconductor mounting substrates having a configuration electrically connected through the semiconductor chip Au wire, that is, lead frame, BGA, PGA, Tape-BGA.

본 발명은 반도체 칩이 실장되고, Au 와이어를 통하여 이와 전기적으로 연결되는, 외부회로와 반도체 기판의 전기적 연결을 레이아웃하는 반도체 실장기판에 있어서, 최상층에 Au 와이어와 접합되는, 바람직하게는 500Å 이하의 두께를 가지는 Au를 가진 접합층과, 이러한 Au를 가진 접합층의 직 하단에 Ag를 포함하는 장벽층이 적층된 구조를 제공함으로써, 보다 개선된 반도체 패키지의 구성을 가능하게 한다.The present invention provides a semiconductor mounting substrate in which a semiconductor chip is mounted and is electrically connected thereto through an Au wire. The semiconductor mounting substrate layouts electrical connection between an external circuit and a semiconductor substrate. By providing a structure in which a bonding layer having Au having a thickness and a barrier layer including Ag are stacked directly below the bonding layer having Au, the structure of the semiconductor package can be improved.

즉, Ag를 포함하는 장벽층을 통하여 실장기판을 이루는 하지금속의 확산현상은 효과적으로 제어되며, 최상층에 도금 적층되는 Au를 가진 접합층에 의하여 Au 와이어와의 접합 특성 및 EMC 와의 접합 특성을 우수하게 할 수 있음은 물론, 그 두께에 있어서, 바람직하게는 500Å이하의 두께를 가지고 있으므로 소자의 가격 면에서 유리한 장점을 가지게 된다.That is, the diffusion phenomenon of the underlying metal constituting the mounting substrate through the barrier layer containing Ag is effectively controlled, and the bonding property with Au wire and the bonding property with EMC are excellent by the bonding layer having Au deposited on the top layer. Of course, in terms of the thickness, the thickness is preferably 500 kPa or less, which is advantageous in terms of the cost of the device.

특히 본 발명에 따른 도금 적층구조는 Au 와이어를 사용하여 반도체 칩과 전기적으로 연결되는 모든 종류의 반도체 실장기판에 적용 가능한 장점을 가지고 있다.In particular, the plated laminate structure according to the present invention has an advantage that can be applied to all kinds of semiconductor mounting substrate that is electrically connected to the semiconductor chip using Au wire.

Claims (8)

반도체 칩이 실장되고, 상기 반도체 칩과 Au 와이어를 통하여 전기적으로 연결되어, 외부회로와 상기 반도체 칩의 전기적 연결을 레이아웃하는 반도체 실장기판으로서,A semiconductor mounting board is mounted and electrically connected to the semiconductor chip through the Au wire, the semiconductor mounting substrate for laying out the electrical connection between the external circuit and the semiconductor chip, 상기 반도체 실장기판의 표면 최상층에 적층되어, 상기 Au 와이어와 접합되는, Au를 가진 접합층과;A bonding layer having Au, laminated on the top layer of the surface of the semiconductor mounting substrate and bonded to the Au wire; 상기 접합층과 반도체 실장기판의 표면사이에, 상기 접합층의 직 하단에 적층되어 하지금속의 표면확산을 방지하는 역할을 하는 Ag를 포함하는 장벽층Barrier layer including Ag between the bonding layer and the surface of the semiconductor mounting substrate, which is laminated directly below the bonding layer to prevent surface diffusion of the underlying metal 을 포함하는 반도체 실장기판Semiconductor mounting substrate comprising a 제1항에 있어서,The method of claim 1, 상기 Au를 가진 접합층의 성분은 Au가 50% 이상인 반도체 실장기판A component of the bonding layer having Au is a semiconductor mounting substrate having Au of 50% or more. 제1항에 있어서,The method of claim 1, 상기 Ag를 포함하는 장벽층의 성분은 Ag가 50% 이상인 반도체 실장기판The barrier layer including Ag is a semiconductor mounting substrate having Ag of 50% or more. 제1항에 있어서,The method of claim 1, 상기 Ag를 포함하는 장벽층은 500Å 이상의 두께를 가지는 Ag 단원소로 이루어진 반도체 실장기판The barrier layer including Ag is a semiconductor mounting substrate made of Ag single element having a thickness of 500 GPa or more. 제1항에 있어서,The method of claim 1, 상기 Ag를 포함하는 장벽층은 500Å이하의 두께를 가지며, 각각 수십 Å이하의 Ag 단원소 박막과, Au 단원소 박막이, 상기 순서로 2층 이상 반복하여 적층된 반도체 실장기판The barrier layer including Ag has a thickness of 500 mV or less, and each of the ten tens of mW or smaller Ag single thin films and the Au single small thin films are repeatedly stacked in two or more layers in this order. 제1항에 있어서,The method of claim 1, 상기 Ag를 포함하는 장벽층은 500Å이하의 두께를 가지며, Ag-Au 또는 Au-Ag 합금으로 이루어진 반도체 실장기판The barrier layer including Ag has a thickness of 500 GPa or less, and is a semiconductor mounting substrate made of Ag-Au or Au-Ag alloy. 제6항에 있어서,The method of claim 6, 상기 Ag-Au 또는 Au-Ag 합금 중 Ag성분이 50% 이상인 반도체 실장기판Semiconductor mounting substrate having Ag of 50% or more in the Ag-Au or Au-Ag alloy 제1항 내지 제7항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 7, 상기 Au를 가진 접합층과 상기 Ag를 포함하는 장벽층 사이, 또는 상기 Ag를 포함하는 장벽층과 상기 반도체 실장기판 표면 사이에는 Ni을 포함하는 보조장벽층이 적층된 반도체 실장기판A semiconductor mounting substrate having an auxiliary barrier layer including Ni stacked between the bonding layer having Au and the barrier layer including Ag, or between the barrier layer containing Ag and the surface of the semiconductor mounting substrate.
KR10-2001-0012042A 2001-03-08 2001-03-08 semiconductor installed board using Au wire connection KR100427827B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR10-2001-0012042A KR100427827B1 (en) 2001-03-08 2001-03-08 semiconductor installed board using Au wire connection

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-2001-0012042A KR100427827B1 (en) 2001-03-08 2001-03-08 semiconductor installed board using Au wire connection

Publications (2)

Publication Number Publication Date
KR20020072069A KR20020072069A (en) 2002-09-14
KR100427827B1 true KR100427827B1 (en) 2004-04-27

Family

ID=27696822

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2001-0012042A KR100427827B1 (en) 2001-03-08 2001-03-08 semiconductor installed board using Au wire connection

Country Status (1)

Country Link
KR (1) KR100427827B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100801444B1 (en) * 2006-05-30 2008-02-11 엠케이전자 주식회사 Au-Ag based alloy wire for a semiconductor package
KR20090109289A (en) * 2008-04-15 2009-10-20 이규한 Semiconductor installed board for csp(chip scale package)

Also Published As

Publication number Publication date
KR20020072069A (en) 2002-09-14

Similar Documents

Publication Publication Date Title
US7501696B2 (en) Semiconductor chip-embedded substrate and method of manufacturing same
JP3546131B2 (en) Semiconductor chip package
US6876074B2 (en) Stack package using flexible double wiring substrate
US7242081B1 (en) Stacked package structure
US6551854B2 (en) Semiconductor device having bump electrodes and method of manufacturing the same
US5882955A (en) Leadframe for integrated circuit package and method of manufacturing the same
US20060055018A1 (en) Semiconductor device
US20070023910A1 (en) Dual BGA alloy structure for improved board-level reliability performance
US5994767A (en) Leadframe for integrated circuit package and method of manufacturing the same
US20090133904A1 (en) Module and manufacturing method thereof
CN111933590B (en) Packaging structure and manufacturing method thereof
US6596620B2 (en) BGA substrate via structure
CN101364586B (en) Construction for packaging substrate
US20080142945A1 (en) Semiconductor package with redistribution layer of semiconductor chip directly contacted with substrate and method of fabricating the same
US6855573B2 (en) Integrated circuit package and manufacturing method therefor with unique interconnector
US7884465B2 (en) Semiconductor package with passive elements embedded within a semiconductor chip
KR100427827B1 (en) semiconductor installed board using Au wire connection
JPH09232506A (en) Semiconductor device and manufacturing method thereof
KR20010063236A (en) Stack package and manufacturing method thereof
US7547974B2 (en) Wiring substrate with improvement in tensile strength of traces
JP2722451B2 (en) Semiconductor device
JP2005150771A (en) Wiring board, semiconductor device, and package stacks semiconductor device
KR100401497B1 (en) Stack type Multi Chip Package and Manufacture Method the same
KR20050006547A (en) PCB for fabricating semiconductor package and semiconductor package using the same
US20050082658A1 (en) Simplified stacked chip assemblies

Legal Events

Date Code Title Description
A201 Request for examination
A302 Request for accelerated examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee