JPH04312937A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor deviceInfo
- Publication number
- JPH04312937A JPH04312937A JP3060653A JP6065391A JPH04312937A JP H04312937 A JPH04312937 A JP H04312937A JP 3060653 A JP3060653 A JP 3060653A JP 6065391 A JP6065391 A JP 6065391A JP H04312937 A JPH04312937 A JP H04312937A
- Authority
- JP
- Japan
- Prior art keywords
- plating layer
- semiconductor device
- copper
- nickel plating
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 238000007747 plating Methods 0.000 claims abstract description 78
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 44
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 23
- 229910000679 solder Inorganic materials 0.000 claims abstract description 20
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052802 copper Inorganic materials 0.000 claims abstract description 17
- 239000010949 copper Substances 0.000 claims abstract description 17
- 239000011889 copper foil Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 12
- 229910052763 palladium Inorganic materials 0.000 claims abstract description 9
- 239000011347 resin Substances 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 abstract description 11
- 239000000956 alloy Substances 0.000 abstract description 11
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical class [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229910001295 No alloy Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002815 nickel Chemical class 0.000 description 2
- 229910000978 Pb alloy Inorganic materials 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 230000006355 external stress Effects 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 229910001174 tin-lead alloy Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3473—Plating of solder
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、樹脂モールドされたＩ
Ｃチップから引き出された外部リードを有する半導体装
置の製造方法に係り、特には、フィルムキャリア（ＴＡ
Ｂ）方式に基づいてパッケージ化された半導体装置の外
部リードのめっき処理技術の改善に関する。[Industrial Application Field] The present invention provides resin-molded I
It relates to a method of manufacturing a semiconductor device having external leads drawn out from a C chip, and in particular, it relates to a method of manufacturing a semiconductor device having external leads drawn out from a C chip.
B) relates to improvements in plating technology for external leads of semiconductor devices packaged based on the method.
【０００２】0002
【従来の技術】図２は、フィルムキャリア（ＴＡＢ）方
式に基づいてパッケージ化された半導体装置をプリント
基板に実装した状態を示す断面図である。同図において
、１はＴＡＢパッケージされた半導体装置、２はプリン
ト基板、３はＩＣチップ、４は樹脂モールド、５は外部
リード、６はＩＣチップ３と外部リード５とを接続する
ためのバンプ、７は外部リード５と接続するためにプリ
ント基板２上に形成された導体である。2. Description of the Related Art FIG. 2 is a sectional view showing a state in which a semiconductor device packaged based on the film carrier (TAB) method is mounted on a printed circuit board. In the figure, 1 is a TAB packaged semiconductor device, 2 is a printed circuit board, 3 is an IC chip, 4 is a resin mold, 5 is an external lead, 6 is a bump for connecting the IC chip 3 and the external lead 5, 7 is a conductor formed on the printed circuit board 2 for connection to the external lead 5.
【０００３】上記の構成において、外部リード５は電気
伝導性に優れ、かつ、プリント基板２上の導体７に十分
な密着性を保って接続される必要があるので、従来は、
図３（ａ）に示すように、銅箔１０の上にはんだ（錫−
鉛合金）めっき層１２を直接形成する製造方法が採られ
ている。In the above configuration, the external lead 5 must have excellent electrical conductivity and must be connected to the conductor 7 on the printed circuit board 2 with sufficient adhesion.
As shown in FIG. 3(a), solder (tin-
A manufacturing method is adopted in which the plating layer 12 (lead alloy) is directly formed.
【０００４】0004
【発明が解決しようとする課題】しかしながら、従来の
ように、銅箔１０の上にはんだめっき層１２を直接形成
すると、たとえ室内に放置した状態においても、時間経
過に伴って、いわゆるカーケンドール効果による相互拡
散が起こり、その結果、図３（ｂ）に示すように、銅箔
１０とはんだめっき層１２との間に合金層１４が形成さ
れる。[Problems to be Solved by the Invention] However, when the solder plating layer 12 is directly formed on the copper foil 10 as in the past, even if it is left indoors, the so-called Kirkendall effect occurs over time. As a result, an alloy layer 14 is formed between the copper foil 10 and the solder plating layer 12, as shown in FIG. 3(b).
【０００５】この合金層１４は、銅−錫からなる金属間
化合物であって、硬くて脆い。しかも、長時間の内には
、相互拡散により銅箔１０を含めて外部リード５の全て
が合金化してしまう。たとえば、めっき直後（図３（ａ
）の状態）における外部リード５の全体の厚さを４０μ
ｍ、銅箔１０の厚さを２０μｍとすると、最終的には４
０μｍの合金層１４が形成される。[0005] This alloy layer 14 is an intermetallic compound consisting of copper and tin, and is hard and brittle. Moreover, over a long period of time, all of the external leads 5 including the copper foil 10 become alloyed due to mutual diffusion. For example, immediately after plating (Fig. 3(a)
) The total thickness of the external lead 5 in the state of ) is 40 μm.
m, and if the thickness of the copper foil 10 is 20 μm, the final thickness is 4
An alloy layer 14 of 0 μm is formed.
【０００６】このため、半導体装置１の搬送時やプリン
ト基板２に実装する際のハンドリング時において、この
外部リード５に外部応力が加わると、合金層１４からク
ラックが入り、外部リード５が破断したり、電気抵抗が
増加するなどの不具合を生じていた。Therefore, if external stress is applied to the external leads 5 during transportation of the semiconductor device 1 or handling when mounting it on the printed circuit board 2, cracks will appear in the alloy layer 14 and the external leads 5 will break. This caused problems such as increased electrical resistance.
【０００７】[0007]
【課題を解決するための手段】本発明は、上述した課題
を解決するためになされたものであって、外部リードの
めっき処理に伴う合金層の成長を抑制し、外部リードの
破断や電気抵抗の増加などの不具合発生を回避するよう
にするものである。[Means for Solving the Problems] The present invention has been made to solve the above-mentioned problems, and suppresses the growth of the alloy layer accompanying the plating process of the external leads, and prevents breakage of the external leads and electrical resistance. This is to avoid problems such as an increase in
【０００８】そのため、第１発明に係る半導体装置の製
造方法では、銅箔の上にニッケルめっき層を、さらに、
このニッケルめっき層の上にはんだめっき層を順次形成
して外部リードを作成するようにしている。Therefore, in the method for manufacturing a semiconductor device according to the first invention, a nickel plating layer is further provided on the copper foil, and
External leads are created by sequentially forming solder plating layers on this nickel plating layer.
【０００９】第２発明に係る半導体装置の製造方法では
、ニッケルめっき層の形成後、はんだめっき層の形成前
に、銅めっき層を形成するようにしている。In the method for manufacturing a semiconductor device according to the second aspect of the invention, a copper plating layer is formed after forming a nickel plating layer and before forming a solder plating layer.
【００１０】第３発明に係る半導体装置の製造方法では
、第１、第２発明におけるニッケルめっき層の形成に代
えて、パラジウムめっき層を形成するようにしている。In the method for manufacturing a semiconductor device according to the third invention, a palladium plating layer is formed instead of forming the nickel plating layer in the first and second inventions.
【００１１】[0011]
【作用】はんだめっき層の下層にニッケルめっき層ある
いはパラジウムめっき層が形成されているので、銅箔中
の銅とはんだめっき層中の錫との相互拡散による合金層
の成長が抑制される。そのため、銅箔の細りがなく、機
械的強度および電気抵抗も良好なものとなる。[Operation] Since the nickel plating layer or the palladium plating layer is formed below the solder plating layer, the growth of the alloy layer due to mutual diffusion between the copper in the copper foil and the tin in the solder plating layer is suppressed. Therefore, the copper foil does not become thinner and has good mechanical strength and electrical resistance.
【００１２】さらに、ニッケルめっき層あるいはパラジ
ウムめっき層の上に銅めっき層を形成するようにすれば
、次のはんだめっき層を形成する際の密着性が改善され
、はんだめっき層の剥離等もなくすことができる。Furthermore, if a copper plating layer is formed on the nickel plating layer or the palladium plating layer, the adhesion when forming the next solder plating layer is improved, and peeling of the solder plating layer is also eliminated. be able to.
【００１３】[0013]
【実施例】図１は本発明の製造方法に係る半導体装置の
外部リードの断面図であり、図３に対応する部分には同
一の符号を付す。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view of an external lead of a semiconductor device according to the manufacturing method of the present invention, and parts corresponding to those in FIG. 3 are given the same reference numerals.
【００１４】この半導体装置の製造方法では、図１（ａ
）に示すように、外部リード５の作成に際して、銅箔１
０の上にニッケルめっき層１６をたとえば０．１〜１．
５μｍ程度の厚さに形成する。次に、このニッケルめっ
き層１６の上に銅めっき層１８をたとえば０．５〜５μ
ｍ程度の厚さに形成する。さらに、この銅めっき層１８
の上にはんだ（錫−鉛合金）めっき層１２をたとえば１
０μｍ程度の厚さに形成する。In this method of manufacturing a semiconductor device, FIG.
), when creating the external leads 5, the copper foil 1
For example, a nickel plating layer 16 of 0.1-1.
It is formed to a thickness of about 5 μm. Next, on this nickel plating layer 16, a copper plating layer 18 is applied, for example, 0.5 to 5 μm.
It is formed to a thickness of about m. Furthermore, this copper plating layer 18
For example, a solder (tin-lead alloy) plating layer 12 is placed on top of the
It is formed to a thickness of about 0 μm.
【００１５】上記のめっき処理をした後にこれを室内に
放置した場合、図１（ｂ）に示すように、銅箔１０とニ
ッケルめっき層１６との間では、殆ど合金層は形成され
ず（合金層の厚さは数Å程度で無視できる）、ニッケル
めっき層１６がそのまま残存する。また、銅めっき層１
８とはんだめっき層１２との間では、銅と錫の相互拡散
により銅−錫合金層２２が形成されるが、銅めっき層１
６は最初から薄肉に形成されているから、銅−錫合金層
２２も薄肉のものとなる。また、ニッケルめっき層１６
と銅めっき層１８との間では殆ど合金層は形成されない
。When the plating is left indoors after the above plating treatment, almost no alloy layer is formed between the copper foil 10 and the nickel plating layer 16, as shown in FIG. 1(b). (The thickness of the layer is approximately several angstroms and can be ignored), and the nickel plating layer 16 remains as it is. In addition, copper plating layer 1
A copper-tin alloy layer 22 is formed between copper plating layer 1 and solder plating layer 12 by mutual diffusion of copper and tin.
Since the copper-tin alloy layer 6 is formed thin from the beginning, the copper-tin alloy layer 22 is also thin. In addition, the nickel plating layer 16
Almost no alloy layer is formed between the copper plating layer 18 and the copper plating layer 18.
【００１６】したがって、めっき直後（図１（ａ）の状
態）における外部リード５の全体の厚さを４０μｍ、銅
めっき層１８の厚が０．５〜５μｍ程度とした場合には
、銅−錫合金層２２の厚さも最大でも５μｍ程度となり
、外部リード５の全体の厚さに比べて薄肉であるため、
クラックは発生しない。Therefore, if the total thickness of the external lead 5 immediately after plating (the state shown in FIG. 1(a)) is 40 μm, and the thickness of the copper plating layer 18 is approximately 0.5 to 5 μm, the copper-tin The thickness of the alloy layer 22 is also approximately 5 μm at maximum, which is thinner than the overall thickness of the external lead 5.
No cracks occur.
【００１７】なお、上記の実施例においては、ニッケル
めっき層１６の上に銅めっき層１８を形成するので、次
のはんだめっき層１２を形成する際の密着性が改善され
、はんだめっき層１２の剥離等もなくすことができる。In the above embodiment, since the copper plating layer 18 is formed on the nickel plating layer 16, the adhesion when forming the next solder plating layer 12 is improved, and the solder plating layer 12 is Peeling etc. can also be eliminated.
【００１８】さらに、上記の実施例のニッケルめっき層
１６に代えてパラジウムめっき層をたとえば０．０５〜
１．５μｍ程度の厚さに形成しても、上記と同様の効果
が得られる。Furthermore, in place of the nickel plating layer 16 in the above embodiment, a palladium plating layer of, for example, 0.05 to
Even if it is formed to a thickness of about 1.5 μm, the same effect as above can be obtained.
【００１９】[0019]
【発明の効果】本発明によれば、外部リードのめっき処
理に伴う合金層の成長が抑制されるので、外部リードの
破断や電気抵抗の増加などの不具合発生が回避される。According to the present invention, since the growth of the alloy layer accompanying the plating process of the external leads is suppressed, problems such as breakage of the external leads and increase in electrical resistance are avoided.
【００２０】特に、ニッケルめっき層あるいはパラジウ
ムめっき層の上に直接にはんだめっき層を形成するので
なく、両者の間に銅めっき層を形成するようにすれば、
はんだめっき層の密着性が改善され、はんだめっき層の
剥離等の発生も有効に防止することができる。In particular, if a copper plating layer is formed between the nickel plating layer or the palladium plating layer, instead of forming the solder plating layer directly on the nickel plating layer or the palladium plating layer,
The adhesion of the solder plating layer is improved, and peeling of the solder plating layer can be effectively prevented.
【図１】本発明の製造方法に係る半導体装置の外部リー
ドの断面図で、図１（ａ）はめっき処理した直後の状態
、図１（ｂ）はめっき処理後の経時変化により合金層が
形成された状態をそれぞれ示す。FIG. 1 is a cross-sectional view of an external lead of a semiconductor device according to the manufacturing method of the present invention, in which FIG. 1(a) shows the state immediately after plating, and FIG. 1(b) shows the state where the alloy layer has changed over time after plating. The formed states are shown respectively.
【図２】半導体装置をプリント基板に実装した状態を示
す断面図である。FIG. 2 is a cross-sectional view showing a semiconductor device mounted on a printed circuit board.
【図３】従来の製造方法に係る半導体装置の外部リード
の断面図で、図３（ａ）はめっき処理した直後の状態、
図３（ｂ）はめっき処理後の経時変化により合金層が形
成された状態をそれぞれ示す。FIG. 3 is a cross-sectional view of an external lead of a semiconductor device according to a conventional manufacturing method, and FIG. 3(a) shows a state immediately after plating;
FIG. 3(b) shows a state in which an alloy layer is formed due to changes over time after the plating process.
１…半導体装置、３…ＩＣチップ、４…樹脂モールド、
５…外部リード、１０…銅箔、１２…はんだめっき層、
１６…ニッケルめっき層（パラジウムめっき層）、１８
…銅めっき層。1... Semiconductor device, 3... IC chip, 4... Resin mold,
5... External lead, 10... Copper foil, 12... Solder plating layer,
16...Nickel plating layer (palladium plating layer), 18
...Copper plating layer.
Claims (3)
もに、このＩＣチップをプリント基板等に電気的に接続
するための外部リードが前記樹脂モールドから引き出さ
れているフィルムキャリア（ＴＡＢ）方式に基づいてパ
ッケージ化された半導体装置の製造方法であって、前記
外部リードは、銅箔の上にニッケルめっき層を、さらに
、このニッケルめっき層の上にはんだめっき層を順次形
成して構成することを特徴とする半導体装置の製造方法
。1. A package based on a film carrier (TAB) method in which an IC chip is molded in a resin and external leads for electrically connecting the IC chip to a printed circuit board or the like are drawn out from the resin mold. A method of manufacturing a semiconductor device according to the present invention, wherein the external lead is formed by sequentially forming a nickel plating layer on a copper foil, and further forming a solder plating layer on the nickel plating layer. A method for manufacturing a semiconductor device.
において、ニッケルめっき層の形成後、はんだめっき層
の形成前に、銅めっき層を形成することを特徴とする半
導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein a copper plating layer is formed after forming the nickel plating layer and before forming the solder plating layer.
記載の半導体装置の製造方法において、ニッケルめっき
層の形成に代えて、パラジウムめっき層を形成すること
を特徴とする半導体装置の製造方法。3. The method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that a palladium plating layer is formed instead of forming a nickel plating layer. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3060653A JP2526434B2 (en) | 1991-03-26 | 1991-03-26 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3060653A JP2526434B2 (en) | 1991-03-26 | 1991-03-26 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04312937A true JPH04312937A (en) | 1992-11-04 |
| JP2526434B2 JP2526434B2 (en) | 1996-08-21 |
Family
ID=13148513
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3060653A Expired - Lifetime JP2526434B2 (en) | 1991-03-26 | 1991-03-26 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2526434B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1995018464A1 (en) * | 1993-12-27 | 1995-07-06 | National Semiconductor Corporation | Protective coating combination for lead frames |
| US5650661A (en) * | 1993-12-27 | 1997-07-22 | National Semiconductor Corporation | Protective coating combination for lead frames |
| US5728285A (en) * | 1993-12-27 | 1998-03-17 | National Semiconductor Corporation | Protective coating combination for lead frames |
| JP2021044468A (en) * | 2019-09-13 | 2021-03-18 | シチズンファインデバイス株式会社 | Submount |
-
1991
- 1991-03-26 JP JP3060653A patent/JP2526434B2/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1995018464A1 (en) * | 1993-12-27 | 1995-07-06 | National Semiconductor Corporation | Protective coating combination for lead frames |
| US5436082A (en) * | 1993-12-27 | 1995-07-25 | National Semiconductor Corporation | Protective coating combination for lead frames |
| US5650661A (en) * | 1993-12-27 | 1997-07-22 | National Semiconductor Corporation | Protective coating combination for lead frames |
| US5728285A (en) * | 1993-12-27 | 1998-03-17 | National Semiconductor Corporation | Protective coating combination for lead frames |
| JP2021044468A (en) * | 2019-09-13 | 2021-03-18 | シチズンファインデバイス株式会社 | Submount |
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| Publication number | Publication date |
|---|---|
| JP2526434B2 (en) | 1996-08-21 |
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