JPS6129142B2 - - Google Patents

Info

Publication number
JPS6129142B2
JPS6129142B2 JP55185930A JP18593080A JPS6129142B2 JP S6129142 B2 JPS6129142 B2 JP S6129142B2 JP 55185930 A JP55185930 A JP 55185930A JP 18593080 A JP18593080 A JP 18593080A JP S6129142 B2 JPS6129142 B2 JP S6129142B2
Authority
JP
Japan
Prior art keywords
layer
gold
semiconductor element
lead frame
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55185930A
Other languages
Japanese (ja)
Other versions
JPS57109347A (en
Inventor
Yoshio Ito
Mitsuo Kobayashi
Toshio Tetsuya
Osamu Usuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP55185930A priority Critical patent/JPS57109347A/en
Publication of JPS57109347A publication Critical patent/JPS57109347A/en
Publication of JPS6129142B2 publication Critical patent/JPS6129142B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To improve mounting performance by a method wherein on a substrate for element arrangement consisting of copper or copper alloy, a semiconductor element which is formed by lamination of a barrier metal layer and an alloy layer which has gold or the like as a pricipal component is mounted. CONSTITUTION:After a bipolar silicon semiconductor element 104 which is formed by lamination of a vanadium layer 105, a nickel layer 106, a gold and germanium alloy layer and a gold layer, is laminated on an island region 102 of a lead frame consisting of single element of copper or copper alloy, it is mounted by heating and pressing, and a junction layer 109 consisting of full solid solution of Au-Ge-Cu is formed. Accordingly, because of a junction with intermediaries of a barrier metal layer consisting of layers 105, 106 and a junction layer 109 which does not contain silicon, firm mounting can be attained.

Description

【発明の詳細な説明】 本発明は半導体装置に関し、特に半導体素子の
マウント部及びこれがマウントされる素子配設基
材の構造を改良した半導体装置に係る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which the structure of a mounting portion for a semiconductor element and an element mounting base material on which the semiconductor element is mounted is improved.

一般に、半導体装置は第１図及び第２図に示す
構造のものが知られている。即ち、第１図はシリ
コン半導体素子（例えばバイポーラ半導体素子）
を素子配設基材（例えばリードフレーム）にマウ
ントし、さらにワイヤボンデイングした状態を示
す斜視図、第２図は樹脂封止、カツテイング加工
後の状態を示す断面図で、図中の１は半導体素子
がマウントされるアイランド部２及びワイヤがボ
ンデイングされるリード部３ａ，３ｂを有するリ
ードフレームである。このリードフレーム１のア
イランド部２、リード部３ａ，３ｂのボンデイン
グ部周囲には銀層４が被覆されている。また、前
記アイランド部２には上面にベース、エミツタの
Al電極５ａ，５ｂを有するシリコン半導体素子
６が金を主成分とする層７を介してマウントされ
ている。この半導体素子６のAl電極５ａ，５ｂ
には夫々金ワイヤ８ａ，８ｂが接地され、かつこ
れら金ワイヤ８ａ，８ｂの地端はベース、エミツ
タの電極として機能するリード部３ａ，３ｂに
夫々ポストボンデイングされている。更に図中の
９は半導体素子６を含むアイランド部２及びリー
ド部３ａ，３ｂの金ワイヤ８ａ，８ｂ接続部付近
を覆う樹脂封止層である。なお、樹脂封止層９か
ら露出したリード部３ａ，３ｂは半田層１０が被
覆されている。 Generally, semiconductor devices having structures shown in FIGS. 1 and 2 are known. That is, FIG. 1 shows a silicon semiconductor device (for example, a bipolar semiconductor device).
2 is a perspective view showing a state in which the semiconductor is mounted on an element mounting base material (for example, a lead frame) and wire bonded. Figure 2 is a cross-sectional view showing the state after resin sealing and cutting processing. 1 in the figure is a semiconductor This is a lead frame having an island portion 2 on which elements are mounted and lead portions 3a and 3b on which wires are bonded. A silver layer 4 is coated around the island portion 2 of the lead frame 1 and the bonding portions of the lead portions 3a and 3b. The island portion 2 also has a base and an emitter on the top surface.
A silicon semiconductor element 6 having Al electrodes 5a and 5b is mounted via a layer 7 mainly composed of gold. Al electrodes 5a, 5b of this semiconductor element 6
Gold wires 8a and 8b are grounded, respectively, and the ground ends of these gold wires 8a and 8b are post-bonded to lead portions 3a and 3b which function as base and emitter electrodes, respectively. Furthermore, numeral 9 in the figure is a resin sealing layer that covers the island portion 2 containing the semiconductor element 6 and the vicinity of the connection portions of the gold wires 8a and 8b of the lead portions 3a and 3b. Note that the lead parts 3a and 3b exposed from the resin sealing layer 9 are covered with a solder layer 10.

ところで、上述した半導体装置においてリード
フレーム１のアイランド部２に半導体素子６をマ
ウントするには、従来、次のような方法により行
なわれている。 Incidentally, in the above-described semiconductor device, mounting the semiconductor element 6 on the island portion 2 of the lead frame 1 has conventionally been carried out by the following method.

第３図に示す如く銅もしくは銅合金からなるリ
ードフレーム１のアイランド部２等に電気メツキ
手段により銀層４を被覆し、このアイランド部２
上に板状の金プリフオーム体１１及び半導体素子
６を順次重ねて載置した後、400〜450℃で加熱し
つつ半導体素子６をリードフレーム１の面と略平
行に振動を与え、金−シリコン共晶を形成すると
同時に、シリコン−金−銀の三元合金層を形成し
マウントする。 As shown in FIG. 3, the island portion 2 of the lead frame 1 made of copper or copper alloy is coated with a silver layer 4 by electroplating.
After placing the plate-shaped gold preform body 11 and the semiconductor element 6 on top of each other in order, the semiconductor element 6 is vibrated approximately parallel to the surface of the lead frame 1 while being heated at 400 to 450°C, and the gold-silicon At the same time as forming the eutectic, a ternary alloy layer of silicon-gold-silver is formed and mounted.

しかしながら、上記方法は次のような種々の欠
点があつた。 However, the above method had various drawbacks as follows.

シリコン半導体素子６よりも相当大きい金プ
リフオーム体１１を用いるため、マウント時の
半導体素子の位置決め精度が悪く、後工程での
不良発生が避けられない。 Since the gold preform body 11, which is considerably larger than the silicon semiconductor element 6, is used, the positioning accuracy of the semiconductor element during mounting is poor, and the occurrence of defects in subsequent processes is unavoidable.

金プリフオーム体１１をリードフレーム１の
アイランド部２に載置する工程を要し、作業の
煩雑さを招くばかりか、プリフオーム体を高精
度に載置するための装置を必要とする。 This requires a step of placing the gold preform body 11 on the island portion 2 of the lead frame 1, which not only complicates the work but also requires a device for placing the preform body with high precision.

高価の金の使用量が多く、半導体装置のコス
ト高騰の一因となる。 A large amount of expensive gold is used, which contributes to the soaring cost of semiconductor devices.

マウント工程において、金プリフオーム体１
１をリードフレーム１上の定位置に載置するた
めの時間と振動を与えるための時間を要し、生
産性が低い。 In the mounting process, the gold preform body 1
It takes time to place the lead frame 1 at a fixed position on the lead frame 1 and time to apply vibration, resulting in low productivity.

マウント工程において、400〜450℃の加熱が
必要なため、半導体素子への熱影響が大きく、
素子の電気特性を悪化させたり、破損を生じる
恐れがある。 The mounting process requires heating to 400-450℃, which has a large thermal effect on the semiconductor element.
There is a risk of deteriorating the electrical characteristics of the element or causing damage.

充分に高い接合強度を得ることが難しく、か
つ強度のばらつきが大きいため、製品の信頼性
が低い。 It is difficult to obtain a sufficiently high bonding strength, and the strength varies widely, resulting in low product reliability.

半導体素子を振動させて共晶を行なわせるた
め、半導体素子が破損したり、電気特性を劣化
させる。 Since the semiconductor element is vibrated to perform eutectic, the semiconductor element may be damaged or its electrical characteristics may deteriorate.

リードフレーム上に金プリフオーム体を圧着
し、合金層を作つてマウントするため、リード
フレームにメツキ法などの手段で銀層を被覆す
る工程が必要となり、製造工程が増えるばかり
か、リードフレームも高価となる。 Since the gold preform body is crimped onto the lead frame, an alloy layer is created, and then mounted, a process of coating the lead frame with a silver layer using a method such as plating is required, which not only increases the manufacturing process, but also makes the lead frame expensive. becomes.

リードフレーム上の銀層の厚さを２〜３μｍ
程度に薄くし、金プリフオーム体を介して半導
体素子をマウントすると、シリコン−金−銀−
銅の金属化合物ができる。このため、熱伝導率
が高く、半導体装置の熱抵抗も高くなり半導体
素子の電気特性の劣化や破損を招き易くなる。 The thickness of the silver layer on the lead frame is 2 to 3 μm.
When a semiconductor element is mounted through a gold preform, silicon-gold-silver-
A copper metal compound is formed. For this reason, the thermal conductivity is high, and the thermal resistance of the semiconductor device is also high, which tends to cause deterioration of the electrical characteristics and damage of the semiconductor element.

前記の対策としてリードフレーム上に５μ
ｍ以上の銀層をメツキするか、或いはニツケル
などの金属層を介して銀層をメツキするか、い
ずれかにより下地の銅が銀を介して金又はシリ
コン中に入らないようにすることが行なわれて
いる。しかし、こうした方法ではメツキ工程が
長くなつたり、煩雑化し、特に銀層を厚くする
と銀の使用量が増え、高価となる。 As a countermeasure for the above, 5μ is placed on the lead frame.
It is possible to prevent the underlying copper from entering the gold or silicon through the silver, either by plating a silver layer of m or more, or by plating the silver layer through a metal layer such as nickel. It is. However, in such a method, the plating process becomes long and complicated, and in particular, when the silver layer is made thicker, the amount of silver used increases and becomes expensive.

リードフレーム上の銀層は、空気中に放置す
ると硫化が起こり、簡単な処理による除去も難
しいため、素子のマウント性が悪化する。この
ため、リードフレームに銀層をメツキした後の
保管に細心の注意を必要とする。 If the silver layer on the lead frame is left in the air, it will sulfurize and it will be difficult to remove it by simple treatment, which will deteriorate the mountability of the device. For this reason, extreme care must be taken when storing the lead frame after it has been plated with a silver layer.

リードフレーム上の銀層の厚さが薄くなる
と、下地の金層が酸化し、銀層の膨れや剥離を
生じ、特に高温高湿になると、更にその膨れや
剥離が発生し易くなる。 When the thickness of the silver layer on the lead frame becomes thin, the underlying gold layer oxidizes, causing blistering and peeling of the silver layer, and especially when the temperature and humidity become high, the blistering and peeling become even more likely to occur.

このようなことから、半導体素子をリードフレ
ームにマウントする方法として、第４図に示す如
く、銅もしくは銅合金からなるリードフレーム１
のアイランド部２等に電気メツキ手段により銀層
４を被覆し、このアイランド部２上に金プリフオ
ーム体１１及びマウント面に厚さ1000〜3000Åの
金もしくは金合金の層１２を有する半導体素子６
を順次重ねて載置した後、400〜450℃で加熱し振
動を与えずに金−シリコン共晶を形成すると同時
にシリコン−金−銀の三元合金層を形成しマウン
トする方法が知られている。この方法によれば前
述したの欠点は解消できるものの他の点は改良
することができないばかりか、新たに半導体素子
のマウント面に金又は金合金の層を形成する工程
が必要となり、かつ価格も高くなる。 For this reason, as a method for mounting a semiconductor element on a lead frame, as shown in FIG. 4, a lead frame 1 made of copper or a copper alloy is
A semiconductor element 6 having a gold preform body 11 on the island portion 2 and a gold or gold alloy layer 12 with a thickness of 1000 to 3000 Å on the mounting surface.
A known method is to stack and mount gold and silicon eutectic layers in sequence, heat them at 400 to 450°C without applying vibration, and at the same time form a ternary alloy layer of silicon, gold and silver. There is. Although this method can eliminate the above-mentioned drawbacks, it cannot improve other points, and it requires an additional step of forming a layer of gold or gold alloy on the mounting surface of the semiconductor element, and is also expensive. It gets expensive.

また、別の方法として第５図に示す如く銅もし
くは銅合金からなるリードフレーム１のアイラン
ド部２等に電気メツキ手段により銀層４を被覆
し、更にこのアイランド部２の銀層４のマウント
部に電気メツキ等により0.5〜３μｍの金又は金
合金のメツキ層１３を被覆し、このメツキ層１３
上にマウント面に厚さ1000〜3000Åの金もしくは
金合金の層１２を有する半導体素子６を載置した
後、400〜450℃で加熱し振動を与えずに金−シリ
コン共晶を形成すると同時にシリコン−金−銀の
三元合金層を形成しマウントする方法が行なわれ
ている。この方法によれば前述した、、、
、の欠点は解消できるものの、他の点は改良
することができない。しかも、リードフレームの
銀層上に金メツキを行なうため、第３図に示した
方法よりも金の使用量が増し、工程も増え、時間
が長くなる。 Alternatively, as shown in FIG. 5, the island portion 2 of the lead frame 1 made of copper or copper alloy is coated with a silver layer 4 by electroplating, and the mounting portion of the silver layer 4 of the island portion 2 is coated with a silver layer 4. A plating layer 13 of 0.5 to 3 μm of gold or gold alloy is coated on the plating layer 13 by electroplating or the like.
A semiconductor element 6 having a layer 12 of gold or gold alloy with a thickness of 1000 to 3000 Å is placed on the mounting surface, and then heated at 400 to 450°C to form a gold-silicon eutectic without vibration. A method of forming and mounting a ternary alloy layer of silicon-gold-silver has been used. According to this method, as mentioned above,
Although the drawbacks of , can be overcome, other points cannot be improved. Moreover, since gold plating is performed on the silver layer of the lead frame, the amount of gold used is increased, the number of steps is increased, and the time is longer than in the method shown in FIG.

更に、別な方法として、第６図に示す如くマウ
ント面に金−シリコン共晶層１４を有する半導体
素子６を用い、これを銀層４が被覆されたリード
フレーム１のアイランド部２にマウントする方法
がある。この方法によれば、前述した〜の欠
点は解消できるものの、〜に挙げた問題点は
解消できない。しかも、新たな欠点として半導体
素子を作製するためのシリコン基板の割断が極め
て困難となる。即ち、マウントに必要な金−シリ
コン共晶層の厚さは最小１μｍで、個々の素子に
分割するにあたつて、通常と逆に金−シリコン共
晶層側からダイシングラインに沿つて切断する方
法が提供されている（特開昭52−132778号公
報）。しかし、実際上切断線とダイシングライン
の位置合せが非常に困難な上、位置ずれが100μ
ｍ以上になる欠点を有する。 Furthermore, as another method, as shown in FIG. 6, a semiconductor element 6 having a gold-silicon eutectic layer 14 on the mounting surface is used, and this is mounted on an island portion 2 of a lead frame 1 covered with a silver layer 4. There is a way. According to this method, although the above-mentioned drawbacks can be solved, the problems listed in - cannot be solved. Moreover, a new drawback is that it becomes extremely difficult to cut the silicon substrate for manufacturing semiconductor elements. In other words, the minimum thickness of the gold-silicon eutectic layer required for mounting is 1 μm, and when dividing into individual devices, cut along the dicing line from the gold-silicon eutectic layer side, contrary to the usual method. A method has been provided (Japanese Patent Application Laid-Open No. 132778/1983). However, in practice, it is extremely difficult to align the cutting line and dicing line, and the misalignment is 100μ.
It has the disadvantage of being more than m.

これに対し、本出願人は既に第７図ａに示す如
く半導体素子６のマウント面にバリア層としての
バナジウム層１５、ニツケル層１６を積層し更に
金−ゲルマニウム合金層１７、金層１８を積層し
たものを用い、この半導体素子６を銀層４が被覆
されたリードフレーム１のアイランド部２に加熱
押圧し、金−銀の金属間化合物１９を介してマウ
ントした構造の半導体装置（第７図ｂ図示）を提
案した。こうした方法によれげ前述した〜の
問題点を解消でき、更にリードレーム１上の銀層
の厚さをそれほど考慮せずにマウントを行なえる
が、リードフレームに銀層を被覆したことに伴な
う〜の問題点は未だ解消し得ない。 In contrast, the present applicant has already laminated a vanadium layer 15 and a nickel layer 16 as barrier layers on the mounting surface of the semiconductor element 6, and further laminated a gold-germanium alloy layer 17 and a gold layer 18, as shown in FIG. 7a. The semiconductor device 6 is heated and pressed onto the island portion 2 of the lead frame 1 coated with the silver layer 4, and mounted via the gold-silver intermetallic compound 19 (see Fig. 7). b) was proposed. This method can solve the above-mentioned problems, and can also be mounted without much consideration of the thickness of the silver layer on the lead frame 1. However, since the lead frame is coated with a silver layer, The problem still cannot be resolved.

なお、上述した問題点は素子配設基材としてリ
ードフレームを用いる代りにステムを用いた場合
でも同様に起こる。 Note that the above-mentioned problems also occur when a stem is used as the element mounting base material instead of a lead frame.

本発明を上述した問題点を一挙に解消するため
になされたもので、金プリフオーム体を使用せ
ず、かつ素子配設基材のマウント部に銀層を被覆
せずに該基材の素地に半導体素子をマウントした
半導体装置を提供しようとするものである。 The present invention has been made in order to solve the above-mentioned problems all at once, and it does not use a gold preform and coats the mounting part of the element mounting base material with a silver layer. The present invention aims to provide a semiconductor device in which a semiconductor element is mounted.

すなわち、本発明は銅もしくは銅合金の単体か
らなる素子配設基材と、半導体素子と、該半導体
素子のマウント面に銅、バナジウム、アルミニウ
ム、チタニウム、クロム、モリブデン、クロム合
金から選ばれる１種または２種以上の第１バリア
層、ニツケルもしくはコパールなどのニツケル合
金からなる第２バリア層、並びにゲルマニウムを
５〜20％含む金及びゲルマニウムを主成分とする
合金層をこの順序で積層した三層構造のろう材と
を用い、銀層が被覆されていない前記基材そのも
のの上に前記素子を前記ろう材を介してマウント
したことを特徴とするものである。 That is, the present invention provides an element mounting base material made of copper or a copper alloy, a semiconductor element, and one type selected from copper, vanadium, aluminum, titanium, chromium, molybdenum, and chromium alloy on the mounting surface of the semiconductor element. Or three layers in which two or more types of first barrier layer, a second barrier layer made of a nickel alloy such as nickel or copal, and an alloy layer mainly composed of gold and germanium containing 5 to 20% germanium are laminated in this order. The present invention is characterized in that the element is mounted on the base material itself, which is not coated with a silver layer, through the brazing material using a structural brazing material.

本発明において、ろう材の一方の構成材である
第１及び第２のバリア金属層は、マウント時の熱
処理に際し、ろう材の他方の構成材である金及び
ゲルマニウムを主成分とする合金層と半導体素子
を構成するシリコンとが反応するのを阻止し、半
導体素子と素子配設基材の接合部に硬くて脆く、
かつ熱抵抗の劣るAu−Cu−Siの金属間化合物が
形成されるのを防止する役目を有する。特に、第
１バリア金属層はバリア効果の他に、半導体素子
と第２バリア金属層とを良好に接着する働きを
し、第２バリア金属層は、バリア効果の他に、第
１バリア金属層と前記合金層とを良好に接着する
働きをするため、半導体素子に対してろう材を一
体的に接着できる。かかる第１のバリア金属層の
厚さは、100〜1000Å、第２バリア金属層は500〜
10000Å程度にすることが望ましい。 In the present invention, the first and second barrier metal layers, which are one of the constituent materials of the brazing filler metal, are combined with the alloy layer mainly composed of gold and germanium, which is the other constituent of the brazing filler metal, during heat treatment during mounting. It prevents the silicon that makes up the semiconductor element from reacting, making the joint between the semiconductor element and the element mounting base hard and brittle.
It also has the role of preventing the formation of Au--Cu--Si intermetallic compounds, which have poor thermal resistance. In particular, the first barrier metal layer not only has a barrier effect but also serves to bond the semiconductor element and the second barrier metal layer well, and the second barrier metal layer has a barrier effect as well as the first barrier metal layer. Since the brazing material serves to bond the alloy layer and the alloy layer well, the brazing material can be integrally bonded to the semiconductor element. The thickness of the first barrier metal layer is 100 to 1000 Å, and the thickness of the second barrier metal layer is 500 to 1000 Å.
It is desirable to set the thickness to about 10,000 Å.

本発明において、ろう材の他方の構成材である
金及びゲルマニウムを主成分とする合金層は素子
配設基材（Cu又はCu合金）に対して半導体素子
を良好にマウントする役目をする。かかる合金層
中のゲルマニウム添加量は５〜20％にすることが
必要である。この理由はゲルマニウムの添加量を
５％未満にすると、シリコン基板の割断に際し、
該合金層が割れ難くなり、かといつてその添加量
が20％を越えると、マウント時の温度を450℃以
上に高くしなければ十分な接合が得難くなり、ひ
いては半導体素子の電気特性に悪影響を及ぼす強
れがあるからである。このような合金層の厚さ
は、0.3〜2.5μｍ程度にすることが望ましい。な
お、必要に応じて、該合金層中のゲルマニウムの
酸化を防止するために、合金層上に更に金、銀、
白金から選ばれる金属層を被覆してもよい。こう
した金属層の厚さは500〜3000Åの範囲にするこ
とが望ましい。 In the present invention, the alloy layer mainly composed of gold and germanium, which is the other component of the brazing material, serves to properly mount the semiconductor element on the element mounting substrate (Cu or Cu alloy). The amount of germanium added in such an alloy layer needs to be 5 to 20%. The reason for this is that when the amount of germanium added is less than 5%, when cutting the silicon substrate,
The alloy layer becomes difficult to crack, and if the amount added exceeds 20%, it will be difficult to obtain a sufficient bond unless the mounting temperature is raised to 450°C or higher, which will have a negative impact on the electrical properties of the semiconductor element. This is because there is a strength that exerts. The thickness of such an alloy layer is preferably about 0.3 to 2.5 μm. In addition, if necessary, gold, silver, or
It may be coated with a metal layer selected from platinum. The thickness of such a metal layer is preferably in the range of 500 to 3000 Å.

本発明における素子配設基材としては、例えば
リードフレーム、ステム等を挙げることができ
る。かかる素子配設基材は酸化され易いが、還元
され易く清浄な面を表出し得る銅もしくは銅−
錫、銅−亜鉛、リン青銅などの銅合金の単体から
なるものである。 Examples of the element mounting base material in the present invention include a lead frame, a stem, and the like. Such element mounting substrates are made of copper or copper--which is easily oxidized but can be reduced easily and can provide a clean surface.
It consists of a single copper alloy such as tin, copper-zinc, or phosphor bronze.

次に、本発明の一実施例を第８図及び第９図を
参照して説明する。 Next, one embodiment of the present invention will be described with reference to FIGS. 8 and 9.

第８図は例えばバイポーラ型半導体素子をリー
ドフレームにマウントし、更にワイヤボンデイン
グを行なつた状態を示す斜視図、第９図は樹脂封
止、カツテイング加工を施した後の半導体装置を
示すものである。図中１０１は半導体素子がマウ
ントされるアイランド部１０２及びワイヤボンデ
イングされるリード部１０３ａ，１０３ｂを有す
る銅単体からなるリードフレームである。また、
図中の１０４は第１０図に示す如くマウント面に
厚さ約600Åのバナジウム層１０５、厚さ約2000
Åのニツケル層１０６、厚さ1.0μｍの金・ゲル
マニウム（Ge12wt％）合金層１０７及び厚さ
1000Åの金層１０８が順次積層された三層構造の
ろう材を有するバイポーラ型シリコン半導体素子
であり、この半導体素子１０４は第９図に示す如
く前記銅単体からなるリードフレーム１０１のア
イランド部１０２に加熱押圧によつてマウントさ
れている。つまり、半導体素子１０４はアイラン
ド部１０２に半導体素子１０４のシリコンが含有
されないAu−Ge−Cuの全率固溶体からなる接合
層１０９を介してマウントされている。また、前
記半導体素子１０４の上面にはベース、エミツタ
のAl電極１１０ａ，１１０ｂが設けられ、これ
らAl電極１１０ａ，１１０ｂには例えば金ワイ
ヤ１１１ａ，１１１ｂの一端が夫々ボンデイング
され、かつこれら金ワイヤ１１１ａ，１１１ｂの
他端は前記銅単体からなるリードフレーム１０１
のベース、エミツタの電極として機能するリード
部１０３ａ，１０３ｂに夫々ポストボンデイング
されている。そして、半導体素子１０４を含むリ
ードフレーム１０１のアイランド部１０２及びリ
ード部１０３ａ，１０３ｂの金ワイヤ１１１ａ，
１１１ｂ接続部付近は樹脂封止層１１２で覆われ
ている。また、樹脂封止層１１２から露出したア
イランド部のリード（図示せず）及びリード部１
０３ａ，１０３ｂには半田層１１３が被覆されて
いる。 Figure 8 is a perspective view showing, for example, a bipolar semiconductor element mounted on a lead frame and wire bonded, and Figure 9 shows the semiconductor device after resin sealing and cutting. be. In the figure, reference numeral 101 denotes a lead frame made of copper and having an island portion 102 on which a semiconductor element is mounted and lead portions 103a and 103b to which wire bonding is performed. Also,
104 in the figure is a vanadium layer 105 with a thickness of about 600 Å on the mounting surface, and a vanadium layer 105 with a thickness of about 2000 Å as shown in FIG.
A nickel layer 106 with a thickness of 1.0 μm, a gold/germanium (Ge12wt%) alloy layer 107 with a thickness of 1.0 μm, and a thickness of
This is a bipolar silicon semiconductor device having a three-layer brazing material in which gold layers 108 of 1000 Å are sequentially laminated, and as shown in FIG. Mounted by heating and pressing. That is, the semiconductor element 104 is mounted on the island portion 102 via the bonding layer 109 made of a solid solution of Au-Ge-Cu which does not contain silicon. Furthermore, base and emitter Al electrodes 110a and 110b are provided on the upper surface of the semiconductor element 104, and one ends of, for example, gold wires 111a and 111b are bonded to these Al electrodes 110a and 110b, respectively. The other end of 111b is the lead frame 101 made of copper alone.
The lead portions 103a and 103b, which function as base and emitter electrodes, are post-bonded, respectively. Then, the island portion 102 of the lead frame 101 including the semiconductor element 104 and the gold wire 111a of the lead portions 103a, 103b,
The vicinity of the connection portion 111b is covered with a resin sealing layer 112. In addition, the leads (not shown) of the island portion exposed from the resin sealing layer 112 and the lead portion 1
03a and 103b are coated with a solder layer 113.

なお、上述した半導体装置は例えば以下に示す
方法により造ることができる。 Note that the above-described semiconductor device can be manufactured, for example, by the method shown below.

まず、銅製薄片板をプレス加工して銅単体から
なるリードフレームを作製する。つづいて複数個
のnpnバイポーラトランジスタが形成されたシリ
コン基板のマウント面に厚さ約600Åのバナジウ
ム層、厚さ約2000Åのニツケル層、厚さ約1.0μ
ｍの金・ゲルマニウム（Ge12％）合金層及び厚
さ1000Åの金層を順次真空蒸着して積層して三層
構造のろう材とした後、シリコン基板をその上面
（マウント面と反対側の面）よりダイヤモンドス
クライブ又はブレードダイサースクライブにより
割断して第１０図に示す半導体素子１０４を作製
する。なお、これら半導体素子は塩化ビニール等
で被覆して保管する。次いで、前記リードフレー
ムをH2−N2のフオーミングガス（還元性雰囲
気）中で370〜400℃に加熱した状態で、このリー
ドフレームのアイランド部に前記半導体素子を振
動を与えずに50〜80ｇの加重で押圧してマウント
する。その後、マウントされた半導体素素子の
Al電極に金ワイヤの一端をボンデイングし、更
に金ワイヤの他端を銅単体のリードフレームのリ
ード部にポストボンデイングし、更に樹脂封止を
施した後、延出したリード部等を半田浴に浸漬し
半田処理を施して第９図に示す半導体装置を造
る。 First, a thin copper plate is pressed to produce a lead frame made of copper alone. Next, on the mounting surface of the silicon substrate on which multiple NPN bipolar transistors were formed, there was a vanadium layer with a thickness of about 600 Å, a nickel layer with a thickness of about 2000 Å, and a layer of nickel with a thickness of about 1.0 μ.
A gold/germanium (Ge 12%) alloy layer with a thickness of 100 Å and a gold layer with a thickness of 1000 Å are sequentially vacuum-deposited and laminated to form a three-layer brazing material. ) is cut using a diamond scribe or a blade dicer scribe to produce a semiconductor element 104 shown in FIG. Note that these semiconductor elements are stored covered with vinyl chloride or the like. Next, with the lead frame heated to 370 to 400°C in a forming gas (reducing atmosphere) of H2 - N2 , the semiconductor element was heated for 50 to 400°C without vibration on the island portion of the lead frame. Mount by pressing with a weight of 80g. After that, the mounted semiconductor element is
One end of the gold wire is bonded to the Al electrode, and the other end of the gold wire is post-bonded to the lead part of a single copper lead frame. After sealing with resin, the extended lead part etc. is placed in a solder bath. A semiconductor device shown in FIG. 9 is manufactured by dipping and soldering.

しかして、本発明はマウント面にバナジウム層
１０５、ツケル層１０６からなるバリア金属層、
金ゲルマニウム合金層１０７及び金層１０８を順
次積層した三層構造のろう材を有する半導体素子
１０４を、銅単体からなるリードフレーム１０１
のアイランド部１０２に前記ろう材を介してマウ
ントし、半導体素子１０１からのシリコンの含有
のないAu−Ge−Cuの全率固溶体からなる接合層
１０９を介して接合するため、半導体素子１０４
をリードフレーム１０１のアイランド部１０２に
対して強固にマウントできる。事実、本発明の半
導体装置の信頼性試験を行なつたところ、以下の
如くなつた。 Therefore, the present invention includes a barrier metal layer consisting of a vanadium layer 105 and a Tsukel layer 106 on the mounting surface.
A semiconductor element 104 having a three-layer brazing material in which a gold germanium alloy layer 107 and a gold layer 108 are successively laminated is mounted on a lead frame 101 made of copper alone.
The semiconductor element 104 is mounted on the island portion 102 of the semiconductor element 102 through the brazing material and bonded through the bonding layer 109 made of a solid solution of Au-Ge-Cu containing no silicon from the semiconductor element 101.
can be firmly mounted on the island portion 102 of the lead frame 101. In fact, when a reliability test was conducted on the semiconductor device of the present invention, the results were as follows.

(i) 熱衝撃試験；本発明の半導体装置及び前述し
た第７図ｂに示すマウント構造の半導体装置の
熱衝撃試験を行なつたところ、第１１図に示す
特性図を得た。なお、図中のＡは本発明の半導
体装置の熱衝撃特性線、Ｂは第７図ｂのマウン
ト構造を有する半導体装置の特性線である。こ
の第１１図より本発明の半導体装置は高温側の
熱衝撃時でも不良率（クラツク発生等）が極め
て低く、マウント性能が良好であることがわか
る。(i) Thermal Shock Test: When the semiconductor device of the present invention and the semiconductor device having the mount structure shown in FIG. 7B described above were subjected to a thermal shock test, the characteristic diagram shown in FIG. 11 was obtained. Note that A in the figure is a thermal shock characteristic line of the semiconductor device of the present invention, and B is a characteristic line of the semiconductor device having the mount structure of FIG. 7b. It can be seen from FIG. 11 that the semiconductor device of the present invention has an extremely low defective rate (occurrence of cracks, etc.) even during thermal shock at high temperatures, and has good mounting performance.

(ii) ボイリング試験；本発明の半導体装置は98〜
100℃の沸騰水中で連続168時間浸漬しても特性
低下が認められず、公称時間（40時間）を大巾
にクリアーするものであつた。(ii) Boiling test; the semiconductor device of the present invention
No deterioration in properties was observed even after continuous immersion in boiling water at 100°C for 168 hours, exceeding the nominal time (40 hours) by a wide margin.

(iii) Ｐ、Ｃ、Ｔ（プレツシヤコツカーテスト）；
本発明の半導体装置は2.5気圧で168時間行なつ
ても特性低下が認められず、公称条件（2.0気
圧、168時間）より苛酷な条件でも十分良好な
特性を保持した。(iii) P, C, T (pressure test);
The semiconductor device of the present invention showed no deterioration in characteristics even after being operated at 2.5 atmospheres for 168 hours, and maintained sufficiently good characteristics even under conditions harsher than the nominal conditions (2.0 atmospheres, 168 hours).

(iv) 熱疲労試験；本発明の半導体装置は常温＋
150℃の温度下で５万サイクルの使用に耐え
（公称値、１万サイクル）、かつ常温＋200℃の
温度下でも５万サイクルの使用に耐えた。(iv) Thermal fatigue test; the semiconductor device of the present invention was tested at room temperature +
It withstood 50,000 cycles of use at a temperature of 150°C (nominal value, 10,000 cycles), and also withstood 50,000 cycles of use at a temperature of +200°C.

また、上記構造の本発明の半導体装置はコレク
タ、エミツタ間飽和電圧、熱抵抗共に従来構造の
半導体装置に比べて良好であつた。 Further, the semiconductor device of the present invention having the above structure had better collector-to-emitter saturation voltage and thermal resistance than the semiconductor device having the conventional structure.

更に、本発明の半導体装置はマウント面にバリ
ア金属層、金・ゲルマニウム合金層を順次積層し
た三層構造のろう材を有する半導体素子を用いる
ことにより、該半導体素子を銅単体（もしくは銅
合金単体）からなるリードフレームのアイランド
に良好にマウントできるため、以下に列挙する如
く種々効果を有するものである。 Further, the semiconductor device of the present invention uses a semiconductor element having a three-layered brazing filler metal in which a barrier metal layer and a gold/germanium alloy layer are successively laminated on the mounting surface. ), it has various effects as listed below.

(1) 金プリフオーム体を用いることなく、最低必
要限の金・ゲルマニウム合金層をろう材の一部
としてマウントするため、マウント時における
位置決め精度が良好で後工程でのワイヤボンデ
イングの不良発生を軽減できる。(1) Since the minimum necessary gold/germanium alloy layer is mounted as part of the brazing material without using a gold preform, positioning accuracy during mounting is good and wire bonding defects in the post-process are reduced. can.

(2) 金プリフオーム体を用いないため、金プリフ
オー体をリードフレーム（素子配設基材）に載
置するための装置が不要となり工程も短縮でき
る。(2) Since a gold preform body is not used, a device for mounting the gold preform body on a lead frame (element mounting base material) is not required, and the process can be shortened.

(3) 高価な金は、金・ゲルマニウム合金として最
少必要限しか用いないため、大幅なコストダウ
ンを図ることができる。(3) Expensive gold is used only in the minimum necessary amount in the gold-germanium alloy, resulting in significant cost reductions.

(4) シリコンの半導体素子と金・ゲルマニウム合
金層の間の第１、第２のバリア金属層を介在さ
せているため、リードフレームに対して半導体
素子を強固にマウントでき、しかもバリア金属
層としてバナジウム層とニツケル層との二層構
造とすることにより半導体素子と金・ゲルマニ
ウム合金属の接着強度を著しく向上できる。(4) Since the first and second barrier metal layers are interposed between the silicon semiconductor element and the gold/germanium alloy layer, the semiconductor element can be firmly mounted on the lead frame, and it can also be used as a barrier metal layer. By adopting a two-layer structure consisting of a vanadium layer and a nickel layer, the adhesive strength between the semiconductor element and the gold-germanium alloy metal can be significantly improved.

(5) 接合に関与する層が金・ゲルマニウム合金か
らなり、前述した従来の如く金・シリコン共晶
層に比べてクラツキング性が良好なため、シリ
コン基板の割断に際し、従来の如く金・シリコ
ン共晶層側から切断せずに、通常の方法に従つ
てシリコン基板上面（マウント面と反対側の
面）からダイシングラインに沿つて行なうこと
ができ、高精度の割断が可能となる。即ち、
金・シリコン共晶（シリコンが2.85wt％）と
金・ゲルマニウム共晶（ゲルマニウムが12wt
％）とのクラツキング性を比較すると、各成分
の密度は金19.3、シリコン2.42、ゲルマニウム
5.46で、金・シリコン共晶中に占めるシリコン
の体積は、19％、金・ゲルマニウム共晶中に占
めるゲルマニウムの体積は33％となり、金・ゲ
ルマニウム共晶はゲルマニウムの占める体積が
相当大で、金の占める比率が低いため、金・シ
リコン共晶に比べてクラツツキングが容易とな
り、上述の如くシリコン基板の上面側からの割
断が可能となる。(5) The layer involved in bonding is made of a gold-germanium alloy, which has better cracking properties than the conventional gold-silicon eutectic layer mentioned above. The cutting can be performed along the dicing lines from the top surface of the silicon substrate (the surface opposite to the mounting surface) according to a conventional method without cutting from the crystal layer side, making it possible to perform cutting with high precision. That is,
Gold-silicon eutectic (2.85wt% silicon) and gold-germanium eutectic (12wt% germanium)
%), the density of each component is 19.3% for gold, 2.42% for silicon, and 2.42% for germanium.
5.46, the volume of silicon in the gold-silicon eutectic is 19%, the volume of germanium in the gold-germanium eutectic is 33%, and the volume occupied by germanium in the gold-germanium eutectic is quite large. Since the proportion of gold is low, cracking is easier than in the gold-silicon eutectic, and the silicon substrate can be cut from the top side as described above.

(6) 金とゲルマニウムの蒸気圧は10-4トール付近
で近似しているため、金・シリコンまたは金・
アンチモンのような分別蒸発を招くことなく、
真空蒸着法により所定組成の金・ゲルマニウム
合金層を形成できる。(6) Since the vapor pressures of gold and germanium are similar at around 10 -4 Torr, gold/silicon or gold/germanium
Without causing fractional evaporation like antimony,
A gold/germanium alloy layer with a predetermined composition can be formed by vacuum evaporation.

(7) 金・ゲルマニウム合金層に更に金層を被覆す
れば、半導体素子をマウントする以前における
金・ゲルマニウム合金層の酸化を防止でき、マ
ウントの強度が極めて良好となり、信頼性の高
い半導体装置を得ることができる。(7) If the gold/germanium alloy layer is further coated with a gold layer, it is possible to prevent the oxidation of the gold/germanium alloy layer before mounting the semiconductor element, and the strength of the mount is extremely good, resulting in highly reliable semiconductor devices. Obtainable.

(8) マウントに際し、370〜400℃の加熱温度で半
導体素子を銅（もしくは銅合金）単体からなる
リードフレームに接触させ軽い圧力で振動を与
えることなくAu−Ge−Cuの三元合金層を形成
できるため、半導体素子への熱影響が少なく電
気特定も安定し、更に安定したマウントがなさ
れた半導体装置を得ることができる。(8) When mounting, the semiconductor element is brought into contact with a lead frame made of copper (or copper alloy) at a heating temperature of 370 to 400℃, and the Au-Ge-Cu ternary alloy layer is mounted using light pressure without vibration. Since it can be formed, it is possible to obtain a semiconductor device with less thermal influence on the semiconductor element, stable electrical specification, and more stable mounting.

(9) リードフレーム上には銀層の被覆が不要とな
り、銅もしくは銅合金の単体からなるため、銀
メツキ工程の省略できることによる工程の短縮
化と、リードフレームを安価に製作できる。(9) There is no need to cover the lead frame with a silver layer, and since it is made of copper or a copper alloy alone, the process can be shortened by eliminating the silver plating process, and the lead frame can be manufactured at low cost.

(10) 銀層の被覆が不要となるため銀の欠点である
銀の硫化による接合強度の低下、銀層下の下地
の酸化を解消でき、リードフレームの保管時、
マウント時に細心な注意をはらうことなく、半
導体素子をリードフレームに強固に接合でき
る。(10) Since there is no need to coat the lead frame with a silver layer, it is possible to eliminate the disadvantages of silver, such as the reduction in bonding strength due to silver sulfurization and the oxidation of the base under the silver layer.
Semiconductor elements can be firmly bonded to lead frames without having to be careful when mounting.

(11) リードフレームに銀層を被覆するためのメツ
キ工程がないので、銀層の信頼試験（銀層の膨
れ、剥れ試験、メツキ厚さ、メツキ不良の試
験）が不要となり、かつ半導体装置の自動化が
容易となり、更にプレス加工後の洗浄が簡単に
なると共に、銀層による方向性の生じない高精
度のリードフレームを得ることができる。その
他、リードフレームの洗浄中に局部電池の発生
による酸化が起こらない。(11) Since there is no plating process for coating the lead frame with a silver layer, there is no need for silver layer reliability tests (silver layer blistering, peeling tests, plating thickness, and plating defect tests), and semiconductor devices automation becomes easy, furthermore, cleaning after press working becomes easy, and a highly accurate lead frame without directionality due to the silver layer can be obtained. Additionally, oxidation due to local battery generation does not occur during cleaning of the lead frame.

(12) 金・ゲルマニウム合金層とリードフレームと
のマウントにより形成された接合層は金・ゲル
マニウム、銅の全率形の固溶体で、金属間化合
物とならない。このため、接合層に金属間化合
物ができないので、電気抵抗が小さく、化学的
に安定し、機械的強度の劣化のない高信頼性の
半導体装置を得ることができる。また、リード
フレームの構成材である銅は酸化され易いが、
接合層は金の拡散もしくは溶融により貴金層化
して耐酸化性が改善される。更に空気中で加熱
酸化されても、金が拡散して貴金属層が広くな
るため、酸化が接合部には起こらない。(12) The bonding layer formed by mounting the gold/germanium alloy layer and the lead frame is a solid solution of gold, germanium, and copper, and does not form an intermetallic compound. Therefore, since no intermetallic compound is formed in the bonding layer, a highly reliable semiconductor device with low electrical resistance, chemical stability, and no deterioration in mechanical strength can be obtained. In addition, copper, which is a constituent material of lead frames, is easily oxidized;
The bonding layer becomes a precious metal layer by diffusion or melting of gold, and its oxidation resistance is improved. Furthermore, even when heated and oxidized in air, the gold diffuses and the noble metal layer becomes wider, so oxidation does not occur at the joint.

なお、本発明に係る半導体装置は上記実施例の
如く半導体素子１０４にバナジウム層１０５、ニ
ツケル層１０６、金・ゲルマニウム合金層１０７
及び金属１０８を順次積層して三層構造ろう材と
し、このろう材を銅単体のリードフレーム１０１
のアイランド部にマウントした構造の限定されな
い。例えば、第１２図に示す如く半導体素子１０
４のマウント面に厚さ約600Åのバナジウム層１
０５、厚さ約2000Åのニツケル層１０６及び層さ
1.0μｍの金・ゲルマニウム合金層１０７を順次
積層して三層構造のろう材とし、このろう材を銅
単体からなるリードフレーム１０１のアイランド
部にマウントした構造でもよい。また、第１３図
に示す如く半導体素子１０４のマウント面に厚さ
約2500Åのニツケル層１０６及び金・ゲルマニウ
ム合金層１０７を順次積層し、これを銅単体から
なるリードフレーム１０１のアイランド部にマウ
ントしてもよい。 Note that the semiconductor device according to the present invention includes a vanadium layer 105, a nickel layer 106, and a gold-germanium alloy layer 107 in the semiconductor element 104 as in the above embodiment.
and metal 108 are sequentially laminated to form a three-layer brazing material, and this brazing material is used as a lead frame 101 made of copper alone.
The structure mounted on the island is not limited to this. For example, as shown in FIG.
Vanadium layer 1 with a thickness of about 600 Å on the mounting surface of 4
05, nickel layer 106 with a thickness of about 2000 Å and
A structure may be employed in which 1.0 μm gold/germanium alloy layers 107 are sequentially laminated to form a three-layered brazing material, and this brazing material is mounted on an island portion of a lead frame 101 made of a single copper element. Further, as shown in FIG. 13, a nickel layer 106 with a thickness of about 2500 Å and a gold-germanium alloy layer 107 are sequentially laminated on the mounting surface of the semiconductor element 104, and these are mounted on the island portion of the lead frame 101 made of copper alone. It's okay.

また、本発明に係る半導体装置は上記実施例の
如く銅（もしくは銅合金）単体からなるリードフ
レームに半導体素子をマウントする構造に限ら
ず、銅もしくは銅合金の単体からなるステムに半
導体素子をマウントしてもよい。 Furthermore, the semiconductor device according to the present invention is not limited to the structure in which the semiconductor element is mounted on a lead frame made of copper (or copper alloy) alone as in the above embodiment, but the semiconductor element is mounted on a stem made of copper or copper alloy alone. You may.

更に、本発明に係る半導体装置は半導体素子の
マウント部に当る素子配設基材部分が銅もしくは
銅合金の単体からなることが必要でワイヤのポス
トボンデイング部に必要に応じて銀層を被覆して
もよい。 Further, in the semiconductor device according to the present invention, the element mounting base material portion corresponding to the mounting portion of the semiconductor element must be made of copper or a copper alloy, and the post bonding portion of the wire may be coated with a silver layer as necessary. It's okay.

以上詳述した如く、本発明によれば金プリフオ
ーム体を使用せず、かつ素子配設基材のマウント
部に銀層を被覆せずに該基材の素地に半導体素子
をマウントすることにより、前述の(1)〜(12)に列挙
したマウント性能、電気特性等に優れ、安価で高
信頼性の半導体装置を提供できるものである。 As detailed above, according to the present invention, by mounting a semiconductor element on the base material of the base material without using a gold preform body and without coating the mounting portion of the base material with a silver layer, It is possible to provide an inexpensive and highly reliable semiconductor device that has excellent mounting performance, electrical characteristics, etc. listed in (1) to (12) above.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はシリコン半導体素子をリードフレーム
に配設した状態を示す斜視図、第２図は第１図の
リードフレームを樹脂封止し、カツテイングした
後の半導体装置を示す断面図、第３図〜第６図は
夫々従来法による半導体素子のマウント工程を示
す断面図、第７図ａ，ｂは本出願人が既に提案し
た半導体素子のマウント工程を示し、第７図ａは
マウント前の状態を示す断面図、第７図ｂはマウ
ント後の状態を示す断面図である。第８図は本発
明の一実施例を示すシリコン半導体素子をリード
フレームにマウント、ボンデイングした状態の斜
視図、第９図は第８図のリードフレームを樹脂封
止し、カツテイング加工した後の半導体装置を示
す断面図、第１０図は半導体素子をマウントする
前の状態を示す断面図、第１１図は本発明の半導
体装置及び第７図ｂの従来の半導体装置における
熱衝撃特性を示す線図、第１２図、第１３図は
夫々本発明の他の実施例を示す半導体素子のマウ
ント前の状態の断面図である。 １０１……銅単体からなるリードフレーム、１
０２……アイランド部、１０３ａ，１０３ｂ……
リード部、１０４……バイポーラ型シリコン半導
体素子、１０５……バナジウム層、１０６，１０
６′……ニツケル層、１０７……金・ゲルマニウ
ム合金層、１０８……金層、１０９……接合層、
１１０ａ，１１０ｂ……ベース、エミツタのAl
電極、１１１ａ，１１１ｂ……金ワイヤ、１１２
……樹脂封止層。 Fig. 1 is a perspective view showing a silicon semiconductor element arranged in a lead frame, Fig. 2 is a sectional view showing the semiconductor device after the lead frame shown in Fig. 1 has been sealed with resin and cut, and Fig. 3 - Fig. 6 is a cross-sectional view showing a mounting process of a semiconductor element by a conventional method, Fig. 7 a and b show a mounting process of a semiconductor element already proposed by the present applicant, and Fig. 7 a shows a state before mounting. FIG. 7b is a sectional view showing the state after mounting. FIG. 8 is a perspective view of a silicon semiconductor device according to an embodiment of the present invention mounted on a lead frame and bonded, and FIG. 9 is a semiconductor after the lead frame shown in FIG. 8 has been sealed with resin and cut. FIG. 10 is a cross-sectional view showing the device before mounting the semiconductor element, and FIG. 11 is a diagram showing the thermal shock characteristics of the semiconductor device of the present invention and the conventional semiconductor device of FIG. 7b. , FIG. 12, and FIG. 13 are sectional views of semiconductor devices before mounting, respectively, showing other embodiments of the present invention. 101...Lead frame made of copper alone, 1
02...Island part, 103a, 103b...
Lead portion, 104... Bipolar silicon semiconductor element, 105... Vanadium layer, 106, 10
6'... Nickel layer, 107... Gold/germanium alloy layer, 108... Gold layer, 109... Bonding layer,
110a, 110b...Base, emitter Al
Electrode, 111a, 111b... Gold wire, 112
...Resin sealing layer.

Claims (1)

【特許請求の範囲】 １ 銅もしくは銅合金の単体からなる素子配設基
材と、半導体素子と、該半導体素子のマウント面
に銅、バナジウム、アルミニウム、テタニウム、
クロム、モリブデン、クロム合金から選ばれる１
種または２種以上の第１バリア層、ニツケルもし
くはニツケル合金からなる第２バリア層、並びに
ゲルマニウムを５〜20％含む金及びゲルマニウム
を主成分とする合金層をこの順序で積層した三層
構造のろう材とを用い、銀層が被覆されていない
前記基材そのものの上に前記素子を前記ろう材を
介してマウントしたことを特徴とする半導体装
置。 ２ 半導体素子上面の電極と素子配設基材とを金
ワイヤで接続したことを特徴とする特許請求の範
囲第１項記載の半導体装置。[Claims] 1. An element mounting base made of copper or a copper alloy, a semiconductor element, and a mounting surface of the semiconductor element containing copper, vanadium, aluminum, tetanium,
1 selected from chromium, molybdenum, and chromium alloys
A three-layer structure in which a first barrier layer of a seed or two or more types, a second barrier layer made of nickel or a nickel alloy, and an alloy layer mainly composed of gold and germanium containing 5 to 20% germanium are laminated in this order. 1. A semiconductor device, wherein the element is mounted on the base material itself, which is not coated with a silver layer, via the brazing material. 2. The semiconductor device according to claim 1, wherein the electrode on the upper surface of the semiconductor element and the element mounting base material are connected by a gold wire.
JP55185930A 1980-12-26 1980-12-26 Semiconductor device Granted JPS57109347A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55185930A JPS57109347A (en) 1980-12-26 1980-12-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55185930A JPS57109347A (en) 1980-12-26 1980-12-26 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS57109347A JPS57109347A (en) 1982-07-07
JPS6129142B2 true JPS6129142B2 (en) 1986-07-04

Family

ID=16179358

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55185930A Granted JPS57109347A (en) 1980-12-26 1980-12-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57109347A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7538401B2 (en) * 2005-05-03 2009-05-26 Rosemount Aerospace Inc. Transducer for use in harsh environments

Also Published As

Publication number Publication date
JPS57109347A (en) 1982-07-07

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