JPS6074539A - Submount for optical semiconductor element - Google Patents

Submount for optical semiconductor element

Info

Publication number
JPS6074539A
JPS6074539A JP58180239A JP18023983A JPS6074539A JP S6074539 A JPS6074539 A JP S6074539A JP 58180239 A JP58180239 A JP 58180239A JP 18023983 A JP18023983 A JP 18023983A JP S6074539 A JPS6074539 A JP S6074539A
Authority
JP
Japan
Prior art keywords
layer
submount
solder
barrier
optical semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58180239A
Other languages
Japanese (ja)
Other versions
JPH063815B2 (en
Inventor
Katsutoshi Saito
斎藤　勝利
Masahide Tokuda
正秀 徳田
Kuninori Imai
今井　邦典
Kenichi Mizuishi
賢一 水石
Katsuaki Chiba
千葉　勝昭
Masamichi Kobayashi
正道 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58180239A priority Critical patent/JPH063815B2/en
Publication of JPS6074539A publication Critical patent/JPS6074539A/en
Publication of JPH063815B2 publication Critical patent/JPH063815B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Lasers (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To obtain the submount which withstands high temperature and high humidity by a method wherein the barrier layer to be provided on a wiring layer is constituted by Pt. CONSTITUTION:A wiring layer 41 is formed by performing a vacuum-deposition of Au layer 37, a Ti layer 38 and a Pt barrier main body layer 30 are successively vapor-deposited, and a barrier layer 41 is formed. Then, a solder layer- shaped window is provided on a resist layer 43. Subsequently, Pb-Sn solder 44 is vapor-deposited on the surface of the resist layer 43 in the state wherein a resist film is coated. Then, a sample is soaked in an organic solvent in which a photoresist film will be dissolved, supersonic vibrations are applied to the solvent, the resist film is removed by dissolution, and a solder layer 52 is selectively formed. Lastly, a heat conductive SiC ceramic substrate 31 is cut in accordance with the patterning pitc of the solder layer, and a submount 50 is manufacture. Then, after a semiconductor lase chip 53 has been die-conded on the solder layer 52, the submount is soldered on a heat dissipating member 56. Then, an Au wire 55 is supersonic die-bonded on the upper electrode 54. Also, an Au wire 57 is supersonic die-bonded on a barrier 42, and a chip lower electrode is connected to the outside part.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、光半導体素子のチップの実装に使用するサブ
マウントの構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to the structure of a submount used for mounting a chip of an optical semiconductor element.

〔発明の背景〕[Background of the invention]

従来、光半導体素子、特にレーザダイオードなどにおり
ては、金属やＳｔあるいは高熱伝導性絶縁材料から成る
サブマウントと称する小片に半導体チップをポンディン
グしたのち、ステムに実装するという手法が一般に用い
られている。このうち、高熱伝導性絶縁基板を用いたサ
ブマウントでは、ダイボンドされたチップの下面の電極
を、サブマウントの表面メタライズ層を介して外部に接
続する必要があるので、通常、第１図（断面図）に示す
構造が採用されていた／特願昭５８−４０６８１、／）
。すなわち、高熱伝導性絶縁基板（Ｉｌ−Ａ型ダイヤモ
ンド、酸化ベリリウム〔ベリリア〕、高熱伝導性ＳｉＣ
セラミックなど）１上に、蒸着、スパッタなどの方法に
よってメタライズした多層膜配線層（通常、最上層はＡ
ＬＩ）２が形成されている。配線層２は、必要ならばパ
ターンニングを施す。また、ソルダ層４と配線／ｍ　２
との反応を防止するためのバリヤ層３が配線層２上に部
分的に設けられている。Conventionally, for optical semiconductor devices, especially laser diodes, etc., a method has generally been used in which a semiconductor chip is bonded to a small piece called a submount made of metal, St, or a highly thermally conductive insulating material, and then mounted on a stem. ing. Among these, in submounts using highly thermally conductive insulating substrates, it is necessary to connect the electrodes on the bottom surface of the die-bonded chip to the outside via the surface metallized layer of the submount. The structure shown in Figure) was adopted/Patent Application No. 58-40681,/)
. That is, high thermal conductive insulating substrates (Il-A type diamond, beryllium oxide [beryllia], high thermal conductive SiC
(ceramic, etc.) 1, a multilayer wiring layer metalized by vapor deposition, sputtering, etc. (usually the top layer is A
LI)2 is formed. The wiring layer 2 is patterned if necessary. In addition, solder layer 4 and wiring/m 2
A barrier layer 3 is partially provided on the wiring layer 2 to prevent reaction with the wiring layer 2.

光半導体チップ（例えばレーデダイオードチップ）５を
実装するには、まず、ソルダ層４を溶融させてチップ５
をサブマウントにダイボンドしたのら、サブマウン）ｆ
金属製の放熱体７にソルダ８によりハンダ付けする（サ
ブマウントの裏面には、予めメタライズ層６が設けられ
ている。）。次に、チップ５の上面電極９とサブマウン
ト上の配線層２に、ＡＨＨＩＯ２１１をワイヤボンディ
ングして組立てを完了するものである。To mount the optical semiconductor chip (for example, a Raded diode chip) 5, first, the solder layer 4 is melted and the chip 5 is mounted.
After die bonding to the submount, the submount) f
It is soldered to the metal heat sink 7 with solder 8 (a metallized layer 6 is provided in advance on the back surface of the submount). Next, the AHHIO 211 is wire-bonded to the upper surface electrode 9 of the chip 5 and the wiring layer 2 on the submount to complete the assembly.

ここで、バリヤの材料には％ＭＯやＷなど、ソルダとの
濡れ性の悪い材料が用いられていた。このため、ソルダ
２４と接するバリヤ最上層には、ｍ２図に示すようにソ
ルダとの濡れ性に優れるＡｕやＡｇなどからなるソルダ
下地層２５を設け、かつ、バリヤ本体層（ＭＯ，Ｗなど
）２３とソルダ下地１−２５との間に、両者の混合層２
６を設けることにより密着性を高めていた。Here, materials with poor wettability with solder, such as %MO and W, have been used as barrier materials. For this reason, the uppermost layer of the barrier in contact with the solder 24 is provided with a solder base layer 25 made of Au, Ag, etc., which has excellent wettability with the solder, as shown in the m2 diagram, and a barrier main layer (MO, W, etc.) 23 and the solder base 1-25, a mixed layer 2 of both.
6, the adhesion was improved.

このサブマウントにおいては、バリヤ層に対するソルダ
の濡れ性やバリヤ層のバリヤ性が優れているが、高温萬
湿下でバリヤ層（Ｍ　ＯやＷ）の露出面が酸化するので
、長期的な信頼性に乏しく、また製造工程が複雑になる
などの欠点をもっていた。Although this submount has excellent solder wettability and barrier properties of the barrier layer, the exposed surface of the barrier layer (MO and W) oxidizes under high temperature and high humidity conditions, resulting in long-term reliability. It had disadvantages such as poor performance and complicated manufacturing process.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記の欠点を排除し、高温高湿にも耐
え得る、光半導体素子用サブマウントを提供することに
ある。An object of the present invention is to provide a submount for optical semiconductor elements that eliminates the above-mentioned drawbacks and can withstand high temperature and high humidity.

〔発明の背景〕[Background of the invention]

上記目的を達成するために、本発明では、配線層上に設
けるバリヤ層をｐｔで構成したことを特徴としている。In order to achieve the above object, the present invention is characterized in that the barrier layer provided on the wiring layer is made of PT.

これによシ、バリヤ層の耐湿性は大幅に改善される。ま
た、ｐｔはソルダに対して適度の濡れ性をもつので、ソ
ルダ層の下地として必ずしもＡｕ層を設ける必要がない
。また、バタンニングされたソルダ層が溶融した時の横
方向のソルダのしみ出しも僅かであるので、バリヤ層を
部分的に限定して設ける必要もない。This significantly improves the moisture resistance of the barrier layer. Furthermore, since PT has a suitable wettability with respect to solder, it is not necessarily necessary to provide an Au layer as a base for the solder layer. Further, when the battened solder layer melts, the solder seeps out in the lateral direction only a little, so there is no need to provide a barrier layer in limited areas.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明を実施例を用いて詳細に説明する。 Hereinafter, the present invention will be explained in detail using examples.

第３図、第４図は、本発明の一実施例を説明するための
断面図である（実、癩例１）。FIGS. 3 and 4 are cross-sectional views for explaining one embodiment of the present invention (actual Leprosy Example 1).

まず、高熱伝導性ＳｉＣセラミック基板３１の裏面に、
基板を４００〜５００Ｃに加熱しながらＴｉ層３２を膜
厚的１００ＯＡ、Ｎｔ層３３を膜厚約４００ＯＡ真空蒸
着し、次いで、基板温度約２００ＣにおいてＡｕ層３４
を約２００ＯＡ真空蒸着して裏面メタライズ層４０を形
成した。First, on the back side of the highly thermally conductive SiC ceramic substrate 31,
While heating the substrate to 400-500C, a Ti layer 32 with a thickness of 100OA and a Nt layer 33 with a thickness of about 400OA are vacuum-deposited, and then an Au layer 34 is deposited with a substrate temperature of about 200C.
The backside metallized layer 40 was formed by vacuum evaporation of about 200 OA.

次に、基板を３００Ｃに加熱しながら基板表面に’ｐｉ
層３５（膜厚的１００ＯＡ）、Ｐｔ層３６（膜厚的３０
０ＯＡ）、次いで基板温度約２００ＣでＡＵ層３７（約
１μｍ）を真空蒸着して配線層４１を形成し、さらに続
けてＴｉ層ａｓ（ｇ厚約１０００人）、Ｐｔバリヤ本体
層３９（膜厚的４００ＯＡ）を順次蒸着してバリヤ層４
２を形成した。Next, while heating the substrate to 300C, 'pi' was applied to the surface of the substrate.
Layer 35 (thickness: 100 OA), Pt layer 36 (thickness: 30 OA), Pt layer 36 (thickness: 30 OA)
0OA), then an AU layer 37 (about 1 μm) is vacuum-deposited at a substrate temperature of about 200C to form a wiring layer 41, followed by a Ti layer AS (g thickness about 1000 mm) and a Pt barrier main layer 39 (film thickness 400OA) was sequentially deposited to form barrier layer 4.
2 was formed.

次に、蒸着１ｇ全面に厚さ３〜５μｍのポジ型ホトレジ
スト膜を塗布し、ホトレジスト技術によシソルダ層の形
状（例えば４００２ｍＸ５００μｍ）の窓をレジスト層
４３に設けた。次いで、レジスト膜が被着した状態でこ
の面にＰ６−ｓｎソルダ４４を厚さ２〜４μｍ真空蒸着
した。次いで、ポジレジスト膜を溶解しうる有機溶剤（
例えばアセトン）中に試料を浸漬し、超音波振動を溶剤
に加えてレジスト膜を溶解除去することによシ、レジス
ト膜上のＰｂ−８ｎソルダ層を除去する、いわゆる「す
７トオフ法」によシ第４図に示すようなソルダ層５２を
選択的に形成した。Next, a positive photoresist film having a thickness of 3 to 5 μm was applied to the entire surface of 1 g of the vapor deposited film, and a window in the shape of the solder layer (for example, 4002 m×500 μm) was provided in the resist layer 43 by photoresist technology. Next, a P6-sn solder 44 was vacuum-deposited to a thickness of 2 to 4 μm on this surface with the resist film adhered thereto. Next, an organic solvent (
The so-called "S7-off method" removes the Pb-8n solder layer on the resist film by immersing the sample in (for example, acetone) and applying ultrasonic vibration to the solvent to dissolve and remove the resist film. A solder layer 52 as shown in FIG. 4 was selectively formed.

ソルダ層の組成比については、ソルダ層上に実装するチ
ップの構造や実装作業温度などを考慮して自由に調整す
ればよい。−例を挙げればｐｂ４０　ｗｔ、チ、Ｓ　ｎ
　６０　ｗｔ、％”’Ｃア；ｂ。The composition ratio of the solder layer may be freely adjusted in consideration of the structure of the chip to be mounted on the solder layer, the temperature of the mounting operation, etc. -For example, pb40 wt, chi, sn
60 wt, %”'Ca;b.

最後に、第４図に示すように、ソルダ層のバタンユング
ピツチにしたがって熱伝導性ＳｉＣセラミック基板３１
を切断し、例えば、横約１．５１１１１　％縦約１．２
閣の大きさのサプマウン）５０を製作した。Finally, as shown in FIG. 4, the thermally conductive SiC ceramic substrate 31 is
For example, width is about 1.51111% length is about 1.2
50 sapu mauns (the size of a cabinet) were made.

次に、サブマウント５０のソルダ層５２上に半導体レー
ザチップ５３をダイボンドしたのち、サブマウント５０
を放熱体５６にソルダ５５を用いてハンダ付けした。次
いで、チップ５３上の上部電極５４にＡｌｌ！５５を超
音波ボンディングし、また、下地に配線層４１をもつバ
リヤ層（Ｔｉ／Ｐｔ）４２上にＡｕ線５７を超音波ボン
ディングしてチップ下部電極を外部に接続した。Next, after die-bonding the semiconductor laser chip 53 onto the solder layer 52 of the submount 50,
was soldered to the heat sink 56 using the solder 55. Next, All! is applied to the upper electrode 54 on the chip 53. 55 was ultrasonically bonded, and an Au wire 57 was ultrasonically bonded onto the barrier layer (Ti/Pt) 42 having the wiring layer 41 as an underlying layer to connect the chip lower electrode to the outside.

以上述べた実施例によるすプマウントは、従来品に比べ
て構造、特にバリヤ層の構成が著しく簡累化されており
、製造工数が大幅に低減されている。例えば、バタンユ
ングのだめのホトレジスト工程を３工程から１工程に、
蒸着工程を４工程から３工程に低減することができた。The suspension mount according to the embodiments described above has a structure, particularly the structure of the barrier layer, that is significantly simplified compared to conventional products, and the number of manufacturing steps is significantly reduced. For example, the photoresist process in Batang Yung was reduced from 3 steps to 1 step.
The number of vapor deposition steps could be reduced from four to three.

また、バリヤ本体層にｐｔを用いているので、きわめて
安定したソルダ濡れ性を得ることができた。さらに、チ
ップ実装後の高温高湿保管テストにおいても、従来品に
みられたバリヤ層の酸化という問題を完全に解消するこ
とができた。Furthermore, since PT was used for the barrier main layer, extremely stable solder wettability could be obtained. Furthermore, even in high-temperature, high-humidity storage tests after chip mounting, we were able to completely eliminate the problem of oxidation of the barrier layer seen in conventional products.

ｌ第５図は本発明の他の実施例を示す断面である（実施
例２）。FIG. 5 is a cross section showing another embodiment of the present invention (Embodiment 2).

本実施例は、チップ下部電極を取出すための専用のポン
ディングパッドを設けたことを特徴とする。This embodiment is characterized by providing a dedicated bonding pad for taking out the chip lower electrode.

まず、高熱伝導性ＳｉＣセラミック基板６１の裏面に、
実施例１と同様のメタライズ層６２を設ける。次いで、
実施例１と同様の手法によシ基板表面に配線層６３とバ
リヤ層（１／ｐｔ）６４を被着し、さらに連続して／ｙ
ｕを厚さ約７０００Ａ被着した。次いで、ホトレジスト
技術を用いて最上ｊｆｊＯＡＵを選択エッチしてポンデ
ィングパッド６５を形成した。First, on the back side of the highly thermally conductive SiC ceramic substrate 61,
A metallized layer 62 similar to that in Example 1 is provided. Then,
A wiring layer 63 and a barrier layer (1/pt) 64 are deposited on the surface of the substrate by the same method as in Example 1, and then /y
A thickness of about 7000A was deposited. Next, the uppermost jfj OAU was selectively etched using a photoresist technique to form a bonding pad 65.

さらに、実施例１と同様のりフトオフ法を用いてバリヤ
層（Ｔｉ／Ｐｔ）６４上にＰｂ−８ｎフルダ層６６を選
択的に形成した。Furthermore, a Pb-8n full layer 66 was selectively formed on the barrier layer (Ti/Pt) 64 using the same lift-off method as in Example 1.

なお、最上ノーのＡｕ層を除去したＰｔバリヤ露出面に
、特別な前処理を施さずにｐｂ−ｓｎソルダ層を蒸着し
た場合には、Ｐｔ層に対するソルダ層の濡れ性が必ずし
も充分でない場合がある。この原因を種々検討した結果
、Ａｕ層の化学エッチによシ露出したＰｔ表面には、酸
化によるものと思われる変成層が存在することがわかっ
た。Note that if a pb-sn solder layer is deposited on the exposed surface of the Pt barrier after the topmost Au layer has been removed without any special pretreatment, the wettability of the solder layer to the Pt layer may not necessarily be sufficient. be. As a result of various investigations into the causes of this, it was found that a metamorphosed layer, which is thought to be caused by oxidation, exists on the Pt surface exposed by chemical etching of the Au layer.

このため、ｐｂ−ｓｎソルダの蒸着時には、ｐｔ衣表面
変成層を除去するための前処理を実施している。その前
処理の一例として、４フツ化水素酸水溶液、またはフッ
化水素酸とフッ化アンモニウムとの混合水溶液、などに
３０秒から数分間（９） 浸漬後、水洗・乾燥するという手法を挙げることができ
る。For this reason, when depositing the pb-sn solder, pretreatment is performed to remove the metamorphic layer on the surface of the pb-sn solder. An example of pretreatment is immersion in an aqueous solution of tetrafluoric acid or a mixed aqueous solution of hydrofluoric acid and ammonium fluoride for 30 seconds to several minutes (9), followed by washing with water and drying. I can do it.

本実施例によるサブマウントは、比較的厚いＡｕ層から
なる専用のポンディングパッドを有するので、実装チッ
プの下部電極を取出す際のワイヤボンディング作業条件
を緩和できる利点を有する。すなわち、低温・低荷重の
条件下でも充分な強さをもつボンディングを行うことが
可能であシ、また、超音波を印加しない熱圧着方式によ
るボンディングも可能である。Since the submount according to this embodiment has a dedicated bonding pad made of a relatively thick Au layer, it has the advantage of easing the wire bonding work conditions when taking out the lower electrode of the mounted chip. That is, it is possible to perform bonding with sufficient strength even under conditions of low temperature and low load, and bonding can also be performed by a thermocompression bonding method that does not apply ultrasonic waves.

配線ノーの抵抗値が多少高くても支障がない場合には、
第６図（断面図）に示すように、バリヤ層自体が配線層
を兼ねる構造とすることができる（実施例３）。以下、
第６図によシ詳細に説明する。If there is no problem even if the resistance value of the wiring no is a little high,
As shown in FIG. 6 (cross-sectional view), the barrier layer itself can serve as a wiring layer (Example 3). below,
This will be explained in detail with reference to FIG.

まず、高熱伝導性ＳｉＣセラミック基板７１の裏面に、
実施例１で述べたのと同様の方法で裏面メタライズｒ＠
７２を形成した。次に、基板温度約３００ＣでＴｉノー
７３を約１００ＯＡ真空蒸着し、次いで基板温度約２０
０Ｃでｐｔ層７４を約（１０） ６０００　人、次いでＡｕを約７０００Ａ連続的に蒸着
した。次いで、実施例２で述べたのと同様の方法でポン
ディングパッド７５とソルダ層７６を形成した。First, on the back side of the highly thermally conductive SiC ceramic substrate 71,
Back side metallization r@ by the same method as described in Example 1
72 was formed. Next, about 100 OA of Ti NO 73 was vacuum-deposited at a substrate temperature of about 300 C, and then the substrate temperature was about 20 C.
A PT layer 74 was continuously deposited at 0C for about (10) 6000A, and then Au was continuously deposited for about 7000A. Next, a bonding pad 75 and a solder layer 76 were formed in the same manner as described in Example 2.

本実施例によるサブマウントは、実施例１．２で述べた
サブマウントに比較して、構造がさらに簡素化されてい
るので、製造工数と製造原価の一層の低減を図ることが
できた。The structure of the submount according to this example is more simplified than that of the submount described in Example 1.2, so that it was possible to further reduce manufacturing man-hours and manufacturing costs.

また、実施例１，２によるサプマウンＨ−ｔ、Ａｕ７１
１を主体とする配線層をもつため、個々のサブマウント
に切断・分離する際、切断代がソルダパタンに接触した
り、ソルダパタンにかかることは許されなかった。もし
、上記のような切断を行うと、切断端面のごく近傍にお
けるバリヤ層の機械的損傷や、ソルダと配線用Ａｕ層と
の接触により、ソルダと配線層との好ましくない合金化
反応が生じてしまう。In addition, the submount H-t according to Examples 1 and 2, Au71
1, when cutting and separating into individual submounts, the cutting allowance was not allowed to come into contact with or cover the solder pattern. If the above-mentioned cutting is performed, mechanical damage to the barrier layer in the vicinity of the cut end surface and contact between the solder and the wiring Au layer may cause an undesirable alloying reaction between the solder and the wiring layer. Put it away.

このため、実施例１．２によるサブマウント製作時の切
断工程においては、きわめて正確な切断位置決めが必要
であった。一方、本実施例による（１１） サブマウントでは、Ａｕ’ｔ−主体とした配線層は存在
しないので、たとえばソルダ・くタンにかかるような切
断を行っても全く支障がない。したがって、本実施例に
よるサブマウントの切断作業では、切断箇所の位置決め
精度が大幅に緩和され、作業時間が短縮できた。Therefore, extremely accurate cutting positioning was required in the cutting process when manufacturing the submount according to Example 1.2. On the other hand, in the (11) submount according to the present embodiment, since there is no wiring layer mainly composed of Au't, there is no problem at all even if cutting is performed such as cutting across the solder. Therefore, in the cutting work of the submount according to this embodiment, the positioning accuracy of the cutting location is significantly relaxed, and the working time can be shortened.

さらに、実施例１．２によるサブマウントでは、Ａｕ配
線導体層上のｐｔバリヤ層のバリヤ性を確保するために
、ピンホールの原因となる塵埃や蒸着条件の厳密な管理
が必要であったが、本実施例の場合には、作業室の無塵
度や蒸着条件を実施例１．２による場合よシも緩和する
ことができる。Furthermore, in the submount according to Example 1.2, in order to ensure the barrier properties of the PT barrier layer on the Au wiring conductor layer, it was necessary to strictly control the dust that causes pinholes and the deposition conditions. In the case of this embodiment, the dust-free degree of the working chamber and the deposition conditions can be made more relaxed than in the case of embodiment 1.2.

以上の説明では、サブマウントを構成する基板材料とし
て高熱伝導性ＳｉＣセラミック基板を用いた例を挙げた
が、ＩＩ−Ａ型ダイヤモンドやベリリアなどの高熱伝導
性絶縁物基板も使用できる。In the above description, an example is given in which a highly thermally conductive SiC ceramic substrate is used as the substrate material constituting the submount, but highly thermally conductive insulating substrates such as II-A type diamond and beryllia can also be used.

さらに、微少な電力しか消費しない光半導体チップを実
装する場合には、必ずしも高熱伝導性が必要ではなく、
アルミナのような通常のセラミック基板を用いることも
可能である。Furthermore, when mounting optical semiconductor chips that consume only a small amount of power, high thermal conductivity is not necessarily required.
It is also possible to use conventional ceramic substrates such as alumina.

（１２） また、エツチングによシ露出させたＰｔ面の変成層を除
去するには、実施例２で述べた方法以外に、イオンエツ
チング、プラズマクリーニングなどの手法によシ物理的
に変成層を除去する方法を適用することも可能である。(12) In addition to the method described in Example 2, in order to remove the metamorphic layer on the Pt surface exposed by etching, methods such as ion etching and plasma cleaning can be used to physically remove the metamorphic layer. It is also possible to apply a method of removal.

また、配線層およびバリヤ層に用いているＴｉ層は、下
地との密着性を確保するための・コンタクトメタルであ
ｐ、’ｒｉＯ代シにＣｒを用いてもよい。Further, the Ti layer used for the wiring layer and the barrier layer may be a contact metal for ensuring adhesion with the underlying layer, and Cr may be used as a contact metal.

さらに、ソルダ層を選択的に形成する手段をしては、リ
フトオフ法以外に、蒸着マスクを用いた選択蒸着法や、
選択メッキ法なども利用できる。Furthermore, methods for selectively forming the solder layer include, in addition to the lift-off method, a selective vapor deposition method using a vapor deposition mask;
Selective plating methods can also be used.

また、以上の実施例では、１個のソルダパタン層と１個
のポンディングパッド層をもつサブマウントについて説
明したが、複数個のソルダバタン層と複数個のポンディ
ングパッドを設けることも光分可能である。Furthermore, in the above embodiment, a submount having one solder pattern layer and one bonding pad layer was described, but it is also possible to provide multiple solder pattern layers and multiple bonding pads. be.

〔発明の効果〕〔Effect of the invention〕

以上詳述したように、本発明によれば、高温高湿にも耐
え得る光半導体用サブマウントが実現で（１３） き、実用に供してその効果は著しい。As detailed above, according to the present invention, it is possible to realize a submount for optical semiconductors that can withstand high temperature and high humidity (13), and its effects are remarkable in practical use.

【図面の簡単な説明】[Brief explanation of the drawing]

、第１図は従来のサブマウントを用いて実装した光半導
体素子の断面図、第２図は従来のサブマウントのバリヤ
層付近の拡大断面図、ｍ３図は本発明の一実施例を示す
断面図、第４図は第３図に示すサブマウントを用いて実
装した光半導体素子の断面図、第５図は本発明の他の実
施例を示す断面図、第６図は本発明のさらに他の実施例
を示す断面図である。 ３１・・・高熱伝導性ＳｉＣセラミック基板、３５・・
・Ｔｉ層、３６・Ｐｔ層、３７・ｌｕ層、３８・・・Ｔ
ｉ層、３９・・・Ｐｔ層、４０・・・裏面メタライズ層
、５２・・・ソルダ層、６３・・・配線層、６４・・・
バリヤ層、６５・・・ポンディングパッド、７１・・・
高熱伝導性ＳｉＣセラミック基板、７３・・・Ｔｉ層、
７４・・・ｐｔ層、７５・・・ポンディングパッド、７
６・・・ソルダ層。 代理人　弁理士　高橋明夫。 （１４） 第　／　圀 第　２　図 第　３　日 第　４　国, Fig. 1 is a cross-sectional view of an optical semiconductor element mounted using a conventional submount, Fig. 2 is an enlarged cross-sectional view of the vicinity of the barrier layer of the conventional submount, and Fig. m3 is a cross-sectional view showing an embodiment of the present invention. 4 is a sectional view of an optical semiconductor element mounted using the submount shown in FIG. 3, FIG. 5 is a sectional view showing another embodiment of the present invention, and FIG. 6 is a further embodiment of the present invention. FIG. 31... High thermal conductivity SiC ceramic substrate, 35...
・Ti layer, 36・Pt layer, 37・lu layer, 38...T
i layer, 39... Pt layer, 40... back metallized layer, 52... solder layer, 63... wiring layer, 64...
Barrier layer, 65... Ponding pad, 71...
High thermal conductivity SiC ceramic substrate, 73...Ti layer,
74... PT layer, 75... Ponding pad, 7
6...Solder layer. Agent: Patent attorney Akio Takahashi. (14) Country/Country Number 2 Figure 3 Day 4 Country

Claims (1)

【特許請求の範囲】 １、光半導体素子のチップを実装するだめのサブマウン
トにおいて、高熱伝導性電気絶縁材料でサブマウント基
体を構成し、かつ、サブマウント基体の主面に第１層Ｔ
ｉまたはＣｒ、第２層Ｐｔ１第３層Ａｌｌからなる多層
膜で配線用導体層を形成し、さらにその上に第１層Ｔｉ
またはＣｒ、第２層ｐｔからなる拡散バリヤ１−を設け
、さらにその上にバタンニングされた複数個のソルダ層
を選択的に設けたことを特徴とする光半導体素子用サブ
マウント。 ２、前記拡散バリヤ層上の一部分に、Ａｕ層からなるワ
イヤポンディングパッドを設けたことを特徴とする特許
請求の範囲第１項記載の光半導体素子用サブマウント。 ３、前記サブマウントの基体材料が高熱伝導性ＳｉＣセ
ラミック（ＳｔＣにＢｅＯを添加した焼結体）であるこ
とを特徴とする特許請求の範囲第１項および第２項記載
の光半導体素子用サブマウント。 ４、前記ソルダ層がＰｂとＳｎの合金で構成されたこと
を特徴とする特許請求の範囲第３項記載の光半導体素子
用サブマウント。 ５、前記サブマウント基体の裏面に第１層ＴｉまたはＣ
ｒ、第２層Ｎ”ｓ第３層Ａｕからなる多層膜を設けたこ
とを特徴とする特許請求の範囲第４項記載の光半導体素
子用サブマウント。 ６、前記第１鳩目Ｔｉ層、前記第２鳩目Ｐｔ層からなる
配線用導体層を兼ねたバリヤ層を有する特許請求の範囲
第４項記載の光半導体素子用サブマウント。[Claims] 1. In a submount for mounting a chip of an optical semiconductor element, the submount base is made of a highly thermally conductive electrical insulating material, and a first layer T is formed on the main surface of the submount base.
A conductor layer for wiring is formed of a multilayer film consisting of a second layer of Pt or a third layer of All, and a first layer of Ti or Cr is formed on the multilayer film.
A submount for an optical semiconductor device, characterized in that a diffusion barrier 1- made of Cr and a second layer PT is provided, and a plurality of solder layers are selectively provided thereon. 2. The submount for an optical semiconductor device according to claim 1, wherein a wire bonding pad made of an Au layer is provided on a portion of the diffusion barrier layer. 3. The sub-sub for an optical semiconductor device according to claims 1 and 2, wherein the base material of the sub-mount is a highly thermally conductive SiC ceramic (a sintered body of StC with BeO added). mount. 4. The submount for an optical semiconductor device according to claim 3, wherein the solder layer is made of an alloy of Pb and Sn. 5. A first layer of Ti or C on the back surface of the submount base.
5. The submount for an optical semiconductor device according to claim 4, further comprising a multilayer film consisting of a second layer N''s and a third layer Au. 6. The first eyelet Ti layer; The submount for an optical semiconductor device according to claim 4, which has a barrier layer that also serves as a wiring conductor layer and is made of a second eyelet Pt layer.
JP58180239A 1983-09-30 1983-09-30 Submount for optical semiconductor device Expired - Lifetime JPH063815B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58180239A JPH063815B2 (en) 1983-09-30 1983-09-30 Submount for optical semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58180239A JPH063815B2 (en) 1983-09-30 1983-09-30 Submount for optical semiconductor device

Publications (2)

Publication Number Publication Date
JPS6074539A true JPS6074539A (en) 1985-04-26
JPH063815B2 JPH063815B2 (en) 1994-01-12

Family

ID=16079797

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58180239A Expired - Lifetime JPH063815B2 (en) 1983-09-30 1983-09-30 Submount for optical semiconductor device

Country Status (1)

Country Link
JP (1) JPH063815B2 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6329970U (en) * 1986-04-03 1988-02-27
JPH0537089A (en) * 1991-07-25 1993-02-12 Mitsubishi Electric Corp Semiconductor laser device
JP2001127370A (en) * 1999-10-22 2001-05-11 Kyocera Corp Submount for mounting semiconductor element
JP2001274500A (en) * 2000-03-28 2001-10-05 Sharp Corp Semiconductor laser device
WO2003094220A1 (en) * 2002-04-30 2003-11-13 Sumitomo Electric Industries, Ltd. Submount and semiconductor device
WO2005091351A1 (en) * 2004-03-24 2005-09-29 Tokuyama Corporation Substrate for device bonding and method for manufacturing same
JP2006173371A (en) * 2004-12-16 2006-06-29 Mitsubishi Electric Corp Semiconductor device
JP2013125768A (en) * 2011-12-13 2013-06-24 Japan Oclaro Inc Solder bonding device and reception module

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI514522B (en) 2005-03-18 2015-12-21 Dowa Electronics Materials Co Submount and method for making a submount

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5715446A (en) * 1980-07-02 1982-01-26 Hitachi Ltd Semiconductor device
JPS57112085A (en) * 1980-12-29 1982-07-12 Fujitsu Ltd Photocoupler

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5715446A (en) * 1980-07-02 1982-01-26 Hitachi Ltd Semiconductor device
JPS57112085A (en) * 1980-12-29 1982-07-12 Fujitsu Ltd Photocoupler

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6329970U (en) * 1986-04-03 1988-02-27
JPH0453017Y2 (en) * 1986-04-03 1992-12-14
JPH0537089A (en) * 1991-07-25 1993-02-12 Mitsubishi Electric Corp Semiconductor laser device
JP2001127370A (en) * 1999-10-22 2001-05-11 Kyocera Corp Submount for mounting semiconductor element
JP2001274500A (en) * 2000-03-28 2001-10-05 Sharp Corp Semiconductor laser device
CN100394567C (en) * 2002-04-30 2008-06-11 住友电气工业株式会社 Submount and semiconductor device
US7015583B2 (en) 2002-04-30 2006-03-21 Sumitomo Electric Industries, Ltd. Submount and semiconductor device
WO2003094220A1 (en) * 2002-04-30 2003-11-13 Sumitomo Electric Industries, Ltd. Submount and semiconductor device
KR100940164B1 (en) 2002-04-30 2010-02-03 스미토모덴키고교가부시키가이샤 Submount and semiconductor device
WO2005091351A1 (en) * 2004-03-24 2005-09-29 Tokuyama Corporation Substrate for device bonding and method for manufacturing same
CN100428432C (en) * 2004-03-24 2008-10-22 德山株式会社 Substrate for bonding element and method of manufacturing the same
US7626264B2 (en) 2004-03-24 2009-12-01 Tokuyama Corporation Substrate for device bonding and method for manufacturing same
JP2006173371A (en) * 2004-12-16 2006-06-29 Mitsubishi Electric Corp Semiconductor device
JP2013125768A (en) * 2011-12-13 2013-06-24 Japan Oclaro Inc Solder bonding device and reception module

Also Published As

Publication number Publication date
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