JPH05190973A - Submount for semiconductor laser - Google Patents

Submount for semiconductor laser

Info

Publication number
JPH05190973A
JPH05190973A JP4004321A JP432192A JPH05190973A JP H05190973 A JPH05190973 A JP H05190973A JP 4004321 A JP4004321 A JP 4004321A JP 432192 A JP432192 A JP 432192A JP H05190973 A JPH05190973 A JP H05190973A
Authority
JP
Japan
Prior art keywords
layer
semiconductor laser
submount
laser chip
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4004321A
Other languages
Japanese (ja)
Other versions
JP3190718B2 (en
Inventor
Motoi Suhara
基 須原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP00432192A priority Critical patent/JP3190718B2/en
Publication of JPH05190973A publication Critical patent/JPH05190973A/en
Application granted granted Critical
Publication of JP3190718B2 publication Critical patent/JP3190718B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To facilitate the position adjustment thereby enabling the continuous bonding step to be performed by one temperature control by a method wherein the contact surface between Aw and solder layer is accepted only on the bonding side onto a metallic radiator while a barrier layer is provided beneath the solder layer on the bonding side onto a semiconductor chip. CONSTITUTION:A Ti layer 2, a Pt layer 3, and Au layers 4a, 4b are respectively formed on a metallic radiator side reverse to the semiconductor laser chip side of a submount 1. Besides, another Pt layer 6 is laminated to be functioned as a barrier metal on a part or the whole surface of the topmost Au layer 4a on a semiconductor laser chip 8 side to be covered with an AuSn solder layer 7. Furthermore, the Au layer 4a on the semiconductor laser chip side works as the junction region of a metallic wire while the other Au layer 4b on, the metallic radiator side works as a part of the solder layer. At this time, the submount 1 is soldered into the AuSn solder layer 7 on the metallic radiator 9 side so that the submount 1 may be bonded onto the radiator 9 due to the AuSn layer in different composition from that in the initial AuSn layer.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、はんだ材の膜厚・組成
の制御性、半導体レーザの信頼性、位置調整の容易性に
優れ、かつ、サブマウントと半導体レーザの連続蒸着及
び、マウント自動化を含めた作業効率を向上する半導体
レーザ用サブマウントに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is excellent in controllability of film thickness and composition of solder material, reliability of semiconductor laser, easy position adjustment, and continuous vapor deposition of submount and semiconductor laser and automation of mounting. The present invention relates to a semiconductor laser submount that improves work efficiency including the above.

【0002】[0002]

【従来の技術】最近の半導体レーザは、光情報処理や光
通信の分野での実用化が進んでおり、いずれの分野でも
素子の信頼性が極めて重要な要素である。このような半
導体レーザは、電流が数10mA〜数100mA の領域で使用す
るが、発熱量が大きいため通常は金属放熱体をヒートシ
ンクとして用いるのが一般的である。さらに、熱膨脹係
数の差がストレス/歪みなどを発生させ、信頼性に影響
を与えることを避けるために金属放熱体の上には、半導
体基板材料と比較的熱膨脹係数が近い材料をサブマウン
トとして配置し、その上にはんだ材料を介して半導体レ
ーザチップを固着する方法をよく用いる。また、オーミ
ック性、接着強度ならびに信頼性を考慮して半導体レー
ザチップの最上層には、Au層を形成する。
2. Description of the Related Art Recent semiconductor lasers are being put to practical use in the fields of optical information processing and optical communication, and the reliability of the device is an extremely important factor in any field. Such a semiconductor laser is used in a region where the current is several 10 mA to several 100 mA, but since a large amount of heat is generated, a metal radiator is generally used as a heat sink. Further, in order to avoid the stress / distortion caused by the difference in thermal expansion coefficient from affecting the reliability, a material having a thermal expansion coefficient relatively close to that of the semiconductor substrate material is arranged as a submount on the metal radiator. Then, a method of fixing the semiconductor laser chip on it via a solder material is often used. An Au layer is formed on the uppermost layer of the semiconductor laser chip in consideration of ohmic property, adhesive strength and reliability.

【0003】本発明に記載する接着とは、いわゆる接着
剤を利用する技術を示すものでなく、比較的薄い金属膜
とはんだ層間または比較的薄い金属膜同士におきる固溶
状態を示すことを付記する。
It should be noted that the term "adhesion" as used in the present invention does not indicate a technique using a so-called adhesive, but indicates a solid solution state that occurs between a relatively thin metal film and a solder layer or between relatively thin metal films. To do.

【0004】固着部の構造例には、特開平1−1387
77号公報により示されたSi半導体基板両面にTi/
Pt/はんだから成る技術があり、この中Ti/Pt層
はバリア金属層として機能する。
An example of the structure of the fixed portion is disclosed in Japanese Patent Laid-Open No. 1-1387.
No. 77 / Ti on both sides of the Si semiconductor substrate
There is a technology consisting of Pt / solder, in which the Ti / Pt layer functions as a barrier metal layer.

【0005】他の例としては、特公平1−40514号
公報により明らかになった技術がある。即ち、Si半導
体基板の両面にAuめっきを施し、金属放熱体側のAu
層を10〜20μmと厚くすることによりAu−Si共晶は
んだを形成し、半導体レーザチップ側のAuとサブマウ
ント側Auの熱圧着を利用する(特開平1−40514
号公報参照)。
Another example is the technique disclosed in Japanese Patent Publication No. 1-40514. That is, both sides of the Si semiconductor substrate are plated with Au, and the Au on the metal radiator side is plated.
Au-Si eutectic solder is formed by increasing the thickness of the layer to 10 to 20 μm, and thermocompression bonding of Au on the semiconductor laser chip side and Au on the submount side is used (Japanese Patent Laid-Open No. 1-40514).
(See the official gazette).

【0006】更に、特開平2−128486号公報に明
らかにした構造を図3の断面図により説明すると、サブ
マウント1の両面にTi層2/Pt層3/Au層4/は
んだ層5を設ける構造が知られている。
Further, the structure disclosed in Japanese Patent Application Laid-Open No. 2-128486 will be described with reference to the cross-sectional view of FIG. 3. A Ti layer 2, a Pt layer 3, an Au layer 4 and a solder layer 5 are provided on both surfaces of the submount 1. The structure is known.

【0007】[0007]

【発明が解決しようとする課題】半導体レーザチップ、
サブマウント及び金属製放熱体のマウントに際しては、
まず金属製放熱体上にサブマウントを接着してから、サ
ブマウントに半導体レーザチップを接着する。更に電流
を流すためにAu細線をチップ上面及びサブマウント表
面に形成することが必要になる。
A semiconductor laser chip,
When mounting the submount and metal radiator,
First, the submount is bonded onto the metal radiator, and then the semiconductor laser chip is bonded to the submount. Further, it is necessary to form an Au thin wire on the upper surface of the chip and the surface of the submount in order to pass a current.

【0008】特開平1−138777号公報の明らかに
した技術では、最上面全面にはんだ層が、あるいはこの
はんだ層を部分的に除去してもPt層が露出するため
に、Au細線を接合することがてきない。
In the technique disclosed in Japanese Laid-Open Patent Publication No. 1-138777, the solder layer is exposed on the entire uppermost surface, or the Pt layer is exposed even if the solder layer is partially removed. I can't come.

【0009】また、特開平1−40514号公報に示し
た技術は、Au細線の接合にも支障がなく、その上連続
マウントも可能な構造であるが、サブマウントの半導体
レーザチップ側におけるAu−Auの熱圧着は、一度接
合すると温度を加えても容易に動かすことができない。
従って、半導体レーザチップの接着時の位置調整が極め
て難しくなる。
Further, the technique disclosed in Japanese Patent Application Laid-Open No. 1-40514 has a structure that does not hinder the joining of Au thin wires and allows continuous mounting. However, Au-on the semiconductor laser chip side of the submount is used. The thermocompression bonding of Au cannot be easily moved even if a temperature is applied once it is bonded.
Therefore, it becomes extremely difficult to adjust the position when bonding the semiconductor laser chip.

【0010】更にまた、特開平2−128486号公報
に明らかにした構造にあっては、サブマウントの両面に
はんだ層を設置するために、サブマウント及び半導体レ
ーザチップ各々の位置調整が容易にできるが、連続マウ
ントをする時に、一方を動かすと他方が動いてしまう可
能性がある。これに加えて、このような難点を防ぐに
は、上下のはんだの材質を即ち接着温度を変える方法も
よく使われる。しかし、Au層の上のはんだ層があるの
で、はんだ加熱時にAuとの反応か起り易く、サブマウ
ント上のAu細線を接着できる領域を浸蝕する恐れがあ
る。
Furthermore, in the structure disclosed in Japanese Unexamined Patent Publication No. 2-128486, since the solder layers are provided on both surfaces of the submount, it is possible to easily adjust the positions of the submount and the semiconductor laser chip. However, when performing continuous mounts, moving one may move the other. In addition to this, in order to prevent such difficulties, a method of changing the material of the upper and lower solders, that is, the bonding temperature is often used. However, since there is a solder layer on the Au layer, a reaction with Au is likely to occur when the solder is heated, and there is a risk of eroding the area on the submount to which the Au thin wire can be bonded.

【0011】本発明は、このような事情により成された
もので、特に、サブマウントと半導体レーザチップの連
続接着ならびにマウント自動化を含めた作業能率の向上
を可能にしたものである。
The present invention has been made in view of the above circumstances, and in particular, makes it possible to improve work efficiency including continuous bonding of a submount and a semiconductor laser chip and automation of mounting.

【0012】[0012]

【課題を解決するための手段】半導体レーザチップを固
着するサブマウント基板と,前記サブマウント基板の他
面に接着する金属製放熱体と,前記サブマウント基板の
金属製放熱体側に以下の順に重ねて連続して形成するT
i層、Pt層、Au層及びはんだ層と,前記サブマウン
ト基板の半導体レーザチップ側に下記の順に連続して形
成するTi層、Pt層及びAu層と,前記半導体レーザ
チップ側に形成するAu層に積層するPt層ならびに前
記はんだ層と同成分から成るはんだ層に本発明に係わる
半導体レーザ用サブマウントの特徴がある。
[MEANS FOR SOLVING THE PROBLEMS] A submount substrate to which a semiconductor laser chip is fixed, a metal heat radiator adhered to the other surface of the submount substrate, and a metal heat radiator side of the submount substrate are stacked in the following order. To form continuously
The i layer, the Pt layer, the Au layer, and the solder layer, the Ti layer, the Pt layer, and the Au layer continuously formed on the semiconductor laser chip side of the submount substrate in the following order, and the Au layer formed on the semiconductor laser chip side. The Pt layer laminated on the layer and the solder layer composed of the same component as the solder layer are characteristic of the semiconductor laser submount according to the present invention.

【0013】前記サブマウント基板の半導体レーザチッ
プ側に形成するはんだ層の厚さを金属製放熱体側のはん
だ層のそれより大きくする点にも特徴がある。
Another feature is that the thickness of the solder layer formed on the semiconductor laser chip side of the submount substrate is made larger than that of the solder layer on the metal radiator side.

【0014】[0014]

【作用】サブマウントの両面には、はんだ層を形成する
ために、半導体レーザチップやサブマウントの位置調整
が容易に行うことができる。また、半導体レーザチップ
側には、接着用のはんだ層が部分的にあり、その下にバ
リア層として機能するPt層を設置しているために接着
用の加熱時にもAu細線の接着領域を浸蝕しないことに
なる。
Since the solder layers are formed on both sides of the submount, the position adjustment of the semiconductor laser chip and the submount can be easily performed. Further, the semiconductor laser chip side has a solder layer for bonding partially, and since the Pt layer functioning as a barrier layer is installed under the solder layer, the bonding area of the Au thin wire is eroded even during heating for bonding. Will not do.

【0015】その上、多きな特徴は、金属製放熱体との
接着側だけにAuとはんだ層の接触面を採用し、半導体
チップの接着側にあつては、はんだ層の下にバリア層を
設置する。この結果、上下のはんだ層の接着時間に差が
生まれて、位置調整の容易さを維持しながら一方を動か
すと他方が動いてしまう問題点を克服した点にある。更
に上下面共、同一組成のはんだを使用するために一温度
制御となり、連続的な接着工程が可能になる。
In addition, many characteristics are that the contact surface between Au and the solder layer is adopted only on the bonding side with the metal radiator, and on the bonding side of the semiconductor chip, the barrier layer is provided under the solder layer. Install. As a result, there is a difference in the bonding time between the upper and lower solder layers, and the problem that the other moves when one is moved while maintaining the ease of position adjustment is overcome. Further, since the solder having the same composition is used on both the upper and lower surfaces, one temperature control is performed, and a continuous bonding process becomes possible.

【0016】[0016]

【実施例】本発明に係わる実施例を図1及び図2を参照
して説明すると、サブマウント1としては、熱伝導率の
良い厚さ400 μmの窒化アルミニウムを用いる。サブマ
ウント1の半導体レーザチップ側(紙面サブマウント1
の上側)と逆の金属製放熱体側には、Ti層2〜100
0オングストロ−ム、Pt層3〜1000オングストロ
−ム、Au層4a とAu層4b 共に〜5000オングス
トロ−ムをこの順に夫々形成する。
EXAMPLE An example according to the present invention will be described with reference to FIGS. 1 and 2. As the submount 1, aluminum nitride having a good thermal conductivity and a thickness of 400 μm is used. Semiconductor laser chip side of submount 1 (paper submount 1
On the metal radiator side opposite to that of Ti layer 2-100.
0 angstrom, Pt layer 3 to 1000 angstrom, Au layer 4a and Au layer 4b are formed to 5,000 angstrom in this order.

【0017】また、半導体レーザチップ8(図2参照)
側のAu層4a 最上層の一部または全面には、厚さ〜2
000オングストロ−ムのPt層6を重ねて設けてバリ
ヤ金属として機能させ、ここに厚さ〜5.2μmのAu
Snはんだ層7(以後ははんだパターニング層と記載す
る)を被覆する。本実施例に使用する半導体レーザチッ
プ8の寸法は、ほぼ400×300×100μmであ
る。
The semiconductor laser chip 8 (see FIG. 2)
The Au layer 4a on the side has a thickness of 2
000 angstrom Pt layer 6 is provided to serve as a barrier metal, where Au having a thickness of ˜5.2 μm is provided.
The Sn solder layer 7 (hereinafter referred to as a solder patterning layer) is covered. The size of the semiconductor laser chip 8 used in this embodiment is approximately 400 × 300 × 100 μm.

【0018】なお、半導体レーザチップ側のAu層4a
は、金属細線の接合領域として働くのに、金属製放熱体
側のAu層4b は、はんだ層の一部として機能する。半
導体レーザチップ側のAu層4a の一部もしくは全面に
Pt層6を形成するのは、半導体レーザチップを電気的
に浮かせるか否かにより決定する。電気的に浮かせるの
は、半導体レーザチップ及びサブマウント方向に電流を
流すか、それとも厚さ方向の途中から反転させて流すか
にかかっている。
The Au layer 4a on the semiconductor laser chip side
Serves as a bonding area for the metal thin wires, but the Au layer 4b on the metal radiator side functions as a part of the solder layer. The formation of the Pt layer 6 on a part or the whole surface of the Au layer 4a on the semiconductor laser chip side is determined by whether or not the semiconductor laser chip is electrically floated. Floating electrically depends on whether a current is passed in the direction of the semiconductor laser chip and the submount, or whether the current is reversed from the middle of the thickness direction and passed.

【0019】図1や図2のように半導体レーザチップ8
側のAu層4a 最上層の一部にPt層6とAuSnはん
だ層7を被覆する時は、半導体レーザを含む電子回路用
の部品を、露出するAu層4a 最上層の一部に例えば金
細線を熱圧着手段により設ける。
A semiconductor laser chip 8 as shown in FIGS.
When the Pt layer 6 and the AuSn solder layer 7 are coated on a part of the uppermost Au layer 4a on the side, a component for an electronic circuit including a semiconductor laser is formed on the exposed uppermost part of the Au layer 4a by, for example, a gold wire. Is provided by thermocompression bonding means.

【0020】一方、半導体レーザチップ側に設けるAu
層4b には、AuSnはんだ層7を例えば4μmに形成
して、半導体レーザチップ側のそれより薄くする。即
ち、半田の総量により決定する固化時間は、両層の差が
1.2μm程度あれば差が生じて、組立工程で有利にな
る。
On the other hand, Au provided on the semiconductor laser chip side
An AuSn solder layer 7 having a thickness of 4 μm, for example, is formed on the layer 4b to be thinner than that on the semiconductor laser chip side. That is, the solidification time determined by the total amount of solder will be different if the difference between the two layers is about 1.2 μm, which is advantageous in the assembly process.

【0021】組立工程としては、先ず前記の各層を積み
重ねたサブマウント1を図2に示す金属製放熱板9に金
属製放熱板側(以後金属製放熱板側を下側、半導体レー
ザチップ側を上側と記載する)のAuSnはんだ層7に
はんだ付けするが、金属製放熱板9を固定する支持台を
約300℃に予め昇温しておく。この時、AnSnはん
だ層7とAu4b 層は、互いに反応してある時間経過す
ると最初の組成と異なるAuSn層となりサブマウント
1と金属製放熱板9を強固に接着する。図2のAnSn
はんだ層7は、反応後の状態を明らかにしており、Au
4b 層を省略した。なおはんだ付け時間は、1分程度が
目安であり、このはんだ付け工程に続く上側のAuSn
はんだ付けに必要な位置合せに要するに足る時間であ
る。
In the assembling process, first, the submount 1 in which the above layers are stacked is placed on the metal heat sink 9 shown in FIG. 2 on the metal heat sink side (hereinafter, the metal heat sink side is the lower side, and the semiconductor laser chip side is the lower side). It is soldered to the AuSn solder layer 7 (described as the upper side), but the support base for fixing the metal radiator plate 9 is preheated to about 300 ° C. At this time, the AnSn solder layer 7 and the Au4b layer become an AuSn layer having a different composition from the initial composition after a certain time of reaction with each other, and firmly bond the submount 1 and the metal heat sink 9 to each other. AnSn of FIG.
The solder layer 7 reveals the state after the reaction, and Au
The 4b layer was omitted. Note that the soldering time is about 1 minute as a guide, and the upper AuSn following this soldering process
It is enough time for the alignment required for soldering.

【0022】次に例えばいわゆるマウンタに取付けた減
圧機構に連通する矢弦タイプの支持体(図示せず)に、
保持した半導体レーザチップ8は、マウンタの稼働によ
りサブマウント1に設置する溶融AnSnはんだ層7に
限り無く接近させ、しかもサブマウント1の外面を基準
として位置合せしてから両者を接触してはんだ付けを行
う。なお、窒素ガスを吹付けることにより冷却する。
Next, for example, on an arrow-string type support (not shown) communicating with a pressure reducing mechanism attached to a so-called mounter,
The held semiconductor laser chip 8 is brought close to the molten AnSn solder layer 7 installed on the submount 1 by the operation of the mounter as much as possible, and furthermore, the outer surface of the submount 1 is positioned as a reference and then the two are contacted and soldered. I do. In addition, it cools by spraying nitrogen gas.

【0023】この時、金属製放熱板側のAuSnはんだ
層7と金属製放熱板9のはんだ付けにより両者が固定状
態となっているために、後のはんだ付けが極めて容易に
進行する。このようなはんだ付け工程は、極めて円滑に
進行するので所要時間も少なく、一温度管理による工程
で連続的に接着することできるので、工程の短縮を図る
ことができる。
At this time, since the AuSn solder layer 7 on the metal heat dissipation plate side and the metal heat dissipation plate 9 are fixed by soldering, the subsequent soldering proceeds extremely easily. Since such a soldering process proceeds extremely smoothly, it takes a short time, and since it is possible to perform continuous bonding in a process controlled by one temperature, it is possible to shorten the process.

【0024】上側のAuSn半田7層の溶融に際して
は、バリア層であるPt層6の存在によりAu4a 層と
反応せずはんだとしての性質を保つことになり、金細線
を熱圧着するのに適した状態が維持できる。
When the AuSn solder 7 layer on the upper side is melted, the presence of the Pt layer 6 as the barrier layer does not react with the Au 4a layer and maintains the property as a solder, which is suitable for thermocompression bonding of fine gold wires. The state can be maintained.

【0025】本実施例では、サブマウト1の材料として
AlNを用いたが、SiCやダイヤモンド、Siのよう
な熱伝導の良い材料も使用可能であり、SiCのように
比較的はんだ材料との反応が激しく、長時間放置すると
Pt層3、6を越えて反応が進むものに対しては、上側
のAuSnはんだ7の厚さ下側のそれより厚くすること
により同様な効果が得られる。
Although AlN is used as the material of the sub-mout 1 in this embodiment, a material having good thermal conductivity such as SiC, diamond, or Si can be used, and a reaction with a solder material such as SiC is relatively likely to occur. The same effect can be obtained by making the AuSn solder 7 on the upper side thicker than that on the lower side for the one in which the reaction proceeds beyond the Pt layers 3 and 6 when left for a long time.

【0026】更に、はんだについては、Auと反応し易
い材料AuGe、AuSi&)及びInPbなども十分
適用できる。
Further, as the solder, materials such as AuGe, AuSi &) and InPb which easily react with Au can be sufficiently applied.

【0027】[0027]

【発明の効果】以上のように本発明によれは、位置調整
が容易で、Au細線の熱圧着領域が確保しつつ、一温度
制御によるサブマウント−金属製放熱板間、サブマウン
ト−半導体レーザチツプ間の連続接着ができるので、工
程の短縮が得られる。
As described above, according to the present invention, the position adjustment is easy and the thermocompression bonding area of the Au thin wire is ensured, and the submount-metal radiator plate and submount-semiconductor laser chip are controlled by one temperature control. Since the continuous adhesion between the two is possible, the process can be shortened.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係わる半導体レーザ用サブマウントの
一実施例の断面図である。
FIG. 1 is a sectional view of an embodiment of a semiconductor laser submount according to the present invention.

【図2】サブマウントに半導体レーザチップを本発明に
より接着後の要部の断面図である。
FIG. 2 is a sectional view of a main part after a semiconductor laser chip is bonded to a submount according to the present invention.

【図3】従来の半導体レーザチップ用サブマウントの断
面図である。
FIG. 3 is a sectional view of a conventional semiconductor laser chip submount.

【符号の説明】[Explanation of symbols]

1:サブマウント、 2:Ti層、 3、6:Pt層、 4a,4b :Au層、 7:AuSnはんだ層、 8:半導体レーザチップ、 9:金属製放熱板。 1: Submount, 2: Ti layer, 3, 6: Pt layer, 4a, 4b: Au layer, 7: AuSn solder layer, 8: Semiconductor laser chip, 9: Metal heat sink.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体レーザチップを接着するサブマウ
ント基板と,前記サブマウント基板の他面に接着する金
属製放熱体と,前記サブマウント基板の金属製放熱体側
に以下の順に重ねて連続して形成するTi層、Pt層、
Au層及びはんだ層と,前記サブマウント基板の半導体
レーザチップ側に下記の順に連続して形成するTi層、
Pt層及びAu層と,前記半導体レーザチップ側に形成
するAu層に積層するPt層ならびに前記はんだ層と同
成分から成るはんだ層を具備することを特徴とする半導
体レーザ用サブマウント
1. A submount substrate to which a semiconductor laser chip is bonded, a metal heat radiator to be bonded to the other surface of the submount substrate, and a metal heat radiator side of the submount substrate, which are successively stacked in the following order. Ti layer, Pt layer to be formed,
An Au layer and a solder layer, and a Ti layer continuously formed on the semiconductor laser chip side of the submount substrate in the following order:
A submount for a semiconductor laser, comprising a Pt layer and an Au layer, a Pt layer laminated on the Au layer formed on the semiconductor laser chip side, and a solder layer composed of the same components as the solder layer.
【請求項2】 前記サブマウント基板の半導体レーザチ
ップ側に形成するはんだ層の厚さを金属製放熱体側のは
んだ層のそれより大きくすることを特徴とする半導体レ
ーザ用サブマウント
2. A submount for a semiconductor laser, wherein the thickness of the solder layer formed on the semiconductor laser chip side of the submount substrate is larger than that of the solder layer on the metal radiator side.
【請求項3】 前記サブマウント基板の半導体レーザチ
ップ側に形成するAu層の一部に積層するPt層ならび
に前記はんだ層と同成分から成るはんだ層を具備するこ
とを特徴とする半導体レーザ用サブマウント
3. A semiconductor laser sub, comprising a Pt layer laminated on a part of an Au layer formed on the semiconductor laser chip side of the submount substrate and a solder layer made of the same component as the solder layer. mount
JP00432192A 1992-01-14 1992-01-14 Submount for semiconductor laser Expired - Fee Related JP3190718B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP00432192A JP3190718B2 (en) 1992-01-14 1992-01-14 Submount for semiconductor laser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP00432192A JP3190718B2 (en) 1992-01-14 1992-01-14 Submount for semiconductor laser

Publications (2)

Publication Number Publication Date
JPH05190973A true JPH05190973A (en) 1993-07-30
JP3190718B2 JP3190718B2 (en) 2001-07-23

Family

ID=11581202

Family Applications (1)

Application Number Title Priority Date Filing Date
JP00432192A Expired - Fee Related JP3190718B2 (en) 1992-01-14 1992-01-14 Submount for semiconductor laser

Country Status (1)

Country Link
JP (1) JP3190718B2 (en)

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JP2002057401A (en) * 2000-08-10 2002-02-22 Sony Corp Semiconductor laser and semiconductor device
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DE102006011232B4 (en) * 2005-04-25 2012-11-08 Hitachi Kyowa Engineering Co., Ltd. Substrate for mounting an electronic component and electronic component
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US9780523B2 (en) 2012-03-22 2017-10-03 Nichia Corporation Semiconductor laser device
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