JPS6395661A - Semiconductor element electrode - Google Patents
Semiconductor element electrodeInfo
- Publication number
- JPS6395661A JPS6395661A JP61241391A JP24139186A JPS6395661A JP S6395661 A JPS6395661 A JP S6395661A JP 61241391 A JP61241391 A JP 61241391A JP 24139186 A JP24139186 A JP 24139186A JP S6395661 A JPS6395661 A JP S6395661A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electrode
- substrate
- semiconductor
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 229910001020 Au alloy Inorganic materials 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 42
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 239000012790 adhesive layer Substances 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 abstract description 6
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 4
- 238000001771 vacuum deposition Methods 0.000 abstract description 3
- 238000007493 shaping process Methods 0.000 abstract 1
- 150000001875 compounds Chemical class 0.000 description 11
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000004215 Carbon black (E152) Substances 0.000 description 1
- 229920000742 Cotton Polymers 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 240000002329 Inga feuillei Species 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229930195733 hydrocarbon Natural products 0.000 description 1
- 150000002430 hydrocarbons Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Lasers (AREA)
- Led Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
(産業上の利用分野)
本発明はm−v族化合物からなる半導体基板を利用する
半導体素子特に光半導体素子の電極構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to an electrode structure of a semiconductor device, particularly an optical semiconductor device, using a semiconductor substrate made of an m-v group compound.
(従来の技術)
半導体レーザや発光ダイオードなどの光半導体素子では
、半導体チップへの通電のために半導体層に金属電極を
被着している。金属電極としては、一般に、Ti/Pt
/Auからなる多層金属膜が用いられる。(Prior Art) In optical semiconductor devices such as semiconductor lasers and light emitting diodes, a metal electrode is attached to a semiconductor layer in order to conduct electricity to the semiconductor chip. The metal electrode is generally Ti/Pt.
A multilayer metal film consisting of /Au is used.
(発明が解決しようとする問題点)
このような電極は、 InP、GaAs、InGaAs
P等の■−■族化合物半導体に対する接着力が極めて弱
い事実が判明した。即ち接着層であるTi膜はこのm−
V族化合物半導体と本来強い接着力を示すが、このTi
膜を形成する際適用する真空装置内に残留するわずかな
ハイドロカーボン(hydro Carbon)を主体
とする気体や水分と、又はこの化合物半導体表面を被覆
する極微量の汚染物質はゲッタ作用の強いT1膜が優先
的に結合して半導体との接着力が弱まることが想定され
る。(Problems to be solved by the invention) Such electrodes include InP, GaAs, InGaAs.
It has been found that the adhesion force to ■-■ group compound semiconductors such as P is extremely weak. That is, the Ti film which is the adhesive layer has this m-
Although Ti exhibits inherently strong adhesion with group V compound semiconductors,
The T1 film, which has a strong getter effect, is responsible for the small amount of gas and moisture mainly consisting of hydrocarbon that remain in the vacuum equipment used when forming the film, and the extremely small amount of contaminants that coat the surface of this compound semiconductor. It is assumed that the bonding force with the semiconductor is weakened due to preferential bonding.
しかも、このTi膜を■−■族化合物半導体に被着する
と、この半導体の組成元素であるPならびにAs等と反
応してその界面に接着力の弱い変成層を形成することが
予想される。更に、他の元素より低温で解離し易いP及
びAsを含む■−V族化合物半導体表面にTi層を隣接
させた多層金属を被着して熱処理を施すと、前記変成層
を形成する度合いがますます進行すると考えられる。Moreover, when this Ti film is applied to a ■-■ group compound semiconductor, it is expected that it will react with the constituent elements of this semiconductor, such as P and As, to form a metamorphosed layer with weak adhesive strength at the interface. Furthermore, when a multilayer metal with a Ti layer adjacent to it is deposited on the surface of a ■-V group compound semiconductor containing P and As, which are more likely to dissociate at low temperatures than other elements, and then subjected to heat treatment, the degree of formation of the metamorphic layer increases. It is thought that this will continue to progress.
本発明は上記雑煮を除去する新規な半導体装置電極に関
し、特に半導体基板との接着力が強く作業性がよくひい
ては信頼性の高いものを提供することを目的とする。The present invention relates to a novel semiconductor device electrode for removing the above-mentioned contaminants, and in particular, an object of the present invention is to provide an electrode that has strong adhesion to a semiconductor substrate, is easy to work with, and is highly reliable.
(問題点を解決するための手段)
このため本発明に係る半導体素子電極では能動もしくは
受動素子をもつ半導体基板に隣接してAuもしくはAu
合金層を設け、こゝに接着層を含む複数の金属層を積層
する手法を採取する。(Means for Solving the Problem) For this reason, in the semiconductor element electrode according to the present invention, Au or Au is used adjacent to the semiconductor substrate having an active or passive element.
A method is adopted in which an alloy layer is provided and multiple metal layers including an adhesive layer are laminated thereon.
(作 用)
このように本発明では■−■族化合物半導体基板表面に
薄い金属層を被覆後、接着層を含む複数の金属層を堆積
して熱処理を施すと、接着力が著るしく改善されて強固
になる事実を基に完成したものである。(Function) In this way, in the present invention, after coating the surface of a ■-■ group compound semiconductor substrate with a thin metal layer, depositing a plurality of metal layers including an adhesive layer and performing heat treatment, the adhesive strength is significantly improved. It was completed based on the fact that it has been strengthened by
こ\で第1表により従来技術との接着強度の比較を明ら
かにするが、その試験法を先に記載する。Here, Table 1 will clarify the comparison of adhesive strength with the conventional technology, but the test method will be described first.
これにはスコッチテープ剥離法によっており、このテー
プに少しでも電極金属片が付着した場合はx印、何等付
着しない折はO印を記載した。尚実際の試験に当っては
スライド硝子に接着剤としてワックスを塗布し、こ\に
前記電極を堆積した■−V族化合物半導体基板であるウ
ェーハを載置して冷却して固定する。この場合綿棒でこ
すって気泡を追出すのは勿論である。この電極には約1
0CI!1のテープをはりつけてからその端部を引きは
がして電極残渣の付着状況をa祭した。This was done by the Scotch tape peeling method, and if any electrode metal pieces were attached to the tape, an x mark was written, and if no electrode metal pieces were attached, an O mark was written. In the actual test, a glass slide is coated with wax as an adhesive, and a wafer, which is a ①-V group compound semiconductor substrate on which the electrodes are deposited, is placed on the glass slide and then cooled and fixed. In this case, of course, remove air bubbles by rubbing with a cotton swab. This electrode has approximately 1
0CI! After attaching the tape No. 1, the end was peeled off to examine the adhesion of the electrode residue.
又基板の種類として示したInGaAsP基板1Pは厚
さ350μsのInP半導体基板に1p程度のInGa
AsPからなるエピタキシャル層を堆積したものであり
。In addition, the InGaAsP substrate 1P shown as a type of substrate is a 350 μs thick InP semiconductor substrate with about 1 p of InGa.
An epitaxial layer made of AsP is deposited.
又熱処理はオーミック電極の形成に(m−V族半導体基
板に形成する場合)適用する400℃〜450℃を勘棄
して不活性雰囲気430℃ 5分の処理を施したもので
ある。Further, the heat treatment was performed at 430°C for 5 minutes in an inert atmosphere, abandoning the 400°C to 450°C applied to the formation of ohmic electrodes (when forming them on m-V group semiconductor substrates).
第1表擾側鍍の比較
このようにAu層を■−V族化合物半導体基板表面に隣
接して形成し、更にTi、 Pt及びAu層を積層した
電極は従来の電極より明らかに接着強度が改善されてい
ることが明らかである。Comparison of the first side plate As shown above, the electrode in which the Au layer is formed adjacent to the surface of the ■-V group compound semiconductor substrate and the Ti, Pt, and Au layers are further laminated has clearly higher adhesion strength than the conventional electrode. It is clear that there has been an improvement.
尚このm−v族化合物半導体基板に隣接して形成するA
u層の厚さは100人〜2500人 が必要である。Note that A formed adjacent to this m-v group compound semiconductor substrate
The thickness of the U layer is required to be 100 to 2,500 people.
と言うのは100人未満の厚さではその効果が充分でな
く又2500Å以下であればその機能を発揮できること
が確認されており、経済的に高価な金属を必要以上被覆
することによってもたらされるコストアップを避ける。This is because it has been confirmed that the effect is not sufficient if the thickness is less than 100 Å, and that it can perform its function if it is less than 2,500 Å, and the cost caused by coating more than necessary with economically expensive metals. Avoid close-ups.
又Au単独層の外にはAuGe層も同様な効果をもたら
すことも確認済みである。It has also been confirmed that in addition to the Au single layer, an AuGe layer also provides the same effect.
このAμ層もしくはAuGe層に連続して形成するTi
層及びpt層は厚さ100人〜5000人 が適用可能
範囲であり、1000人が最も好ましい値である。又最
上層のAuはこゝに熱圧着する金属細線の種類Al。Ti formed continuously on this Aμ layer or AuGe layer
The applicable thickness of the layer and PT layer is 100 to 5,000 layers, with 1,000 layers being the most preferable value. Also, the top layer of Au is a type of Al thin metal wire that is bonded by thermocompression.
Cu、もしくはAu細線によりAl、Cu層など適当に
選択可能であり、pt層は複数種の金属層を積層した結
果、発生が予想される金属原子の拡散に対するバリヤ層
として動作する。An Al, Cu layer, etc. can be appropriately selected from Cu or Au thin wires, and the PT layer acts as a barrier layer against the diffusion of metal atoms that is expected to occur as a result of stacking a plurality of metal layers.
又Ti層は前述のようにゲッタ作用を発揮するのに加え
てpt及びAu層との接着を確実にする役割りを果すも
のでありこれをCr層と置換することは差しつかえない
ことを付記する。In addition, it should be noted that the Ti layer not only exhibits the getter function as mentioned above, but also plays a role in ensuring adhesion with the PT and Au layers, and that it can be replaced with the Cr layer. do.
(実施例) 図面を参照して本発明の実施例を詳述する。(Example) Embodiments of the present invention will be described in detail with reference to the drawings.
この例ではInGaAsPからなる半導体基板1に本発
明を適用するもので、この半導体基板1には図示してい
ないが、能動素子もしくは受動素子を形成済みである。In this example, the present invention is applied to a semiconductor substrate 1 made of InGaAsP, and although not shown, active elements or passive elements have already been formed on this semiconductor substrate 1.
この能動あるいは受動素子はその電極をこの半導体基板
の特定位置に配線し、こぎにいわゆるA1又はA1合金
からなるパッドを設け、この半導体基板をヒートシンク
にマウントし、更にステムにヒートシンクを固定しリー
ドと金属細線により電気的に接続して、このリードを使
用機器と接触して回路接続する。This active or passive element has its electrode wired to a specific position on this semiconductor substrate, a pad made of so-called A1 or A1 alloy is provided on the saw, this semiconductor substrate is mounted on a heat sink, and the heat sink is further fixed to the stem and the leads are connected. Electrical connections are made using thin metal wires, and the leads are brought into contact with the equipment used to connect the circuit.
このパッドとしての機能を果す本発明の電極はいわゆる
E−Gunを使用する真空蒸着法により連続して形成す
る。The electrode of the present invention, which functions as a pad, is continuously formed by a vacuum evaporation method using so-called E-Gun.
素子を形成したInGaAsP基板1にはレジストの空
あきパターンを設けこれを2XIP’torrを下限と
した真空蒸着装置内にセット後Au層2を500人Ti
層3を1000人、 pt層4を1000人更にAu層
5を5000人順次積層する。次に400℃乃至450
℃に保持した不活性(N2)雰囲気で約5分熱処理を施
し更にこのInGaAsP半導体基板1の裏側にも電極
(図示せず)を形成し、更に又積層した複数金属層にA
u6を5000人オーバーコートして半導体素子電極を
形成する。An open resist pattern was formed on the InGaAsP substrate 1 on which the device was formed, and after setting it in a vacuum evaporation apparatus with a lower limit of 2XIP'torr, an Au layer 2 was deposited with a thickness of 500 Ti.
Layer 3 is layered by 1000 layers, PT layer 4 is layered by 1000 layers, and Au layer 5 is layered by 5000 layers. Next, 400℃ to 450℃
A heat treatment was performed for about 5 minutes in an inert (N2) atmosphere maintained at ℃, an electrode (not shown) was formed on the back side of this InGaAsP semiconductor substrate 1, and A was applied to the laminated multiple metal layers.
Semiconductor element electrodes are formed by overcoating 5,000 layers of u6.
このオーバーコート後レジストをスペーサとするりフト
オフ法によってこの電極以外の積層した複数の金属層を
除去するが、これ以外の種々の慣用手段が適用可能であ
ることは言うまでもなく。After this overcoating, a plurality of laminated metal layers other than the electrodes are removed by a lift-off method using the resist as a spacer, but it goes without saying that various other conventional means can be applied.
更に半導体基板の導電型はPもしくはn型の何れでも採
用できる。Furthermore, the conductivity type of the semiconductor substrate can be either P or n type.
前述のように■−■族化合物半導体基板に隣接してAu
層もしくはAU合金層を設けると、極めて接着力が得ら
れることが判明したし、これを半導体素子の電極として
適用して外部リードとの接続゛を図れば信頼性の高い特
性が得られるにれはTi等の接着層の保有する優れた接
着力を利用した従来電極に発生した。変成層の形成が避
けられて半導体素子特性を長期にわたって十分発揮でき
るものである。As mentioned above, Au is placed adjacent to the ■-■ group compound semiconductor substrate.
It has been found that providing an AU alloy layer or an AU alloy layer can provide extremely strong adhesive strength, and if this is applied as an electrode of a semiconductor element to connect with an external lead, highly reliable characteristics can be obtained. This occurs in conventional electrodes that utilize the excellent adhesive strength of an adhesive layer such as Ti. The formation of metamorphic layers can be avoided and the semiconductor device characteristics can be fully exhibited over a long period of time.
図は本発明に係る半導体素子電極の断面図である。 The figure is a cross-sectional view of a semiconductor element electrode according to the present invention.
Claims (1)
AuもしくはAu合金からなる層を設け、こゝに接着層
を含む複数の金属層を積層することを特徴とする半導体
素子電極。A semiconductor element electrode characterized in that a layer made of Au or an Au alloy is provided adjacent to the surface of a semiconductor substrate having an active or passive element, and a plurality of metal layers including an adhesive layer are laminated thereon.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61241391A JPS6395661A (en) | 1986-10-13 | 1986-10-13 | Semiconductor element electrode |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61241391A JPS6395661A (en) | 1986-10-13 | 1986-10-13 | Semiconductor element electrode |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6395661A true JPS6395661A (en) | 1988-04-26 |
Family
ID=17073582
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61241391A Pending JPS6395661A (en) | 1986-10-13 | 1986-10-13 | Semiconductor element electrode |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6395661A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0508618A2 (en) * | 1991-03-26 | 1992-10-14 | AT&T Corp. | Method of making ohmic contact to a III-V semiconductor device |
JP2007533133A (en) * | 2004-04-07 | 2007-11-15 | ティンギ テクノロジーズ プライベート リミテッド | Fabrication of reflective layer on semiconductor light emitting diode |
JP2007535804A (en) * | 2004-03-15 | 2007-12-06 | ティンギ テクノロジーズ プライベート リミテッド | Semiconductor device manufacturing |
US8004493B2 (en) | 2007-06-08 | 2011-08-23 | Apple Inc. | Methods and systems for providing sensory information to devices and peripherals |
JP2011199031A (en) * | 2010-03-19 | 2011-10-06 | Denso Corp | Semiconductor device, and method of manufacturing the same |
US8034643B2 (en) | 2003-09-19 | 2011-10-11 | Tinggi Technologies Private Limited | Method for fabrication of a semiconductor device |
US8067269B2 (en) | 2005-10-19 | 2011-11-29 | Tinggi Technologies Private Limted | Method for fabricating at least one transistor |
US8124994B2 (en) | 2006-09-04 | 2012-02-28 | Tinggi Technologies Private Limited | Electrical current distribution in light emitting devices |
-
1986
- 1986-10-13 JP JP61241391A patent/JPS6395661A/en active Pending
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0508618A2 (en) * | 1991-03-26 | 1992-10-14 | AT&T Corp. | Method of making ohmic contact to a III-V semiconductor device |
JPH04320387A (en) * | 1991-03-26 | 1992-11-11 | American Teleph & Telegr Co <Att> | Manufacture of article having semiconductor element |
US8034643B2 (en) | 2003-09-19 | 2011-10-11 | Tinggi Technologies Private Limited | Method for fabrication of a semiconductor device |
JP2007535804A (en) * | 2004-03-15 | 2007-12-06 | ティンギ テクノロジーズ プライベート リミテッド | Semiconductor device manufacturing |
JP2007533133A (en) * | 2004-04-07 | 2007-11-15 | ティンギ テクノロジーズ プライベート リミテッド | Fabrication of reflective layer on semiconductor light emitting diode |
US8067269B2 (en) | 2005-10-19 | 2011-11-29 | Tinggi Technologies Private Limted | Method for fabricating at least one transistor |
US8124994B2 (en) | 2006-09-04 | 2012-02-28 | Tinggi Technologies Private Limited | Electrical current distribution in light emitting devices |
US8004493B2 (en) | 2007-06-08 | 2011-08-23 | Apple Inc. | Methods and systems for providing sensory information to devices and peripherals |
US8619050B2 (en) | 2007-06-08 | 2013-12-31 | Apple Inc. | Methods and systems for providing sensory information to devices to determine an orientation of a display |
US8830169B2 (en) | 2007-06-08 | 2014-09-09 | Apple Inc. | Methods and systems for providing sensory information to devices and peripherals |
JP2011199031A (en) * | 2010-03-19 | 2011-10-06 | Denso Corp | Semiconductor device, and method of manufacturing the same |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100286151B1 (en) | Integrated circuit packages, lead frames, and their manufacture | |
US5675177A (en) | Ultra-thin noble metal coatings for electronic packaging | |
JP3271475B2 (en) | Electrical element joining material and joining method | |
JP2983486B2 (en) | Semiconductor substrate having a brazing material layer | |
US6147403A (en) | Semiconductor body with metallizing on the back side | |
CA1224886A (en) | Semiconductor device and process for producing the same | |
US6203926B1 (en) | Corrosion-free multi-layer conductor | |
JPS5932055B2 (en) | Method for manufacturing a semiconductor device having contacts | |
JPS6395661A (en) | Semiconductor element electrode | |
US6653738B2 (en) | Semiconductor device | |
US3544704A (en) | Bonding islands for hybrid circuits | |
US6548386B1 (en) | Method for forming and patterning film | |
JP2000269583A (en) | Semiconductor light emitting device and manufacture thereof | |
JPS6074539A (en) | Submount for optical semiconductor element | |
US3840982A (en) | Contacts for semiconductor devices, particularly integrated circuits, and methods of making the same | |
US11798807B2 (en) | Process for producing an electrical contact on a silicon carbide substrate | |
JPS592175B2 (en) | semiconductor equipment | |
JPS60176231A (en) | Electrode forming process of compound semiconductor element | |
JP2950285B2 (en) | Semiconductor element and method for forming electrode thereof | |
JPH0793329B2 (en) | How to fix semiconductor pellets | |
JPS6129142B2 (en) | ||
JPH03246945A (en) | Semiconductor device | |
JPH07130790A (en) | Construction of electrode of semiconductor device | |
JPH04120734A (en) | Manufacture of semiconductor device | |
JPH038371A (en) | Semiconductor device |